CN102583225A - Fabricating method for one-dimensional large-scale multistage-step structure - Google Patents
Fabricating method for one-dimensional large-scale multistage-step structure Download PDFInfo
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- CN102583225A CN102583225A CN2012100611133A CN201210061113A CN102583225A CN 102583225 A CN102583225 A CN 102583225A CN 2012100611133 A CN2012100611133 A CN 2012100611133A CN 201210061113 A CN201210061113 A CN 201210061113A CN 102583225 A CN102583225 A CN 102583225A
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Abstract
The invention relates to a fabricating method for a one-dimensional large-scale multistage-step structure. The fabricating method comprises the steps that: a barrier layer is deposited on a substrate; first photoresist is coated, and a first window is formed by photoetching; the barrier layer in the first window is etched, and the first photoresist is removed; second photoresist is coated, a second window is formed by photoetching and is opposite to the first window, and the width of the second window is less than that of the first window; the substrate in the second widow is etched, a first step is formed on the substrate, and the second photoresist is removed; the substrate is etched by adopting the barrier layer as a mask, and a second step is formed on the substrate; and the barrier layer is removed. According to the invention, the one barrier layer and a plurality of photoresist processes are adopted, the multistage steps are formed on the substrate, and the height of the steps can reach a micrometer level and even a nanometer level, so that the performance of a one-dimensional large-scale component is improved. According to the invention, a sacrificial layer is adopted for removing residues and polymers in the etching process.
Description
Technical field
The present invention relates to technical field of semiconductors, the preparation method of the multistage ledge structure of particularly a kind of one dimension large scale.
Background technology
Optics is one of the earliest and the most active field of microelectromechanical systems (MEMS) technical application, and the typical application field comprises digital light projection, the demonstration of full color numeral, tunable light source and sensor, fiber-optical switch, free-space communication etc.
Micro-electronic mechanical system technique is applied in optical field has its distinctive advantage.Because photon almost do not have quality, and the power that is applied on the micro-structural is very little, and the formed device of the little processing of silicon only and these photons interaction is arranged, so they are most suitable on optical applications.And the encapsulation of light microelectromechanical systems is also simple relatively, guarantees in the shell of printing opacity that they do not receive particle, air-flow, the directly interference of environmental factors such as contact as long as light microelectromechanical systems parts are sealed in.
Certainly, be applied to optical field to micro-electronic mechanical system technique and also face some challenges.Preparation polishing level and smooth minute surface difficulty relatively normally on micromechanical component for example; Such as producing the compound that is difficult to removal in some large-sized etching processes, cause and to adopt special PROCESS FOR TREATMENT again.
In field of optical applications, fiber waveguide is one of modal device, is different from other common on IC production line devices, and it generally has bigger yardstick on a certain direction, even length is more than 10mm, but other direction yardsticks are micron even nanometer scale.In the etching process of these one dimension large scale devices, tend to stay some residues or produce some polymer.These residues or polymer can't be removed clean through common cleaning step, can influence normally carrying out of subsequent technique, even can cause unacceptable consequence.
Summary of the invention
The preparation method that the purpose of this invention is to provide the multistage ledge structure of a kind of one dimension large scale to form one dimension large scale device, is removed the residue and the polymer that in etching process, stay simultaneously.
Technical solution of the present invention is the preparation method of the multistage ledge structure of a kind of one dimension large scale, may further comprise the steps:
Deposition one deck barrier layer on substrate;
Apply first photoresist, photoetching forms first window;
First photoresist is removed on barrier layer in etching first window;
Apply second photoresist, photoetching forms second window, and said second window and width corresponding with first the window's position is less than first window;
Substrate in etching second window obtains first step on substrate, remove second photoresist;
With the barrier layer is the mask etching substrate, on substrate, obtains second step;
Remove the barrier layer.
As preferably: after removing second photoresist, further comprising the steps of:
On substrate, form sacrifice layer through thermal response;
Wet etching is removed sacrifice layer.
As preferably: the material of said substrate is silicon or germanium.
As preferably: the material on said barrier layer is oxide or nitride or nitrogen oxide.
As preferably: said barrier layer is a single or multiple lift.
As preferably: the material of said sacrifice layer is oxide or nitride or nitrogen oxide.
As preferably: the height of said first step is the 0.01-100 micron.
As preferably: the height of said second step is the 0.01-100 micron.
Compared with prior art; The present invention adopts barrier layer and photoresist to form multistage step as the etching barrier layer that step forms; The height of step can reach micron dimension even nanometer scale, thereby has improved the performance of one dimension large scale device, and technology is simple; Adopt sacrifice layer simultaneously, remove the residue and the polymer that produce in the etching process.
Description of drawings
Fig. 1 is the flow chart of the preparation method of the multistage ledge structure of one dimension large scale of the present invention.
Fig. 2 a-2l is the profile of each processing step in the preparation method of the multistage ledge structure of one dimension large scale of the present invention.
The specific embodiment
The present invention below will combine accompanying drawing to do further to detail:
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture is not to draw according to equal proportion, and said sketch map is instance, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and step.
Fig. 1 shows the flow chart of the preparation method of the multistage ledge structure of one dimension large scale of the present invention.
See also shown in Figure 1ly, in the present embodiment, the preparation method of the multistage ledge structure of a kind of one dimension large scale may further comprise the steps:
In step 101, shown in Fig. 2 a, deposition one deck barrier layer 201 on substrate 200, the material of said substrate 200 is silicon or germanium, also can be other semi-conducting materials.The material on said barrier layer 201 is oxide or nitride or nitrogen oxide, material that substrate is had high etching selection ratio such as silica or silicon nitride for example, and barrier layer 201 is individual layer or is multilayer;
In step 102, shown in Fig. 2 b, apply first photoresist 202, shown in Fig. 2 c, photoetching forms the first window 202a;
In step 103, shown in Fig. 2 d, first photoresist 202 is removed on the barrier layer 201 in the etching first window 202a, and remaining barrier layer 201 is as the mask of subsequent etching;
In step 104, shown in Fig. 2 e, apply second photoresist 203, shown in Fig. 2 f, photoetching forms the second window 203a, and the said second window 203a and width corresponding with the position of the first window 202a is less than the first window 202a;
In step 105, shown in Fig. 2 g, the substrate 200 in the etching second window 203a obtains first step 204 on substrate, shown in Fig. 2 h, remove second photoresist 203; The height h1 of said first step 204 is the 0.01-100 micron, for example 0.2 micron, 1 micron, 8 microns and 20 microns.In the forming process of multistage step, easily at the sidewall formation residue and the polymer of step, after etching, can form the residual of silicon or germanium in the etching process, the etching pattern is produced fatal influence.Therefore, after removing second photoresist, also selectively adopt following steps; Shown in Fig. 2 i, thermal response one deck sacrifice layer 205 on substrate 200 is like thermal oxidation process; If adopt silicon materials as substrate, then thermal oxide forms silica, in the process of removing silica subsequently; Remove residue and polymer simultaneously, shown in Fig. 2 j, wet etching is removed sacrifice layer 205; The material of said sacrifice layer 205 is oxide or nitride or nitrogen oxide, for example silica or silicon nitride;
In step 106; Shown in Fig. 2 k; With barrier layer 201 is mask etching substrate 200, on substrate 200, forms second step 206, and first step 204 is synchronously downward etching same depth in etching process; The height h2 of said second step 206 is the 0.01-100 micron, for example 0.1 micron, 0.5 micron, 4 microns and 5 microns;
In step 107, shown in Fig. 2 l, remove barrier layer 201, obtain the multistage step on the substrate 200 thus.
The present invention adopts one deck barrier layer and photoetching process repeatedly; On substrate, form multistage step; The height of step can reach micron dimension even nanometer scale, thereby has improved the performance of one dimension large scale device, also adopts sacrifice layer to remove residue and polymer in etching process.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (8)
1. the preparation method of the multistage ledge structure of one dimension large scale is characterized in that, may further comprise the steps:
Deposition one deck barrier layer on substrate;
Apply first photoresist, photoetching forms first window;
First photoresist is removed on barrier layer in etching first window;
Apply second photoresist, photoetching forms second window, and said second window and width corresponding with first the window's position is less than first window;
Substrate in etching second window obtains first step on substrate, remove second photoresist;
With the barrier layer is the mask etching substrate, on substrate, obtains second step;
Remove the barrier layer.
2. the preparation method of the multistage ledge structure of one dimension large scale according to claim 1 is characterized in that, and is after removing second photoresist, further comprising the steps of:
On substrate, form sacrifice layer through thermal response;
Wet etching is removed sacrifice layer.
3. the preparation method of the multistage ledge structure of one dimension large scale according to claim 1 is characterized in that: the material of said substrate is silicon or germanium.
4. the preparation method of the multistage ledge structure of one dimension large scale according to claim 1 is characterized in that: the material on said barrier layer is oxide or nitride or nitrogen oxide.
5. the preparation method of the multistage ledge structure of one dimension large scale according to claim 1 is characterized in that: said barrier layer is a single or multiple lift.
6. the preparation method of the multistage ledge structure of one dimension large scale according to claim 2 is characterized in that: the material of said sacrifice layer is oxide or nitride or nitrogen oxide.
7. the preparation method of the multistage ledge structure of one dimension large scale according to claim 1 is characterized in that: the height of said first step is the 0.01-100 micron.
8. the preparation method of the multistage ledge structure of one dimension large scale according to claim 1 is characterized in that: the height of said second step is the 0.01-100 micron.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298459A (en) * | 2016-10-10 | 2017-01-04 | 武汉新芯集成电路制造有限公司 | The forming method of step wedge filter layer |
| CN108557758A (en) * | 2018-02-08 | 2018-09-21 | 南京大学 | A kind of method of cycle alternation etching homogeneity multistage slope step guiding growth nano-wire array |
| CN111137846A (en) * | 2019-12-24 | 2020-05-12 | 中国电子科技集团公司第十三研究所 | Preparation method of micron-level step height standard sample block |
| WO2024045268A1 (en) * | 2022-08-29 | 2024-03-07 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure, and semiconductor structure |
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| US20020055253A1 (en) * | 2000-11-09 | 2002-05-09 | Joachim Rudhard | Method for producing a micromechanical structure and a micromechanical structure |
| US20020164833A1 (en) * | 2001-05-07 | 2002-11-07 | Dong-Il Cho | Method of fabricating an electrostatic vertical and torsional actuator using one single-crystalline silicon wafer |
| CN101388364A (en) * | 2007-09-13 | 2009-03-18 | 李刚 | Electric isolation region forming method adopting low temperature process, single chip integration method and chip |
| CN101648695A (en) * | 2009-09-07 | 2010-02-17 | 北京时代民芯科技有限公司 | MEMS bulk silicon technological method for transferring mask layer three-dimensional structure |
| CN102004281A (en) * | 2010-09-10 | 2011-04-06 | 上海宏力半导体制造有限公司 | Manufacture method of optical waveguide device with low roughness |
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2012
- 2012-03-09 CN CN201210061113.3A patent/CN102583225B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20020055253A1 (en) * | 2000-11-09 | 2002-05-09 | Joachim Rudhard | Method for producing a micromechanical structure and a micromechanical structure |
| US20020164833A1 (en) * | 2001-05-07 | 2002-11-07 | Dong-Il Cho | Method of fabricating an electrostatic vertical and torsional actuator using one single-crystalline silicon wafer |
| CN101388364A (en) * | 2007-09-13 | 2009-03-18 | 李刚 | Electric isolation region forming method adopting low temperature process, single chip integration method and chip |
| CN101648695A (en) * | 2009-09-07 | 2010-02-17 | 北京时代民芯科技有限公司 | MEMS bulk silicon technological method for transferring mask layer three-dimensional structure |
| CN102004281A (en) * | 2010-09-10 | 2011-04-06 | 上海宏力半导体制造有限公司 | Manufacture method of optical waveguide device with low roughness |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298459A (en) * | 2016-10-10 | 2017-01-04 | 武汉新芯集成电路制造有限公司 | The forming method of step wedge filter layer |
| CN108557758A (en) * | 2018-02-08 | 2018-09-21 | 南京大学 | A kind of method of cycle alternation etching homogeneity multistage slope step guiding growth nano-wire array |
| CN108557758B (en) * | 2018-02-08 | 2020-04-28 | 南京大学 | Method for growing nanowire array by guiding steps of circularly alternately etching homogeneous multistage slope surface |
| CN111137846A (en) * | 2019-12-24 | 2020-05-12 | 中国电子科技集团公司第十三研究所 | Preparation method of micron-level step height standard sample block |
| WO2024045268A1 (en) * | 2022-08-29 | 2024-03-07 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure, and semiconductor structure |
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| CN102583225B (en) | 2015-05-06 |
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