CN102714223A - Oxide-nitride-oxide stack having multiple oxynitride layers - Google Patents
Oxide-nitride-oxide stack having multiple oxynitride layers Download PDFInfo
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- CN102714223A CN102714223A CN2012800001075A CN201280000107A CN102714223A CN 102714223 A CN102714223 A CN 102714223A CN 2012800001075 A CN2012800001075 A CN 2012800001075A CN 201280000107 A CN201280000107 A CN 201280000107A CN 102714223 A CN102714223 A CN 102714223A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
Abstract
A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.
Description
The cross reference of related application
The application's case is the U. S. application case the 11/811st in the application of applying on June 13rd, 2007 that coexists; No. 958 the part application case that continues; U. S. application case the 11/811st; Advocate the priority of No. the 60/931st, 947, the U.S. Provisional Patent Application case of application on May 25th, 2007 according to 35U.S.C.119 (e) No. 958, both all are incorporated herein by reference for this.
Technical field
The present invention is about semiconductor machining, and more particular about oxide-nitride thing with improvement or oxide-nitride thing-oxide stack of oxynitride layer and forming method thereof.
Background technology
Non-volatility semiconductor memory body (such as division gate electrode quick flash memory body) typically uses the floating gate polar form field effect electric crystal that piles up, and wherein electronics is induced in the float gate of the memory cell that the body region ground connection of treating the substrate of formation memory cell by control grid being applied bias voltage and making above stylizes.
Use oxide-nitride thing-oxide (ONO) to pile up as the electric charge storage layer in silicon-oxide-nitride--oxide-silicon (SONOS) electric crystal or as float gate in the division gate electrode quick flash memory body and the insulating barrier between the control grid.
Fig. 1 is the partial cross sectional view of the intermediate structure of semiconductor device 100 (such as memory device), and this semiconductor device 100 has and comprises that the convention ONO that on the surface 106 of silicon substrate 108, forms according to prior art method piles up 104 SONOS gate and piles up or structure 102.In addition, device 100 typically further comprises the diffusion region 110 (such as source electrode and drain area) that one or more and gate pile up aligning and separated by passage area 112.In brief, SONOS structure 102 is included in ONO and piles up on 104 and to form and pile up 104 polysilicon (polycrystalline) gate layers 114 that contact with ONO.Polycrystalline gate layer (poly gate layer) 114 piles up 104 by ONO to be separated or electric insulation with substrate 108.ONO piles up 104 and generally comprises the nitride of bottom oxide skin(coating) 116, the Charge Storage that is used as device 100 or memory body layer or top high-temperature oxide (HTO) layer 120 of oxynitride layer 118 and covering nitride or oxynitride layer.
A problem of convention SONOS structure 102 and forming method thereof is that the data hold facility of nitride or oxynitride layer 118 is relatively poor, leakage current restraint device 100 life-spans and/or its use in some application of this layer because of passing this layer.
The stoichiometric amount that another problem of convention SONOS structure 102 and forming method thereof is oxynitride layer 118 both also non-the best of heterogeneity on the thickness of this layer.Particular it, oxynitride layer 118 usually uses single processing gas mixture and fixing or constant process condition to form or deposit in one step, in the hope of obtaining the conforming layer that on the thickness than thick-layer relatively, has higher nitrogen and higher oxygen concentration.Yet because top and bottom effect, this measure causes nitrogen, oxygen and silicon concentration in whole convention oxynitride layer 118, to change.The top effect is caused by the order of handling gas disconnection after deposition.Particular it, siliceous processing gas (such as silane) typically at first breaks off, and produces oxygen and/or amount of nitrides height and the low top section of silicone content in the oxynitride layer 118.Similarly, the bottom effect causes by introducing the order of processing gas with initial deposition.Particular it, the deposition of oxynitride layer 118 typically after annealing (annealing) step, thereby when deposition manufacture process begins, produce ammonia (NH
3) peak value or relative higher concentration and produce oxygen in the oxynitride layer and silicone content is low and nitrogen content is high base section.The bottom effect is also owing to the surface nucleation phenomenon, and wherein available oxygen and silicon are preferential in the initial treatment gas mixture reacts and do not facilitate the formation of oxynitride layer with silicon at substrate surface.Therefore, with ONO pile up 104 memory devices 100 processed Charge Storage characteristic and particular stylize and erase speed and data preservation affect adversely.
Therefore, to have utilize oxynitride layer as represent improvement stylizing and there are needs in memory device that the ONO of the memory body layer of erase speed and data preservation piles up.Further formation is had method and the processing procedure that the ONO of the oxynitride layer of the nitrogen oxide stoichiometric amount that represents improvement piles up and have needs.
Summary of the invention
The present invention provides a kind of semiconductor device that comprises silicon-oxide-nitrogen oxide-oxide-silicon structure and forming method thereof.In an instantiation, this structure comprises: in the tunnel oxide that comprises on the substrate surface of silicon; The multilayer electric charge storage layer; It comprises oxygen enrichment first oxynitride layer on this tunnel oxide; Wherein the stoichiometric amount of this first oxynitride layer composition causes it not have trap in fact; And oxygen deprivation second oxynitride layer on this first oxynitride layer, wherein the stoichiometric amount of this second oxynitride layer is formed and is caused its trap densification; Barrier oxide layer on this second oxynitride layer; And the siliceous gate layer on this barrier oxide layer.
In an instantiation, this method comprises: (i) on the silicon-containing layer of substrate, form tunnel oxide; (ii) by deposition oxygen enrichment first oxynitride layer on this tunnel oxide (wherein the stoichiometric amount of this first oxynitride layer form cause it not have trap in fact) and on this first oxynitride layer deposition oxygen deprivation second oxynitride layer (wherein the stoichiometric amount of this second oxynitride layer form cause its trap fine and close) form the multilayer electric charge storage layer; (iii) on this second oxynitride layer, form the barrier oxide layer; Reach and (iv) on this barrier oxide layer, form siliceous gate layer.
Description of drawings
The calcspar of the cross-sectional side view of the intermediate structure of the memory device that oxide-nitride thing-oxide (ONO) that Fig. 1 (prior art) forms according to prior art method for explanation has piles up;
One instantiation has the calcspar of cross-sectional side view of a part of the semiconductor device of the silicon-oxide-nitrogen oxide-oxide-silicon structure that comprises the multilayer electric charge storage layer to Fig. 2 according to the present invention for explanation;
Fig. 3 forms the flow chart of the method for the oxide-nitrogen oxide-oxide structure that comprises the multilayer electric charge storage layer for an instantiation according to the present invention;
Fig. 4 compares for showing with the memory device that uses convention memory body layer, uses the figure of the improvement of memory device aspect data preservation of memory body layer formed according to the present invention;
Fig. 5 forms the flow chart of the method for the oxide-nitrogen oxide-oxide structure that comprises the multilayer electric charge storage layer for another instantiation according to the present invention;
Fig. 6 is the energy band diagram with the convention memory device that stylizes of ONO structure; And
Fig. 7 A and Fig. 7 B comprise that for an instantiation according to the present invention the memory device of multilayer electric charge storage layer is at the energy band diagram that stylizes after reaching before.
Embodiment
The present invention is substantially about a kind of device and manufacturing approach thereof that comprises the silicon-oxide-nitrogen oxide-oxide-silicon gate structure that comprises the multilayer electric charge storage layer.Gate structure and method are particularly useful for forming the memory body layer in the memory device, such as the memory electric crystal.
In the following description, set forth a large amount of specific detail for explanatory purposes so that provide to thorough of the present invention.Yet it is to show and easy knowledge that structure of the present invention and method can be implemented under these specific detail of nothing those who familiarize themselves with the technology.In other cases, well known structures and technology do not show in detail or show to avoid unnecessarily obscuring the understanding to this description with block diagram form.
Mention in the description that " instantiation (one embodiment) " or " instantiation (an embodiment) " means the described special characteristic of combination instantiation, structure or characteristic and be included at least one instantiation.May not all refer to same instantiation at the different local phrases " in an instantiation (in one embodiment) " that occur of specification.Term as used herein " coupling (to couple) " can comprise direct connection and connect both indirectly via one or more intervention package.
In brief, this method relate to form comprise oxygen, nitrogen and/or silicon with variable concentrations a plurality of oxynitride layers (such as silicon oxynitride (Si
2N
2O) multilayer electric charge storage layer layer).Nitride in oxynitride layer and the convention ONO structure or oxynitride layer are compared under higher temperature and are formed, and each layer uses the different disposal gas mixture and/or with different flow rates formation.Generally speaking, oxynitride layer comprises top oxynitride layer and bottom oxynitride layer at least.In some instantiation; The stoichiometric amount of layer is formed through adjustment or selection so that bottom or bottom nitrogen oxide have higher oxygen and silicone content; And the top oxynitride layer has higher silicon and higher nitrogen concentration and oxygen concentration is lower, to produce oxygen deprivation, persilicic nitride or nitrogen oxide.Silicon-rich and oxygen enrichment bottom oxynitride layer do not damage device speed or formula with initial (life-span begins) difference of erasing between the voltage under the minimizing store charge lose.Silicon-rich, oxygen deprivation top oxynitride layer increase stylizing and the difference of erasing between the voltage of memory device, the operation lifetime of improved device speed, enhancing data preservation and extension fixture thus.In some instantiations, Silicon-rich, oxygen deprivation top oxynitride layer can further comprise through selecting to increase the wherein carbon of the concentration of trap number.
According to circumstances, between top oxynitride layer and the bottom oxynitride layer ratio of thickness can through select with promote to use dry type or wet oxidation form first oxide layer after on the tunnel of silicon-oxide-nitrogen oxide-oxide-silicon gate structure or first oxide layer, form oxynitride layer.
To silicon-oxide-nitrogen oxide-oxide-silicon structure and manufacturing approach thereof according to various instantiations of the present invention be described in more detail with reference to Fig. 2 to Fig. 4 at present.
Fig. 2 has the calcspar of cross-sectional side view of a part of the semiconductor memory body device 200 of the silicon-oxide-nitrogen oxide-oxide-silicon gate structure that comprises the multilayer electric charge storage layer according to an instantiation for explanation.With reference to Fig. 2, memory device 200 comprises that the silicon-oxide-nitrogen oxide-oxide-silicon gate structure or the gate of the multilayer electric charge storage layer 204 that forms on the surface 206 that is included in the silicon layer on substrate or the silicon substrate 208 pile up 202.In addition, device 200 further comprises the diffusion region 210 (such as source electrode and drain area or structure) that one or more and gate pile up 202 alignings and separated by passage area 212.Generally speaking, silicon-oxide-nitrogen oxide-oxide-silicon gate structure comprises the part of siliceous gate layer (such as the polysilicon or the polycrystalline gate layer 214 that on multilayer electric charge storage layer 204, form and contact with multilayer electric charge storage layer 204) and silicon layer or substrate 208.Polycrystalline gate layer 214 is separated or electric insulation with substrate 208 by multilayer electric charge storage layer 204.Silicon-oxide-nitrogen oxide-oxide-silicon structure comprises that making gate pile up 202 separates with passage area 212 or thin bottom oxide skin(coating) or tunnel oxide 216, top or barrier oxide layer 218 and the multilayer electric charge storage layer 204 of electric insulation.Reach as stated as shown in Figure 2, multilayer electric charge storage layer 204 comprises at least two oxynitride layers, comprises top oxynitride layer 220A and bottom oxynitride layer 220B.
The bottom oxide skin(coating) of silicon-oxide-nitrogen oxide-oxide-silicon structure or tunnel oxide 216 generally comprise about 15 dust (angstrom;
) to about
And it is about in some instantiations
Relatively thin silicon dioxide (SiO
2) layer.Tunnel oxide 216 can form or deposition by any suitable method (comprise for example heat growth or use the chemical vapor deposition (CVD) deposition).Generally speaking, the thermal oxidation in the tunnel oxide use oxygen environment forms or grows.In an instantiation; Processing procedure relates to the dry type method for oxidation; Wherein substrate 208 is placed in deposition or the process cavity, be heated to about 700 ℃ to about 850 ℃ temperature, and be exposed to oxygen and continue based on the selected predetermined amount of time of the desired thickness of finished product tunnel oxide 216.In another instantiation, tunnel oxide is used oxygen (O on substrate under the temperature at least 1000 ℃ in ISSG (situ steam produces (In-Situ Steam Generation)) chamber
2) and hydrogen (H
2) between reaction utilize free-radical oxidation to grow.The exemplary processing time is about 10 minutes to about 100 minutes.Oxidation can under atmospheric pressure or under low pressure be carried out.
As stated; The multilayer electric charge storage layer generally comprises at least two and has the oxynitride layers that Different Silicon, oxygen and nitrogen are formed, and can have approximately
to
approximately and in some instantiation the general thickness of
approximately.In an instantiation, oxynitride layer uses the silicon source (such as silane (SiH in the low pressure chemical vapor deposition processing procedure
4), chlorosilane (SiH
3Cl), dichlorosilane or DCS (SiH
2Cl
2), tetrachloro silicane (SiCl
4) or two tri-butylamine base silane (BTBAS)), nitrogenous source is (such as nitrogen (N
2), ammonia (NH
3), nitrogen peroxide (NO
3) or nitrous oxide (N
2O)) and oxygen-containing gas (such as oxygen (O
2) or N
2O) form or deposit.Perhaps, can use the hydrogen gas of deuterium exchange, comprise and for example use ammonia, deuterated (ND
3) replacement NH
3With deuterium replace hydrogen advantageously passivation increase NBTI (Negative Bias Temperature Instability (Negative Bias Temperature the Instability)) life-span of device thus at the outstanding key of the Si at silicon-oxide interface place.
For example, bottom or bottom oxynitride layer 220B can by following on tunnel oxide 216 deposition: substrate 208 be placed in the deposition chambers and introduce comprise N
2O, NH
3And the processing gas of DCS, chamber is maintained under about 5 millitorrs (mT) to the pressure of about 500mT, and make substrate maintain about 700 ℃ to about 850 ℃ and in some instantiation at least about continuing about 2.5 minutes about 20 minutes time extremely under 760 ℃ the temperature.Particular it, handle gas and can comprise with about 8: 1 N to about 1: 8 ratio mixed
2O and NH
3First admixture of gas and with about 1: 7 DCS and NH to about 7: 1 ratio mixed
3Second admixture of gas, and can about 5 standard cube centimeters per minute introduce to the flow rate of about 200 standard cube centimeters per minute (sccm).Found produce under these conditions or the oxynitride layer of deposition produce reduce stylize the back and erase after Silicon-rich, the oxygen enrichment bottom oxynitride layer 220B of loss of charge rate (its in preservation mode with small voltage skew performance).
In some instantiations, the top oxynitride layer 220A of Silicon-rich, rich nitrogen and oxygen deprivation can use processing gas on the oxynitride layer 220B of bottom, to deposit in the CVD processing procedure, and this processing gas bag is drawn together with about 7: 1 BTBAS and the ammonia (NH to about 1: 7 ratio mixed
3), further to comprise through selecting to increase the wherein carbon of the concentration of trap number.Selected concentration of carbon in second oxynitride layer can comprise about 5% to about 15% concentration of carbon.
In some instantiation, top oxynitride layer 220A in regular turn with form the used identical instrument of bottom oxynitride layer 220B in substantially do not destroy the vacuum deposit of deposition chambers.In some instantiation, top oxynitride layer 220A does not substantially change the situation deposit of the temperature of oxynitride layer 220B heats substrate 208 in the deposition bottom.In an instantiation, top oxynitride layer 220A oxynitride layer 220B's in deposition bottom is back by with respect to DCS/NH
3Admixture of gas reduces N
2O/NH
3The flow rate of admixture of gas is come in regular turn with the required ratio that admixture of gas is provided and is deposited at once, to produce the top oxynitride layer 220A of Silicon-rich, rich nitrogen and oxygen deprivation.
In some instantiation, another oxide or oxide skin(coating) (not shown in the figures at these) pile up after 202 at the formation gate and use steam oxidation to form in the zones of different on substrate 208 or in device.In this instantiation, the top oxynitride layer 220A of silicon-oxide-nitrogen oxide-oxide-silicon structure and top or barrier oxide layer 218 be steam annealing during the steam oxidation processing procedure advantageously.Particular it; The quality of steam annealing improvement top or barrier oxide layer 218; Reduce near near the trap number that forms of end face end face and the top oxynitride layer 220A of lower floor of barrier oxide layer; Reduce thus or eliminate the electric field that possibly on the barrier oxide layer, form in addition in fact, this electric field possibly cause that electric charge carrier preserves through its refluence and the data or the electric charge that influence unfriendly in the electric charge storage layer.
The suitable thickness of having found bottom oxynitride layer 220B is about
extremely about
, and has found that the ratio of thickness between bottom and the top oxynitride layer is about 1: 6 to about 6: 1 and in some instantiation, is at least about 1: 4.
The top of silicon-oxide-nitrogen oxide-oxide-silicon structure or barrier oxide layer 218 comprise approximately
To about
And it is about in some instantiation
Relative thicker SiO
2Layer.Top or barrier oxide layer 218 can form or deposition by any suitable method (comprise for example heat growth or use the CVD deposition).In an instantiation, top or barrier oxide layer 218 are for using the high-temperature oxide (HTO) of CVD processing procedure deposition.Generally speaking, deposition manufacture process relates at about 50mT and in deposition chambers, substrate 208 is exposed to silicon source (such as silane, chlorosilane or dichlorosilane) and oxygen-containing gas (such as O to the pressure of about 1000mT
2Or N
2O) continue about 10 minutes to about 120 minutes time, make simultaneously substrate maintain about 650 ℃ to about 850 ℃ temperature.
In some instantiation, top or barrier oxide layer 218 with form oxynitride layer 220A, the used identical instrument of 220B in deposition in regular turn.In some instantiation, oxynitride layer 220A, 220B and top or barrier oxide layer 218 with growth tunnel oxide 216 used identical instruments in form or deposition.Suitable instrument comprises for example can be available from AVIZA technology (Scotts Valley, ONO AVP California).
To form or make the folded method of silicon-oxide-nitrogen oxide-oxide-silicon stack according to an instantiation with reference to the flow chart description of Fig. 3 at present.
With reference to Fig. 3, this method starts from and on substrate 208 lip-deep silicon-containing layers, forms silicon-oxide-nitrogen oxide-oxide-silicon gate and pile up 202 first oxide skin(coating) (such as tunnel oxide 216) (300).Then, on the surface of first oxide layer, form first or bottom oxynitride layer 220B (302) of the multilayer electric charge storage layer 204 that comprises nitrogen oxide.As stated, this first or bottom oxynitride layer 220B can use by the CVD processing procedure and comprise that ratio and flow rate are through the N of adjustment with oxynitride layer that Silicon-rich and oxygen enrichment are provided
2O/NH
3And DCS/NH
3The processing gas of admixture of gas forms or deposition.Subsequently, first or the surface of bottom oxynitride layer 220B on form second or top oxynitride layer 220A (304) of multilayer electric charge storage layer 204.Second or top oxynitride layer 220A have be different from first or the stoichiometric amount of the stoichiometric amount of oxygen, nitrogen and/or the silicon of bottom oxynitride layer 220B oxygen, nitrogen and/or the silicon formed form.Particular and as stated, second or top oxynitride layer 220A can by the CVD processing procedure use comprise ratio and flow rate through adjustment so that the DCS/NH of Silicon-rich, oxygen deprivation top oxynitride layer to be provided
3And N
2O/NH
3The processing gas of admixture of gas forms or deposition.At last, on the surface of the second layer of multilayer electric charge storage layer, form the top or the barrier oxide layer 218 (306) of silicon-oxide-nitrogen oxide-oxide-silicon structure.As stated, this top or barrier oxide layer 218 can form or deposition by any suitable method, but in some instantiations, in the CVD processing procedure, deposit.In an instantiation, top or the high-temperature oxide of barrier oxide layer 218 in HTO CVD processing procedure, depositing.Perhaps; Top or barrier oxide layer 218 can heat be grown, yet, should be appreciated that in this instantiation; Scalable or increase the thickness of top nitrogen oxide 220A will be because some top nitrogen oxide will effectively consume or oxidation during heat is grown the processing procedure of top or barrier oxide layer 218.
According to circumstances, method can further be included in form on the surface of top or barrier oxide layer 218 or the depositing silicon layer to form the folded or structure (308) of silicon-oxide-nitrogen oxide-oxide-silicon stack.Silicon-containing layer can be for example for by the polysilicon layer of CVD processing procedure deposition to form electric crystal or to install 200 control or polycrystalline gate layer 214.
To compare the memory device that uses the memory body layer that forms according to an instantiation of the present invention data preservation with reference to Fig. 4 compared to the memory device that uses convention memory body layer at present.Particular it, Fig. 4 explains the electronics limit voltage of device in the programmed ROM (EEPROM) variation during (VTE) of during using convention ONO structure and having stylizing in device lifetime of the EEPROM that the silicon-oxide-nitrogen oxide-oxide-silicon structure of multilayer oxynitride layer processes (VTP), erasing of can erasing.When collecting the data of this figure, two all circulation 100K circulations in advance under 85 ℃ ambient temperature of device.
With reference to Fig. 4, the EEPROM that 402 explanations of this figure or line use convention ONO structure with single oxynitride layer to process initially writing-and VTP is over time under the situation of no longer new memory body for formula or the back of erasing.Real data point on the line 402 is shown as the end and fills circle, and the remainder of line shows the extrapolation that is stopped (EOL) by the guideline lives of VTP to EEPROM.The VTE of the EEPROM that figure or line 404 explanation use convention ONO structures are processed over time.Real data point on the line 404 is shown as the filling circle, and the remainder of line shows the extrapolation by the EOL of VTE to EEPROM.Generally speaking, VTE and regulation difference VTP between of EEPROM under EOL for 0.5V at least can differentiate or respond to the difference between formula and the erased status.As figure is visible since then, uses EEPROM that convention ONO structure the processes difference between VTE and the VTP under 20 years regulation EOL to be about 0.35V.Therefore, the EEPROM that uses convention ONO structure to process and operate under these conditions can not meet the predetermined operation life-span at least about 17 years.
On the contrary, VTP and the VTE that has an EEPROM that the silicon-oxide-nitrogen oxide-oxide-silicon structure of multilayer oxynitride layer processes by the use of line 406 and line 408 explanations respectively is presented at over time that the difference between the VTE and VTP is at least about 1.96V under the regulation EOL.Therefore, the EEPROM that uses silicon-oxide-nitrogen oxide-oxide-silicon structure to process according to an instantiation of the present invention will meet and surpass the predetermined operation life-span in 20 years.Particular it, figure or line 406 explanation use according to an instantiation of the present invention silicon-oxide-nitrogen oxide-oxide-silicon structure EEPROM VTP over time.Real data point on the line 406 is shown as the end and fills square, and the remainder of line shows that VTP is to the extrapolation of stipulating EOL.The VTE of figure or line 408 explanation EEPROM over time, and the real data point is shown as the filling square on the line 408, the remainder of line shows the extrapolation of VTE to EOL.
The existing method that forms or make semiconductor device with reference to the flow chart description of Fig. 5 according to another instantiation.
With reference to Fig. 5, this method starts from and on substrate, forms tunnel oxide 216 (500).Then, on the surface of tunnel oxide 216, form the oxygen enrichment first or the bottom oxynitride layer 220B (502) of multilayer electric charge storage layer 204.As stated, this oxygen enrichment first or bottom oxynitride layer 220B can use by the CVD processing procedure and comprise the dichlorosilane (SiH of ratio in about 5: 1 to 15: 1 scopes
2Cl
2)/ammonia (NH
3) mixture and ratio in about 2: 1 to 4: 1 scopes and flow rate through the nitrous oxide (N of adjustment with oxynitride layer that the Silicon-rich that do not have trap in fact and oxygen enrichment are provided
2O)/NH
3The processing gas of mixture forms or deposition.That is first or the stoichiometric amount of bottom oxynitride layer 220B form and comprise high concentration oxygen, this high concentration with by serve as second or top oxynitride layer 220A and substrate 208 in barrier between the electric charge of being caught increase the preservation usefulness of multilayer electric charge storage layer.First or bottom oxynitride layer 220B in selected oxygen concentration can comprise about 15% to about 40% and in some instantiation about 35% oxygen concentration.
Subsequently, first or the surface of bottom oxynitride layer 220B on form second or top oxynitride layer 220A (504) of oxygen deprivation.Second or the stoichiometric amount of top oxynitride layer 220A with oxygen, nitrogen and/or silicon that the stoichiometric amount of the oxygen, nitrogen and/or the silicon that are different from ground floor forms form.Particular and as stated, second or top oxynitride layer 220A can use by the CVD processing procedure and comprise the N of ratio in about 1: 6 to 1: 8 scope
2O/NH
3Mixture and the ratio SiH in about 1.5: 1 to 3: 1 scopes
2Cl
2/ NH
3The processing gas of mixture forms or deposition, to provide the trap with the oxygen concentration below about 5% or 5% fine and close oxynitride layer.Therefore, second or top oxynitride layer 220A comprise than first or the charge trap density of at least 1000 times of bottom oxynitride layer 220B height.
At last, on second or top oxynitride layer 220A of multilayer electric charge storage layer 204, form top or barrier oxide layer 218 (506).As stated, this top or barrier oxide layer 218 can form or deposition by any suitable method.In an instantiation, second or barrier oxide layer 218 with cause second or top oxynitride layer 220A form via the mode that a part of oxidation that makes second oxynitride layer is thinned to predetermined thickness.At last, said about Fig. 4 like preceding text, the preservation usefulness of multilayer electric charge storage layer 204 strengthens increases at least about 20 years the end-of-life (EOL) of semiconductor device under the regulation difference between formula voltage (VTP) and the voltage of erasing (VTE).
In another aspect; Multilayer electric charge storage layer of the present invention has band-gap energy; This band-gap energy to produce the opposite electric field of accumulating because of the Charge Storage in the electric charge storage layer under the state of stylizing, strengthens data preservation through engineered thus under the situation that does not influence stylize voltage and/or device speed.The energy band diagram of the conventional devices that stylizes is described among Fig. 6, and this device comprises passage, tunnel oxide 604, even nitride or nitrogen oxide electric charge storage layer 606, barrier oxide layers 608 and the polysilicon control grid 610 in the silicon substrate 602.With reference to Fig. 6, the electric charge of catching that should note being positioned near larger amt electric charge storage layer 606 centers causes away from tunnel oxide 604 towards the big electric field accumulation of catching electric charge, and it can cause or cause the store charge loss.
On the contrary; In the memory device of the multilayer electric charge storage layer of the present invention that comprises engineered band-gap energy (band gap energy); The multilayer electric charge storage layer causes the electric field accumulation of pointing to inner (the self charge reservoir is towards tunnel oxide); It is opposite with the electric field of accumulating because of store charge, preserves thereby strengthen electric charge.Show the memory device that do not stylize that comprises multilayer electric charge storage layer 706 among Fig. 7 A.This device comprises passage, tunnel oxide 704, oxygen deprivation oxynitride layer 706A, oxygen enrichment bottom oxynitride layer 706B, barrier oxide layers 708 and the polysilicon control grid 710 in the silicon substrate 702.With reference to Fig. 7 A, trap site among the oxynitride layer 706A of oxygen deprivation top produce will with the opposite electric field of electric field by the charge generation of catching in the device that stylizes.Comprise that the band gap diagram that the device of multilayer electric charge storage layer 706 produces is showed among Fig. 7 A under the state of stylizing.
Although above displaying and be described as only having two oxynitride layers (that is layer on top and bottom layer); Yet the invention is not restricted to this; And the multilayer electric charge storage layer can comprise an any amount n oxynitride layer, and any or all these oxynitride layers can have the stoichiometric amount of different oxygen, nitrogen and/or silicon and form.Particular it, made and tested and had the multilayer electric charge storage layer that respectively has the oxynitride layer that the different chemical amount of calculation forms up to five.Yet, such as those who familiarize themselves with the technology understanding, generally need utilize the least possible layer to realize required result, thereby reduce the required fabrication steps of manufacturing installation, and much simple and more firm manufacturing processing procedure is provided thus.In addition, utilize the least possible layer also to produce higher yields, because be easy to control the stoichiometric amount composition and the size of less layer.
Although should further understand displaying and be described as the folded part of silicon-oxide in the memory device-nitrogen oxide-oxide-silicon stack; Yet structure of the present invention and method are not limited to; This and silicon-oxide-nitrogen oxide-oxide-silicon structure can be used for any semiconductor technology or use with any semiconductor technology under the situation that does not deviate from category of the present invention; Or be used for anyly needing the device or the dielectric layer of Charge Storage or piling up, comprise for example divide that gate electrode quick flash memory body, TaNOS pile up, IT (electric crystal) SONOS type unit, 2T SONOS type unit, 3T SONOS type unit, local 2 bit unit, multistage stylizing or unit and/or 9T or 12T non-volatility semiconductor memory body (NVSM) unit.Fig. 8 A to Fig. 8 E is the especially sketch map of suitable exemplary memory cell framework of multilayer electric charge storage layer of the present invention.
The advantage that had been superior to previous or prior art method according to structure of an instantiation of the present invention and forming method thereof comprises: (i) use by oxynitride layer is divided into a plurality of films or layer and adjust the structure of oxygen, nitrogen and silicon features on each layer can the enhance memory body device in data preservation; (ii) can be under the situation of not damaging data preservation the speed of enhance memory body device; (iii) can meet or surpass the data preservation and the speed specification of the memory device of the silicon-oxide-nitrogen oxide-oxide-silicon structure that uses an instantiation of the present invention under at least about 125 ℃ temperature; And (iv) provide 100,000 to circulate or 100,000 durable formula erase cycles that circulation is above.
Although described the present invention with reference to the particular exemplary instantiation, yet obviously these instantiations can be made various modifications and variation under the situation that does not deviate from broad spirit of the present invention and category.Therefore, specification and graphicly should be regarded as illustrative but not restrictive, sense.
The as request summary will allow the reader to confirm the 37C.F.R. § 1.72 (b) of the character of technological disclosure fast, and [Chinese abstract of invention] of the present invention is provided.It is that condition is submitted with category or the meaning that it is not used in explanation or restriction claim.In addition, in above-mentioned [embodiment], visible from the purpose that the present invention is linked to be an integral body with various characteristic sets in single instantiation.The method of the present invention should not be construed as in instantiation that reflection advocates and each claim clear and definite said compare need more characteristics intention.More precisely, such as following claim reflection, subject matter of the present invention is in and is less than in the single whole characteristics that disclose instantiation.Therefore, following claim is incorporated in [embodiment] by this, and each claim advocates itself to be an other instantiation.
In formerly describing, for illustrative purposes, a large amount of specific detail have been set forth so that the thorough to multilayer electric charge storage layer of the present invention and method is provided.Yet those who familiarize themselves with the technology will show and be prone to know, interfare device of the present invention and method can be implemented under the situation of not having these specific detail.In other cases, well known structures and technology do not show in detail or show to avoid unnecessarily obscuring the understanding to this description with block diagram form.
Mentioning in the description that " instantiation (one embodiment) " or " instantiation (an embodiment) " means combines the described special characteristic of instantiation, structure or characteristic to be included in heat to go at least one instantiation of latched system or method.May not all refer to same instantiation at the different local phrases " instantiation (one embodiment) " that occur of specification.Term as used herein " coupling (to couple) " can comprise two or more assemblies of direct electrical connection or element and connect both indirectly via one or more intervention package.
Claims (23)
1. silicon-oxide-nitrogen oxide-oxide-silicon structure, it comprises:
Lip-deep tunnel oxide at the substrate that comprises silicon;
The multilayer electric charge storage layer, it is included in oxygen enrichment first oxynitride layer on this tunnel oxide, and wherein the stoichiometric amount of this first oxynitride layer composition causes it not have trap in fact; And oxygen deprivation second oxynitride layer on this first oxynitride layer, wherein the stoichiometric amount of this second oxynitride layer is formed and is caused its trap densification;
Barrier oxide layer on this second oxynitride layer; And
Siliceous gate layer on this barrier oxide layer.
2. structure as claimed in claim 1, wherein the concentration of oxygen is about 15% to about 40% in this first oxynitride layer.
3. structure as claimed in claim 1, wherein the concentration of oxygen is lower than about 5% in this second oxynitride layer.
4. structure as claimed in claim 1, wherein this second oxynitride layer comprises the charge trap density than at least 1000 times of this first nitrogen oxide floor heights.
5. structure as claimed in claim 1, wherein this second oxynitride layer further comprises through selecting to increase the wherein carbon of the concentration of trap number.
6. semiconductor device, it comprises:
Comprise silicon and have source electrode and the substrate on the surface that drain area is spaced;
On this surface of this substrate, cover the tunnel oxide of these source electrodes and drain area;
On this tunnel oxide and laterally be placed in the multilayer electric charge storage layer between these isolated source electrodes and the drain area; This multilayer electric charge storage layer comprises oxygen enrichment first oxynitride layer, and wherein the stoichiometric amount of this first oxynitride layer composition causes it not have trap in fact; And oxygen deprivation second oxynitride layer, wherein the stoichiometric amount of this second oxynitride layer is formed and is caused its trap densification;
Barrier oxide layer on this second oxynitride layer; And
Siliceous gate layer on this barrier oxide layer.
7. semiconductor device as claimed in claim 6, wherein the concentration of oxygen is about 15% to about 40% in this first oxynitride layer.
8. semiconductor device as claimed in claim 6, wherein the concentration of oxygen is lower than about 5% in this second oxynitride layer.
9. semiconductor device as claimed in claim 6, wherein this second oxynitride layer comprises the charge trap density than at least 1000 times of this first nitrogen oxide floor heights.
10. semiconductor device as claimed in claim 6, wherein this second oxynitride layer further comprises through selecting to increase the wherein carbon of the concentration of trap number.
11. a method that forms semiconductor device, it comprises:
On the silicon-containing layer of substrate, form tunnel oxide;
By following formation multilayer electric charge storage layer:
Deposition oxygen enrichment first oxynitride layer on this tunnel oxide, wherein the stoichiometric amount of this first oxynitride layer composition causes it not have trap in fact; And
Deposition oxygen deprivation second oxynitride layer on this first oxynitride layer, wherein the stoichiometric amount of this second oxynitride layer is formed and is caused its trap densification;
On this second oxynitride layer, form the barrier oxide layer; And
On this barrier oxide layer, form siliceous gate layer.
12. method as claimed in claim 11; Wherein this stoichiometric amount of this first oxynitride layer is formed and is comprised certain density oxygen, this concentration through select with by serve as the electric charge of being caught in this second oxynitride layer and this substrate between barrier increase the preservation usefulness of this multilayer electric charge storage layer.
13. method as claimed in claim 12, wherein this concentration of oxygen is about 15% to about 40% in this first oxynitride layer.
14. method as claimed in claim 12, wherein this concentration of oxygen is about 35% in this first oxynitride layer.
15. method as claimed in claim 12, wherein this concentration of oxygen is lower than about 5% in this second oxynitride layer.
16. method as claimed in claim 12, wherein this preservation usefulness of this multilayer electric charge storage layer makes the end-of-life (end-of-life of this semiconductor device under formula and the regulation difference between the voltage of erasing; EOL) increase at least about 20 years.
17. method as claimed in claim 11, wherein this second oxynitride layer comprises the charge trap density than at least 1000 times of this first nitrogen oxide floor heights.
18. method as claimed in claim 11, wherein this first oxynitride layer uses in the chemical vapor deposition (CVD) processing procedure and comprises the dichlorosilane (SiH of ratio in about 5: 1 to 15: 1 scopes
2Cl
2)/ammonia (NH
3) mixture and the ratio nitrous oxide (N in about 2: 1 to 4: 1 scopes
2O)/NH
3The processing gas of mixture forms, and wherein this second oxynitride layer uses in the CVD processing procedure and comprises the N of ratio in about 1: 6 to 1: 8 scope
2O/NH
3Mixture and the ratio SiH in about 1.5: 1 to 3: 1 scopes
2CI
2/ NH
3The processing gas of mixture forms.
19. method as claimed in claim 18 wherein forms this first oxynitride layer and this second oxynitride layer and ties up in the single CVD instrument by changing these N
2O/NH
3And SiH
2Cl
2/ NH
3This ratio of mixture carries out in regular turn.
20. method as claimed in claim 11, wherein this tunnel oxide is used oxygen (O on this substrate under the temperature at least 1000 ℃ in ISSG (situ steam produces (In-Situ Steam Generation)) chamber
2) and hydrogen (H
2) between reaction utilize free-radical oxidation to grow.
21. method as claimed in claim 11, wherein this barrier oxide layer forms by high-density electric slurry (HDP) oxidation of the part of this second oxynitride layer.
22. method as claimed in claim 11, wherein this second oxynitride layer further comprises through selecting to increase the wherein carbon of the concentration of trap number.
23. method as claimed in claim 22, wherein this second oxynitride layer uses in the CVD processing procedure and comprises with about 7: 1 two tri-butylamine base silanes (BTBAS) and the ammonia (NH to about 1: 7 ratio mixed
3) processing gas form.
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| PCT/US2012/021583 WO2012097373A1 (en) | 2011-01-14 | 2012-01-17 | Oxide-nitride-oxide stack having multiple oxynitride layers |
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| US20100096687A1 (en) * | 2008-10-21 | 2010-04-22 | Applied Materials, Inc. | Non-volatile memory having silicon nitride charge trap layer |
| CN101859702A (en) * | 2009-04-10 | 2010-10-13 | 赛普拉斯半导体公司 | Oxide-nitride-oxide stack containing a plurality of oxynitrides layers |
Also Published As
| Publication number | Publication date |
|---|---|
| JP6258412B2 (en) | 2018-01-10 |
| TW201243951A (en) | 2012-11-01 |
| JP2016197732A (en) | 2016-11-24 |
| TWI534897B (en) | 2016-05-21 |
| KR20140025262A (en) | 2014-03-04 |
| WO2012097373A1 (en) | 2012-07-19 |
| JP2014504027A (en) | 2014-02-13 |
| JP5960724B2 (en) | 2016-08-02 |
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