CN102751331A - Strain SiGe square-in-square type channel NMOS (N-channel Metal Oxide Semiconductor) integrated device and preparation method thereof - Google Patents

Strain SiGe square-in-square type channel NMOS (N-channel Metal Oxide Semiconductor) integrated device and preparation method thereof Download PDF

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CN102751331A
CN102751331A CN2012102443753A CN201210244375A CN102751331A CN 102751331 A CN102751331 A CN 102751331A CN 2012102443753 A CN2012102443753 A CN 2012102443753A CN 201210244375 A CN201210244375 A CN 201210244375A CN 102751331 A CN102751331 A CN 102751331A
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CN102751331B (en
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胡辉勇
宣荣喜
张鹤鸣
宋建军
吕懿
王海栋
王斌
郝跃
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Xidian University
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Abstract

The invention provides a strain SiGe square-in-square type channel NMOS (N-channel Metal Oxide Semiconductor) integrated device which is suitable for an NMOS integrated device, and a preparation method of the strain SiGe square-in-square type channel NMOS integrated device by using a micron level process. The preparation method comprises the steps of: continuously growing a Si epitaxial layer, a first strain SiGe light doping drain region (LDD) electrode layer, a strain SiGe layer, a second strain SiGe LDD region layer and an N type Si layer; forming a drain region, a source region and a drain connecting region by using technical means such as chemical vapor deposition (CVD) and dry etching and finally forming an NMOS device; and photoetching a lead to form an NMOS integrated circuit. According to the invention, under the condition of no addition of any fund and equipment input, the stain SiGe square-in-square type vertical channel NMOS integrated device which is improved in property in comparison with a body Si NMOS is manufactured at low temperature.

Description

A kind of strain SiGe returns type raceway groove NMOS integrated device and preparation method
Technical field
The invention belongs to the semiconductor integrated circuit technical field, relate in particular to that a kind of to use the micron order integrated circuit technology to prepare conducting channel length be that the strain SiGe of 22～45nm returns type vertical-channel NMOS integrated device and preparation method.
Background technology
IC industry has the high multiplication property and the degree of association for modern economy and social development.The development of integrated circuit technique and industry thereof; Can promote the development of consumer electronics industry, computer industry, communication industry and related industry; IC chip is as the core of conventional industries intellectualized reconstruction, and is significant with promotion national economy and social informatization development for promoting whole industrial level.As with fastest developing speed on the human history, have the greatest impact, most widely used technology, integrated circuit has become the important symbol of weighing national science technical merit, overall national strength and a defense force.The technical performance of integrated circuit, industry size are determining the development level and the international competitiveness of a National modern industrial or agricultural, defence equipment and the household electronic class consumer goods, are the motive power of modern economy development.
Since first silicon integrated circuit in 1958 was born, it was 10 that development of integrated circuits has experienced integrated level 2～10 3Little/the medium-scale integration of individual element reaches 10 to current integrated level 9～10 11In integrated a plurality of stages of huge size individual or above element, also impel silicon materials to become the leading role of semiconductor industry gradually.Along with the researcher constantly furthers investigate the technology that adopts silicon materials to make integrated circuit; Cause the silicon technology integrated technology to reach its maturity, its improvement and innovation are constantly promoting integrated circuit march toward more high-performance, more high integration, the new world of high reliability more.At present, silicon technology has become the mainstream technology of IC industry, and the silicon integrated circuit product is a main product.Because this product price ratio is high, practical, in all microelectronic integrated circuit products, keeping the monopoly position of 90% above share.Simultaneously, consider, estimate that in decades to come in other technology integrated technology still can not substitute or surmount the silicon technology integrated technology from composite factors such as the practicality of silicon technology integrated technology, cost performance, system integration development trends.
Continue to advance in order to promote semiconductor industry, the characteristic size of IC-components is constantly dwindled, and integration density improves constantly, and integrated scale increases rapidly.In decades in the past, be micron technology till now the nanometer technology of the microelectronics manufacture of main rapidoprint from beginning with silicon, the IC chip integrated level is increasingly high, and cost is more and more lower.But along with the characteristic line breadth of silicon integrated circuit gets into nanoscale, SiO 2Traditional materials such as gate dielectric material, polysilicon, silicide gate electrode are owing to receive the restriction of material behavior; Can't satisfy the demand of nanoscale devices and circuit; Traditional devices structure and technology also can't satisfy the manufacturing requirement of nanoscale devices and integrated circuit simultaneously; Therefore, silicon microelectric technique is faced with stern challenge, and this present situation has seriously restricted the development of semicon industry.
Summary of the invention
The object of the present invention is to provide the existing micro process of a kind of usefulness to prepare strain SiGe and return type raceway groove NMOS integrated device preparation method; Do not change existing equipment and do not increase under the condition of cost to be implemented in, the strain SiGe of preparing conducting channel and be 22～45nm returns type vertical-channel NMOS integrated device.
The object of the present invention is to provide a kind of strain SiGe to return type vertical-channel NMOS integrated device, the conducting channel of said device is back type, and channel direction is vertical with substrate surface.
Further, channel region is the strain SiGe material, the Ge component changes in gradient in the raceway groove, and is tensile strain at channel direction.
Further, said device is included in N type Si epitaxial loayer, a N type strain SiGe layer, P type strain SiGe layer, the 2nd N type strain SiGe layer and the N type Si layer of growing successively on the substrate.
Further, said N type Si epitaxy layer thickness is 1.5～2.5 μ m, doping content is 5 * 10 19～5 * 10 20Cm -3, as the drain region; A said N type strain SiGe layer thickness is 3 ~ 5nm, and doping content is 5 * 10 17～5 * 10 18Cm -3, the Ge component is 10%, as the first lightly-doped source drain region (LDD) layer; Said P type strain SiGe layer thickness is 22～45nm, and doping content is 5 * 10 16～5 * 10 17Cm -3, the Ge component is that lower floor is 10%, the upper strata is 20～30% Gradient distribution, as channel region; Said the 2nd N type strain SiGe layer thickness is 3 ~ 5nm, and doping content is 5 * 10 17～5 * 10 18Cm -3, the Ge component is 20～30%, as the second lightly-doped source drain region (LDD) layer; Said N type Si layer thickness is 200～400nm, and doping content is 5 * 10 19～5 * 10 20Cm -3, as the source region.
Another object of the present invention is to provide a kind of method that strain SiGe returns type vertical-channel NMOS integrated device for preparing, carry out as follows:
The first step, to choose doping content be 5 * 10 15～5 * 10 16Cm -3About P type Si substrate slice;
Second goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, five layer materials of on substrate, growing continuously: ground floor is that thickness is the N type Si epitaxial loayer of 1.5～2.5 μ m, and doping content is 5 * 10 19～5 * 10 20Cm -3, as the drain region; The second layer is that thickness is 3 ~ 5nmN type strain SiGe layer, and doping content is 5 * 10 17～5 * 10 18Cm -3, the Ge component is 10%, as the first lightly-doped source drain region (LDD) layer; The 3rd layer is that thickness is the P type strain SiGe layer of 22～45nm, and doping content is 5 * 10 16～5 * 10 17Cm -3, the Ge component is that lower floor is 10%, the upper strata is 20～30% Gradient distribution, as channel region; The 4th layer is that thickness is the N type strain SiGe layer of 3 ~ 5nm, and doping content is 5 * 10 17～5 * 10 18Cm -3, the Ge component is 20～30%, as the second lightly-doped source drain region (LDD) layer; Layer 5 is that thickness is the N type Si layer of 200～400nm, and doping content is 5 * 10 19～5 * 10 20Cm -3, as the source region;
The deep trouth district is isolated in the 3rd step, photoetching, utilizes dry etch process, etches the deep trouth that the degree of depth is 2.5～3.5 μ m in isolated area;
The 4th the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, be the SiO of 20～40nm at the substrate surface deposition thickness 2Layer all covers the deep trouth inner surface, and deposit Poly-Si (polysilicon) forms deep trench isolation with filling up in the deep trouth again;
The 5th step, photolithographic source are leaked isolated area, utilize dry etch process, leak isolated area in the source and etch the shallow slot that the degree of depth is 0.5～0.7 μ m; Utilize chemical vapor deposition (CVD) method again,, in shallow slot, fill SiO at 600～800 ℃ 2At last,, remove unnecessary oxide layer, form shallow-trench isolation with chemico-mechanical polishing (CMP) method;
The 6th the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2And layer of sin, etch away SiN, SiO 2Form and leak the bonding pad window; Trench region is leaked in photoetching, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.7～0.9 μ m; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is the 2nd SiO of 20～40nm at the substrate surface growth thickness 2Layer forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the 2nd SiO of drain region channel bottom 2Layer.Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, the deposit doping content is 5 * 10 19～5 * 10 20Cm -3N type Poly-Si will fill up groove, remove the unnecessary Poly-Si in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad;
The 7th the step, utilize dry etch process, etch away SiN, SiO 2The barrier layer.Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2And layer of sin, etch away SiN, the SiO of gate region 2Form the grid window.Utilize dry etch process, etch the gate groove that the degree of depth is 0.7～0.9 μ m.Utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of the high-k of 6～10nm at the substrate surface deposition thickness 2Layer as gate dielectric layer, at 600～800 ℃, is 5 * 10 in substrate surface deposit one deck doping content 19～5 * 10 20Cm -3N type Poly-Si, and gate groove filled up, remove surface portion Poly-Si, form grid;
The 8th step,, the etching source region, form nmos device;
The 9th step. utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface growth regulation four SiO 2The layer, and on grid, source and drain region lithography fair lead;
The tenth step, metallization, photoetching lead-in wire form drain electrode, source electrode and gate metal lead-in wire, and constituting conducting channel length is the NMOS integrated circuit of 22～45nm.
Further, channel length is confirmed according to the P type strain SiGe layer thickness of the second step deposit.
Further, channel length is got 22～45nm.
Further, related maximum temperature determines that according to chemical vapor deposition (CVD) technological temperature in second, four, five, six, seven and nine steps maximum temperature is smaller or equal to 800 ℃ among this preparation method.
Another object of the present invention is to provide a kind of strain SiGe to return the preparation method of type vertical-channel nmos device integrated circuit, comprise the steps:
Step 1, the epitaxial material preparation process:
(1a) choosing doping content is 5 * 10 16Cm -3The P type Si substrate slice of magnitude;
(1b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on substrate growth one layer thickness be the N type Si epitaxial loayer of 2 μ m as the drain region, doping content is 5 * 10 20Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth thickness is the N type strain SiGe layer of 3nm on substrate, and doping content is 5 * 10 18Cm -3, the Ge component is 10%, as the first lightly-doped source drain region (LDD) layer;
(1d) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the Si epitaxial loayer growth one layer thickness be the P type SiGe layer of 22nm as channel region, doping content is 5 * 10 17Cm -3, the Ge component is that lower floor is 10%, the upper strata is 30% Gradient distribution;
(1e) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth thickness is the 2nd N type strain SiGe layer of 3nm on substrate, and doping content is 5 * 10 18Cm -3, the Ge component is 30%, as the second lightly-doped source drain region (LDD) layer;
(1f) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the SiGe layer growth one layer thickness be the N type Si layer of 300nm as the source region, doping content is 5 * 10 20Cm -3
Step 2, the isolation preparation step:
(2a) the deep trouth district is isolated in photoetching, utilizes dry etch process, etches the deep trouth that the degree of depth is 3 μ m in isolated area;
(2b) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is the SiO of 40nm at the substrate surface deposition thickness 2Layer all covers the deep trouth inner surface;
(2c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill Poly-Si, form deep trench isolation at 800 ℃;
(2d) the deep trouth district is isolated in photoetching, utilizes dry etch process, leaks isolated area in the source and etches the shallow slot that the degree of depth is 0.6 μ m;
(2e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2
(2f), remove unnecessary oxide layer, form shallow-trench isolation with chemico-mechanical polishing (CMP) method;
Step 3, leak the bonding pad preparation process:
(3a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(3b) photoetching SiN and SiO 2Form and leak the bonding pad window;
(3c) utilize dry etch process, etching the degree of depth is the leakage groove of 0.8 μ m;
(3d) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is the 2nd SiO of 40nm at the substrate surface growth thickness 2Layer forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the 2nd SiO of drain region channel bottom 2Layer;
(3e) utilize chemical vapor deposition (CVD) method, at 800 ℃, the deposit doping content is 5 * 10 20Cm -3N type Poly-Si will fill up groove, remove the unnecessary Poly-Si in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad;
Step 4, NMOS forms step:
(4a) utilize dry etch process, etch away SiN and SiO 2The barrier layer;
(4b) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2, deposit layer of sin in the above again;
The SiN of (4c) photoetching gate region and SiO 2, form the grid window;
(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.7 μ m;
(4e) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 400 ℃, is the HfO of the high-k of 10nm at the substrate surface growth thickness 2Layer is as gate dielectric layer;
(4f) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is 5 * 10 in substrate surface deposit doping content 20Cm -3N type Poly-Si, and gate groove filled up, remove surface portion Poly-Si, form grid;
(4g) etching source region forms nmos device;
Step 5 constitutes NMOS integrated circuit step:
(5a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface growth regulation Three S's iO 2Layer;
(5b) lithography fair lead on grid, source and drain region;
(5c) metallization;
(5d) photoetching lead-in wire forms drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, and constituting conducting channel length is the NMOS integrated circuit of 22nm.
The present invention has following advantage:
1. the strain SiGe nmos device channel direction of the present invention's preparation is the vertical direction of strain SiGe layer; Then channel length is the strain SiGe layer thickness; This thickness can be controlled through SiGe material growth technique, thereby has avoided the small size photoetching, has reduced the input of lithographic equipment; Reduce process complexity, reduced cost;
2. the SiGe material is tensile strain along channel direction in the strain SiGe nmos device of the present invention's preparation; Tensile strain SiGe material electronics mobility is higher than the Si material; Therefore, performances such as this device frequency and current driving ability are higher than unidimensional relaxation Si nmos device;
3. the strain SiGe nmos device raceway groove of the present invention's preparation is back type; Promptly grid can be controlled raceway groove on four sides in groove; Therefore, this device has increased the width of raceway groove in limited zone, thereby has improved the current driving ability of device; Increase the integrated level of integrated circuit, reduced the manufacturing cost of lsi unit area;
4. the Ge component changes in gradient in the strain SiGe NMOS raceway groove of the present invention's preparation; Therefore can produce the built-in field that an accelerated electron transports at channel direction; Strengthen the carrier transport ability of raceway groove, thereby improved the frequency characteristic and the current driving ability of strain SiGe nmos device;
5. in the strain SiGe NMOS structure of the present invention's preparation, adopted the HfO of high K value 2As gate medium, improved the grid-control ability of device, strengthened the electric property of device;
6. in the strain SiGe nmos device of the present invention's preparation,, introduce lightly-doped source drain region (LDD) technology, improved device performance in order effectively to suppress short-channel effect;
7. to prepare the maximum temperature that relates in the strain SiGe vertical-channel nmos device process be 800 ℃ in the present invention; Be lower than the technological temperature that causes strain SiGe channel stress relaxation; Therefore this preparation method can keep strain SiGe channel stress effectively, improves the performance of integrated circuit;
8. because process proposed by the invention and existing micron order Si integrated circuit processing technology are compatible; Therefore; Can be under the situation that need not append any fund and equipment input; Prepare nmos device and integrated circuit that conducting channel length is 22～45nm, the manufacturing capacity of existing micron order Si integrated circuit technology platform is significantly improved, realize the great-leap-forward development of domestic integrated circuit working ability.
Description of drawings
Fig. 1 is the flow chart that strain SiGe provided by the invention returns the preparation method of type vertical-channel NMOS integrated device and circuit;
Fig. 2 is the process sketch map that returns type raceway groove NMOS integrated device and circuit preparation with the inventive method strain SiGe.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention provides a kind of strain SiGe to return type vertical-channel NMOS integrated device, and the conducting channel of said device is back type, and channel direction is vertical with substrate surface.
As a prioritization scheme of the embodiment of the invention, channel region is the strain SiGe material, and the Ge component changes in gradient in the raceway groove, and is tensile strain at channel direction.
As a prioritization scheme of the embodiment of the invention, said device is included in N type Si epitaxial loayer, a N type strain SiGe layer, P type strain SiGe layer, the 2nd N type strain SiGe layer and the N type Si layer of growing successively on the substrate.
As a prioritization scheme of the embodiment of the invention, said N type Si epitaxy layer thickness is 1.5～2.5 μ m, and doping content is 5 * 10 19～5 * 10 20Cm -3, as the drain region; A said N type strain SiGe layer thickness is 3 ~ 5nm, and doping content is 5 * 10 17～5 * 10 18Cm -3, the Ge component is 10%, as the first lightly-doped source drain region (LDD) layer; Said P type strain SiGe layer thickness is 22～45nm, and doping content is 5 * 10 16～5 * 10 17Cm -3, the Ge component is that lower floor is 10%, the upper strata is 20～30% Gradient distribution, as channel region; Said the 2nd N type strain SiGe layer thickness is 3 ~ 5nm, and doping content is 5 * 10 17～5 * 10 18Cm -3, the Ge component is 20～30%, as the second lightly-doped source drain region (LDD) layer; Said N type Si layer thickness is 200～400nm, and doping content is 5 * 10 19～5 * 10 20Cm -3, as the source region.
Following with reference to accompanying drawing 1 and accompanying drawing 2, the technological process of strain SiGe of the present invention being returned the preparation of type raceway groove NMOS integrated device describes in further detail.
Embodiment 1: the preparation conducting channel is that the strain SiGe of 45nm returns type raceway groove NMOS integrated device and circuit, and concrete steps are following:
Step 1, the epitaxial material preparation is shown in Fig. 2 (a).
(1a) choosing doping content is 10 15Cm -3About P type Si substrate slice 1;
(1b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, on substrate growth one layer thickness be the N type Si epitaxial loayer 2 of 2.5 μ m as the drain region, doping content is 5 * 10 19Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth thickness is the N type strain SiGe layer 3a of 5nm on substrate, and doping content is 5 * 10 17Cm -3, the Ge component is 10%, as the first lightly-doped source drain region (LDD) layer;
(1d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, on the Si epitaxial loayer growth one layer thickness be the P type SiGe layer 3 of 45nm as channel region, doping content is 5 * 10 16Cm -3, the Ge component is that lower floor is 10%, the upper strata is 20% Gradient distribution;
(1e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth thickness is the N type strain SiGe layer 3b of 5nm on substrate, and doping content is 5 * 10 17Cm -3, the Ge component is 20%, as the second lightly-doped source drain region (LDD) layer;
(1f) utilize the method for chemical vapor deposition (CVD), at 600 ℃, on the SiGe layer growth one layer thickness be the N type Si layer 4 of 400nm as the source region, doping content is 5 * 10 19Cm -3
Step 2, isolation preparation is shown in Fig. 2 (b) (left side is a profile, and the right is a vertical view).
(2a) the deep trouth district is isolated in photoetching, utilizes dry etch process, etches the deep trouth that the degree of depth is 3.5 μ m in isolated area;
(2b) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the SiO of 20nm at the substrate surface deposition thickness 2Layer 5 all covers the deep trouth inner surface;
(2c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill Poly-Si6, form deep trench isolation 7 at 600 ℃;
(2d) the deep trouth district is isolated in photoetching, utilizes dry etch process, leaks isolated area in the source and etches the shallow slot that the degree of depth is 0.7 μ m;
(2e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2
(2f), remove unnecessary oxide layer, form shallow-trench isolation 8 with chemico-mechanical polishing (CMP) method.
Step 3 is leaked the bonding pad preparation, shown in Fig. 2 (c) (left side is a profile, and the right is a vertical view).
(3a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(3b) photoetching SiN, SiO 2Form and leak the bonding pad window;
(3c) utilize dry etch process, etching the degree of depth is the leakage groove of 0.9 μ m;
(3d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the 2nd SiO of 20nm at the substrate surface growth thickness 2Layer 9 forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the 2nd SiO of drain region channel bottom 2Layer;
(3e) utilize chemical vapor deposition (CVD) method, at 600 ℃, the deposit doping content is 1 * 10 20Cm -3N type Poly-Si will fill up groove, remove the unnecessary Poly-Si in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad.
Step 4, NMOS forms, shown in Fig. 2 (d) (left side is a profile, and the right is a vertical view).
(4a) utilize dry etch process, etch away SiN, SiO 2The barrier layer;
(4b) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
The SiN of (4c) photoetching gate region, SiO 2, form the grid window;
(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.9 μ m;
(4e) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of the high-k of 6nm at the substrate surface growth thickness 2Layer 11 is as gate dielectric layer;
(4f) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3N type Poly-Si 12, and gate groove filled up, remove surface portion Poly-Si, form grid;
(4g) the etching source region 13, form nmos device 14.
Step 5 constitutes the NMOS integrated circuit, shown in Fig. 2 (e) (left side is a profile, and the right is a vertical view).
(5a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface growth regulation four SiO 2Layer 15;
(5b) lithography fair lead on grid, source and drain region;
(5c) metallization;
(5d) photoetching lead-in wire forms drain metal lead-in wire 16, source metal lead-in wire 17 and gate metal lead-in wire 18, and constituting conducting channel length is the NMOS integrated circuit of 45nm.
Embodiment 2: the preparation conducting channel is that the strain SiGe of 30nm returns type raceway groove NMOS integrated device and circuit, and concrete steps are following:
Step 1, the epitaxial material preparation is shown in Fig. 2 (a).
(1a) choosing doping content is 5 * 10 15Cm -3About P type Si substrate slice 1;
(1b) utilize the method for chemical vapor deposition (CVD), at 700 ℃, on substrate growth one layer thickness be the N type Si epitaxial loayer 2 of 2.5 μ m as the drain region, doping content is 1 * 10 20Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth thickness is the N type strain SiGe layer 3a of 4nm on substrate, and doping content is 1 * 10 18Cm -3, the Ge component is 10%, as the first lightly-doped source drain region (LDD) layer;
(1d) utilize the method for chemical vapor deposition (CVD), at 700 ℃, on the Si epitaxial loayer growth one layer thickness be the P type SiGe layer 3 of 30nm as channel region, doping content is 1 * 10 17Cm -3, the Ge component is that lower floor is 10%, the upper strata is 50% Gradient distribution;
(1e) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth thickness is the N type strain SiGe layer 3b of 4nm on substrate, and doping content is 1 * 10 18Cm -3, the Ge component is 50%, as the second lightly-doped source drain region (LDD) layer;
(1f) utilize the method for chemical vapor deposition (CVD), at 700 ℃, on the SiGe layer growth one layer thickness be the N type Si layer 4 of 200nm as the source region, doping content is 1 * 10 20Cm -3
Step 2, isolation preparation is shown in Fig. 2 (b) (left side is a profile, and the right is a vertical view).
(2a) the deep trouth district is isolated in photoetching, utilizes dry etch process, etches the deep trouth that the degree of depth is 2.5 μ m in isolated area;
(2b) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is the SiO of 30nm at the substrate surface deposition thickness 2Layer 5 all covers the deep trouth inner surface;
(2c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill Poly-Si6, form deep trench isolation 7 at 700 ℃;
(2d) the deep trouth district is isolated in photoetching, utilizes dry etch process, leaks isolated area in the source and etches the shallow slot that the degree of depth is 0.5 μ m;
(2e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃ 2
(2f), remove unnecessary oxide layer, form shallow-trench isolation 8 with chemico-mechanical polishing (CMP) method.
Step 3 is leaked the bonding pad preparation, shown in Fig. 2 (c) (left side is a profile, and the right is a vertical view).
(3a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck SiO 2, and layer of sin;
(3b) photoetching SiN, SiO 2Form and leak the bonding pad window;
(3c) utilize dry etch process, etching the degree of depth is the leakage groove of 0.7 μ m;
(3d) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is the 2nd SiO of 30nm at the substrate surface growth thickness 2Layer 9 forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the 2nd SiO of drain region channel bottom 2Layer;
(3e) utilize chemical vapor deposition (CVD) method, at 700 ℃, the deposit doping content is 5 * 10 19Cm -3N type Poly-Si will fill up groove, remove the unnecessary Poly-Si in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad.
Step 4, NMOS forms, shown in Fig. 2 (d) (left side is a profile, and the right is a vertical view).
(4a) utilize dry etch process, etch away SiN, SiO 2The barrier layer;
(4b) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
The SiN of (4c) photoetching gate region, SiO 2, form the grid window;
(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.7 μ m;
(4e) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 350 ℃, is the HfO of the high-k of 8nm at the substrate surface growth thickness 2Layer 11 is as gate dielectric layer;
(4f) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is 5 * 10 in substrate surface deposit doping content 19Cm -3N type Poly-Si12, and gate groove filled up, remove surface portion Poly-Si, form grid;
(4g) the etching source region 13, form nmos device 14.
Step 5 constitutes the NMOS integrated circuit, shown in Fig. 2 (e) (left side is a profile, and the right is a vertical view).
(5a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface growth regulation four SiO 2Layer 15;
(5b) lithography fair lead on grid, source and drain region;
(5c) metallization;
(5d) photoetching lead-in wire forms drain metal lead-in wire 16, source metal lead-in wire 17 and gate metal lead-in wire 18, and constituting conducting channel length is the NMOS integrated circuit of 30nm.
Embodiment 3: the preparation conducting channel is that the strain SiGe of 22nm returns type raceway groove NMOS integrated device and circuit, and concrete steps are following:
Step 1, the epitaxial material preparation is shown in Fig. 2 (a).
(1a) choosing doping content is 10 16Cm -3About P type Si substrate slice 1;
(1b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on substrate growth one layer thickness be the N type Si epitaxial loayer 2 of 2 μ m as the drain region, doping content is 5 * 10 20Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth thickness is the N type strain SiGe layer 3a of 3nm on substrate, and doping content is 5 * 10 18Cm -3, the Ge component is 10%, as the first lightly-doped source drain region (LDD) layer;
(1d) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the Si epitaxial loayer growth one layer thickness be the P type SiGe layer 3 of 22nm as channel region, doping content is 5 * 10 17Cm -3, the Ge component is that lower floor is 10%, the upper strata is 30% Gradient distribution;
(1e) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth thickness is the N type strain SiGe layer 3b of 3nm on substrate, and doping content is 5 * 10 18Cm -3, the Ge component is 30%, as the second lightly-doped source drain region (LDD) layer;
(1f) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the SiGe layer growth one layer thickness be the N type Si layer 4 of 300nm as the source region, doping content is 5 * 10 20Cm -3
Step 2, isolation preparation is shown in Fig. 2 (b) (left side is a profile, and the right is a vertical view).
(2a) the deep trouth district is isolated in photoetching, utilizes dry etch process, etches the deep trouth that the degree of depth is 3 μ m in isolated area;
(2b) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is the SiO of 40nm at the substrate surface deposition thickness 2Layer 5 all covers the deep trouth inner surface;
(2c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill Poly-Si6, form deep trench isolation 7 at 800 ℃;
(2d) the deep trouth district is isolated in photoetching, utilizes dry etch process, leaks isolated area in the source and etches the shallow slot that the degree of depth is 0.6 μ m;
(2e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2
(2f), remove unnecessary oxide layer, form shallow-trench isolation 8 with chemico-mechanical polishing (CMP) method.
Step 3 is leaked the bonding pad preparation, shown in Fig. 2 (c) (left side is a profile, and the right is a vertical view).
(3a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(3b) photoetching SiN, SiO 2Form and leak the bonding pad window;
(3c) utilize dry etch process, etching the degree of depth is the leakage groove of 0.8 μ m;
(3d) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is the 2nd SiO of 40nm at the substrate surface growth thickness 2Layer 9 forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the 2nd SiO of drain region channel bottom 2Layer;
(3e) utilize chemical vapor deposition (CVD) method, at 800 ℃, the deposit doping content is 5 * 10 20Cm -3N type Poly-Si will fill up groove, remove the unnecessary Poly-Si in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad.
Step 4, NMOS forms, shown in Fig. 2 (d) (left side is a profile, and the right is a vertical view).
(4a) utilize dry etch process, etch away SiN, SiO 2The barrier layer;
(4b) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2, deposit layer of sin in the above again;
The SiN of (4c) photoetching gate region, SiO 2, form the grid window;
(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.7 μ m;
(4e) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 400 ℃, is the HfO of the high-k of 10nm at the substrate surface growth thickness 2Layer 11 is as gate dielectric layer;
(4f) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is 5 * 10 in substrate surface deposit doping content 20Cm -3N type Poly-Si 12, and gate groove filled up, remove surface portion Poly-Si, form grid;
(4g) the etching source region 13, form nmos device 14.
Step 5 constitutes the NMOS integrated circuit, shown in Fig. 2 (e) (left side is a profile, and the right is a vertical view).
(5a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface growth regulation four SiO 2Layer 15;
(5b) lithography fair lead on grid, source and drain region;
(5c) metallization;
(5d) photoetching lead-in wire forms drain metal lead-in wire 16, source metal lead-in wire 17 and gate metal lead-in wire 18, and constituting conducting channel length is the NMOS integrated circuit of 22nm.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims (9)

1. a strain SiGe returns type vertical-channel NMOS integrated device, it is characterized in that the conducting channel of said device is back type, and channel direction is vertical with substrate surface.
2. strain SiGe according to claim 1 returns type vertical-channel NMOS integrated device, it is characterized in that channel region is the strain SiGe material, and the Ge component changes in gradient in the raceway groove, and is tensile strain at channel direction.
3. strain SiGe according to claim 1 returns type vertical-channel NMOS integrated device; It is characterized in that said device is included in N type Si epitaxial loayer, a N type strain SiGe layer, P type strain SiGe layer, the 2nd N type strain SiGe layer and the N type Si layer of growing successively on the substrate.
4. strain SiGe according to claim 1 returns type vertical-channel NMOS integrated device, it is characterized in that, said N type Si epitaxy layer thickness is 1.5～2.5 μ m, and doping content is 5 * 10 19～5 * 10 20Cm -3, as the drain region; A said N type strain SiGe layer thickness is 3 ~ 5nm, and doping content is 5 * 10 17～5 * 10 18Cm -3, the Ge component is 10%, as the first lightly-doped source drain region (LDD) layer; Said P type strain SiGe layer thickness is 22～45nm, and doping content is 5 * 10 16～5 * 10 17Cm -3, the Ge component is that lower floor is 10%, the upper strata is 20～30% Gradient distribution, as channel region; Said the 2nd N type strain SiGe layer thickness is 3 ~ 5nm, and doping content is 5 * 10 17～5 * 10 18Cm -3, the Ge component is 20～30%, as the second lightly-doped source drain region (LDD) layer; Said N type Si layer thickness is 200～400nm, and doping content is 5 * 10 19～5 * 10 20Cm -3, as the source region.
5. a strain SiGe returns the preparation method of type vertical-channel NMOS integrated device, it is characterized in that, comprises the steps:
The first step, to choose doping content be 5 * 10 15～5 * 10 16Cm -3P type Si substrate slice;
Second goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, five layer materials of on substrate, growing continuously: ground floor is that thickness is the N type Si epitaxial loayer of 1.5～2.5 μ m, and doping content is 5 * 10 19～5 * 10 20Cm -3, as the drain region; The second layer is that thickness is the N type strain SiGe layer of 3 ~ 5nm, and doping content is 5 * 10 17～5 * 10 18Cm -3, the Ge component is 10%, as the first lightly-doped source drain region (LDD) layer; The 3rd layer is that thickness is the P type strain SiGe layer of 22～45nm, and doping content is 5 * 10 16～5 * 10 17Cm -3, the Ge component is that lower floor is 10%, the upper strata is 20～30% Gradient distribution, as channel region; The 4th layer is that thickness is the 2nd N type strain SiGe layer of 3 ~ 5nm, and doping content is 5 * 10 17～5 * 10 18Cm -3, the Ge component is 20～30%, as the second lightly-doped source drain region (LDD) layer; Layer 5 is that thickness is the N type Si layer of 200～400nm, and doping content is 5 * 10 19～5 * 10 20Cm -3, as the source region;
The deep trouth district is isolated in the 3rd step, photoetching, utilizes dry etch process, etches the deep trouth that the degree of depth is 2.5～3.5 μ m in isolated area;
The 4th the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, be the SiO of 20～40nm at the substrate surface deposition thickness 2Layer all covers the deep trouth inner surface, and deposit Poly-Si forms deep trench isolation with filling up in the deep trouth again;
The 5th step, photolithographic source are leaked isolated area, utilize dry etch process, leak isolated area in the source and etch the shallow slot that the degree of depth is 0.5～0.7 μ m; Utilize chemical vapor deposition (CVD) method again,, in shallow slot, fill SiO at 600～800 ℃ 2At last,, remove unnecessary oxide layer, form shallow-trench isolation with chemico-mechanical polishing (CMP) method;
The 6th the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2And layer of sin, etch away SiN and SiO 2Form and leak the bonding pad window; Trench region is leaked in photoetching, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.7～0.9 μ m; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is the 2nd SiO of 20～40nm at the substrate surface growth thickness 2Layer forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the 2nd SiO of drain region channel bottom 2Layer; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, the deposit doping content is 5 * 10 19～5 * 10 20Cm -3N type Poly-Si will fill up groove, remove the unnecessary Poly-Si in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad;
The 7th the step, utilize dry etch process, etch away SiN and SiO 2The barrier layer; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2And layer of sin, etch away the SiN and the SiO of gate region 2Form the grid window; Utilize dry etch process, etch the gate groove that the degree of depth is 0.7～0.9 μ m; Utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of the high-k of 6～10nm at the substrate surface deposition thickness 2Layer as gate dielectric layer, at 600～800 ℃, is 5 * 10 in substrate surface deposit one deck doping content 19～5 * 10 20Cm -3N type Poly-Si, and gate groove filled up, remove surface portion Poly-Si, form grid;
The 8th step, etching source region form nmos device;
The 9th the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface growth regulation Three S's iO 2The layer, and on grid, source and drain region lithography fair lead;
The tenth step, metallization, photoetching lead-in wire form drain electrode, source electrode and gate metal lead-in wire, and constituting conducting channel length is the NMOS integrated circuit of 22～45nm.
6. method according to claim 5 is characterized in that, channel length is confirmed according to the P type strain SiGe layer thickness of the second step deposit.
7. method according to claim 5 is characterized in that channel length is got 22～45nm.
8. method according to claim 5 is characterized in that, maximum temperature related among this preparation method is according to chemical vapor deposition (CVD) the technological temperature decision in second, four, five, six, seven and nine steps, and maximum temperature is smaller or equal to 800 ℃.
9. a strain SiGe returns the preparation method of type vertical-channel nmos device integrated circuit, it is characterized in that, comprises the steps:
Step 1, the epitaxial material preparation process:
(1a) choosing doping content is 5 * 10 16Cm -3The P type Si substrate slice of magnitude;
(1b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on substrate growth one layer thickness be the N type Si epitaxial loayer of 2 μ m as the drain region, doping content is 5 * 10 20Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth thickness is the N type strain SiGe layer of 3nm on substrate, and doping content is 5 * 10 18Cm -3, the Ge component is 10%, as the first lightly-doped source drain region (LDD) layer;
(1d) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the Si epitaxial loayer growth one layer thickness be the P type SiGe layer of 22nm as channel region, doping content is 5 * 10 17Cm -3, the Ge component is that lower floor is 10%, the upper strata is 30% Gradient distribution;
(1e) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth thickness is the 2nd N type strain SiGe layer of 3nm on substrate, and doping content is 5 * 10 18Cm -3, the Ge component is 30%, as the second lightly-doped source drain region (LDD) layer;
(1f) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the SiGe layer growth one layer thickness be the N type Si layer of 300nm as the source region, doping content is 5 * 10 20Cm -3
Step 2, the isolation preparation step:
(2a) the deep trouth district is isolated in photoetching, utilizes dry etch process, etches the deep trouth that the degree of depth is 3 μ m in isolated area;
(2b) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is the SiO of 40nm at the substrate surface deposition thickness 2Layer all covers the deep trouth inner surface;
(2c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill Poly-Si, form deep trench isolation at 800 ℃;
(2d) the deep trouth district is isolated in photoetching, utilizes dry etch process, leaks isolated area in the source and etches the shallow slot that the degree of depth is 0.6 μ m;
(2e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2
(2f), remove unnecessary oxide layer, form shallow-trench isolation with chemico-mechanical polishing (CMP) method;
Step 3, leak the bonding pad preparation process:
(3a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(3b) photoetching SiN and SiO 2Form and leak the bonding pad window;
(3c) utilize dry etch process, etching the degree of depth is the leakage groove of 0.8 μ m;
(3d) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is the 2nd SiO of 40nm at the substrate surface growth thickness 2Layer forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the 2nd SiO of drain region channel bottom 2Layer;
(3e) utilize chemical vapor deposition (CVD) method, at 800 ℃, the deposit doping content is 5 * 10 20Cm -3N type Poly-Si will fill up groove, remove the unnecessary Poly-Si in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad;
Step 4, NMOS forms step:
(4a) utilize dry etch process, etch away SiN and SiO 2The barrier layer;
(4b) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2, deposit layer of sin in the above again;
The SiN of (4c) photoetching gate region and SiO 2, form the grid window;
(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.7 μ m;
(4e) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 400 ℃, is the HfO of the high-k of 10nm at the substrate surface growth thickness 2Layer is as gate dielectric layer;
(4f) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is 5 * 10 in substrate surface deposit doping content 20Cm -3N type Poly-Si, and gate groove filled up, remove surface portion Poly-Si, form grid;
(4g) etching source region forms nmos device;
Step 5 constitutes NMOS integrated circuit step:
(5a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface growth regulation Three S's iO 2Layer;
(5b) lithography fair lead on grid, source and drain region;
(5c) metallization;
(5d) photoetching lead-in wire forms drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, and constituting conducting channel length is the NMOS integrated circuit of 22nm.
CN201210244375.3A 2012-07-16 2012-07-16 Strain SiGe square-in-square type channel NMOS (N-channel Metal Oxide Semiconductor) integrated device and preparation method thereof Expired - Fee Related CN102751331B (en)

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Publication number Priority date Publication date Assignee Title
US20030227072A1 (en) * 2002-06-10 2003-12-11 Leonard Forbes Output prediction logic circuits with ultra-thin vertical transistors and methods of formation
US20070205468A1 (en) * 2001-11-30 2007-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Complementary Metal Oxide Semiconductor Transistor Technology Using Selective Epitaxy of a Strained Silicon Germanium Layer
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070205468A1 (en) * 2001-11-30 2007-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Complementary Metal Oxide Semiconductor Transistor Technology Using Selective Epitaxy of a Strained Silicon Germanium Layer
US20030227072A1 (en) * 2002-06-10 2003-12-11 Leonard Forbes Output prediction logic circuits with ultra-thin vertical transistors and methods of formation
US20080237637A1 (en) * 2003-06-17 2008-10-02 International Business Machines Corporation ULTRA SCALABLE HIGH SPEED HETEROJUNCTION VERTICAL n-CHANNEL MISFETS AND METHODS THEREOF

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