CN102769004A - Electronic component packaging structure - Google Patents
Electronic component packaging structure Download PDFInfo
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- CN102769004A CN102769004A CN2012100237357A CN201210023735A CN102769004A CN 102769004 A CN102769004 A CN 102769004A CN 2012100237357 A CN2012100237357 A CN 2012100237357A CN 201210023735 A CN201210023735 A CN 201210023735A CN 102769004 A CN102769004 A CN 102769004A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
Abstract
The present invention discloses an electronic component packaging structure which comprises a semiconductor component, a first protection layer, a first conductor welding pad, a second conductor welding pad, at least one break-over structure and a second protection layer. The semiconductor component comprises a semiconductor base electrode, an emitter, a collector and a grid electrode. The emitter and the grid electrode are arranged on the first surface of the semiconductor base electrode, the collector is arranged on a second surface of the semiconductor base electrode. The first protection layer is arranged on the first surface of the semiconductor base electrode around the grid electrode. The first conductor welding pad is arranged on the first protection layer. The second conductor welding pad is arranged above the collector of the second surface of the semiconductor base electrode. The break-over structure is electrically connected with the first conductor welding pad and the second conductor welding pad after passing through the first protection layer, the first surface and the second surface of the semiconductor base electrode. The second protection layer is arranged between the break-over structure and the semiconductor base electrode.
Description
Technical field
The present invention relates to a kind of integrated circuit, and particularly relate to a kind of electronic element packaging structure.
Background technology
Traditional power component is to adopt top-bottom electrode structures to be separately positioned on two surfaces of chip.Because the power consumption of power chip is high, especially be applied to the power chip of electric motor car, how kilowatt more than the grade, so heat radiation is a major challenge.It is the structure of adopting upper/lower electrode that the power model that uses now still belongs to traditional power component; Such structure will use routing and welding manner to accomplish module package in encapsulation simultaneously, and its manufacturing process steps is comparatively complicated and its sealed in unit cost is quite high again.
Summary of the invention
The object of the present invention is to provide a kind of electronic element packaging structure can utilize simple mode to accomplish encapsulation, and have more area of dissipation,, increase reliability to promote heat dissipation.
For reaching above-mentioned purpose, the present invention proposes a kind of electronic element packaging structure, comprises semiconductor element, first protective layer, the first conductor weld pad, the second conductor weld pad and at least one conducting structure.Semiconductor element comprises semiconductor base stage, the first conductivity type matrix area, the second conductivity type doped region, first dielectric, second dielectric layer, emitter-base bandgap grading, the collection utmost point and grid.Semiconductor-based have first surface and a second surface, and first surface and second surface are relative.The collection utmost point is positioned on the second surface of semiconductor base stage.The first conductivity type matrix area is positioned on the first surface of semiconductor base stage.The second conductivity type doped region is arranged in the first conductivity type matrix area.Grid is positioned on the first surface of semiconductor base stage; Said first conductivity type matrix area in cover part and the said second conductivity type doped region of part, and grid is isolated with first surface, the first conductivity type matrix area and the second conductivity type doped region of first dielectric layer and semiconductor base stage.The second dielectric layer cover gate has opening in second dielectric layer, and opening runs through the second conductivity type doped region, and the bottom that extends to opening exposes the first conductivity type matrix area.Emitter-base bandgap grading is positioned on second dielectric layer of semiconductor base stage, and is filled in the opening, is electrically connected the second conductivity type doped region and the first conductivity type matrix area.First protective layer is positioned on the first surface of the semiconductor base stage around the grid.The first conductor weld pad is positioned on first protective layer.The second conductor weld pad is positioned at the collection utmost point top on the second surface of semiconductor base stage.Above-mentioned conducting structure runs through first surface and the second surface and the collection utmost point of first protective layer, conductor base stage.Conducting structure comprises the conductor pin and second protective layer.Conductor pin is electrically connected the first conductor weld pad and the second conductor weld pad.Second protective layer is between conductor pin and semiconductor base stage.
Said according to one embodiment of the invention, it is characterized in that also comprising first projection and second projection.First projection is electrically connected with the said first conductor weld pad.Second projection is electrically connected with said emitter-base bandgap grading.
Said according to one embodiment of the invention, it is characterized in that the said first conductor weld pad comprises the projection lower metal layer.
Said according to one embodiment of the invention, it is characterized in that the material of the said first conductor weld pad comprises nickel or gold, or its alloy.
Said according to one embodiment of the invention, it is characterized in that the material of the said second conductor weld pad comprises metal or metal alloy.
Said according to one embodiment of the invention, the material of the wherein said second conductor weld pad comprises copper or aluminium, or its alloy.
Said according to one embodiment of the invention, be characterised in that also to comprise the first conductor bonding wire and the second conductor bonding wire.The first conductor bonding wire is electrically connected with the said first conductor weld pad.The second conductor bonding wire is electrically connected with said emitter-base bandgap grading.
Said according to one embodiment of the invention, it is characterized in that the material of said conductor pin comprises metal or metal alloy.
Said according to one embodiment of the invention, it is characterized in that the material of said conductor pin comprises copper, tungsten or aluminium, or its alloy.
Said according to one embodiment of the invention, it is characterized in that the material of said first protective layer comprises silicon dioxide, silicon nitride or aluminium nitride.
Said according to one embodiment of the invention, it is characterized in that the material of said second protective layer comprises silicon dioxide, silicon nitride or aluminium nitride.
Said according to one embodiment of the invention; It is characterized in that the said first conductivity type matrix area comprises that P type body region and the said second conductivity type doped region comprise N type doped region, or the said first conductivity type matrix area comprises that N type body region and the said second conductivity type doped region comprise P type doped region.The present invention proposes a kind of electronic element packaging structure again, comprising: semiconductor element, protective layer and conductor weld pad.Semiconductor element comprises semiconductor base stage, the first conductivity type matrix area, the second conductivity type doped region, first dielectric, second dielectric layer, emitter-base bandgap grading, the collection utmost point and grid.Comprise first district, second district and the 3rd district on the first surface of semiconductor base stage, the 3rd district is positioned between first district and second district.The collection utmost point is positioned in second district of semiconductor base stage.The first conductivity type matrix area is positioned on the first surface of semiconductor base stage.The second conductivity type doped region is arranged in the first conductivity type matrix area.Grid is positioned at the top, first district of semiconductor base stage, said first conductivity type matrix area in cover part and the said second conductivity type doped region of part.Grid is isolated with first surface, the first conductivity type matrix area and the second conductivity type doped region of first dielectric layer and semiconductor base stage.The second dielectric layer cover gate has opening in second dielectric layer, and opening runs through the second conductivity type doped region, and the bottom that extends to opening exposes the first conductivity type matrix area.Emitter-base bandgap grading is positioned on second dielectric layer of semiconductor base stage, and is filled in the opening, is electrically connected the second conductivity type doped region and the first conductivity type matrix area.Protective layer is positioned in the 3rd district.The conductor weld pad is positioned at collection and extremely goes up.
Said according to one embodiment of the invention, it is characterized in that also comprising first projection and second projection.First projection is electrically connected with said conductor weld pad.Second projection is electrically connected with said emitter-base bandgap grading.
Said according to one embodiment of the invention, it is characterized in that said conductor weld pad comprises the projection lower metal layer.
Said according to one embodiment of the invention, it is characterized in that the material of said conductor weld pad comprises nickel or gold, or its alloy.
Said according to one embodiment of the invention, be characterised in that also to comprise the first conductor bonding wire and the second conductor bonding wire.The first conductor bonding wire is electrically connected with said conductor weld pad.The second conductor bonding wire is electrically connected with said emitter-base bandgap grading.
Said according to one embodiment of the invention, it is characterized in that the material of said protective layer comprises silicon dioxide, silicon nitride or aluminium nitride.
Said according to one embodiment of the invention, it is characterized in that the material of said protective layer is identical with the material of said first dielectric layer.
Said according to one embodiment of the invention, it is characterized in that the material of material and said first dielectric layer of said protective layer is different.
Said according to one embodiment of the invention; It is characterized in that the said first conductivity type matrix area comprises that P type body region and the said second conductivity type doped region comprise N type doped region, or the said first conductivity type matrix area comprises that N type body region and the said second conductivity type doped region comprise P type doped region.Based on above-mentioned, electronic element packaging structure of the present invention can utilize routing or welding manner to accomplish encapsulation, and has more area of dissipation, to promote heat dissipation, increases reliability.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended accompanying drawing to elaborate as follows.
Description of drawings
Fig. 1 is the generalized section of a kind of electronic element packaging structure of illustrating of first embodiment of the invention.
Fig. 2 is the generalized section of a kind of electronic element packaging structure of illustrating of second embodiment of the invention.
Fig. 3 is the generalized section of a kind of electronic element packaging structure of illustrating of third embodiment of the invention.
Fig. 4 is the generalized section of a kind of electronic element packaging structure of illustrating of fourth embodiment of the invention.
The main element symbol description
10a, 10b, 110a, 110b: electronic element packaging structure
12,112: the semiconductor base stage
12a: first surface
12b: second surface
14,114: semiconductor element
16: the first protective layers
17: the second protective layers
18: the first conductor weld pads
19: via
20: the second conductor weld pads
21: conductor pin
22: conducting structure
24,124: the first projections
26,126: the second projections
28,128: emitter-base bandgap grading
30,130: the collection utmost point
32,132: grid
32,132: the first dielectric layers
34,134: the second dielectric layers
38,138: opening
40,140: the first conductivity type matrix areas
42,142: the second conductivity type doped regions
44,144: the first conductor bonding wires
46,146: the second conductor bonding wires
50,170: fin
60,160: heat-conducting glue
100: substrate
100a, 112a: surface
116: protective layer
118: the conductor weld pad
150: the first districts
152: the second districts
154: the three districts
Embodiment
Fig. 1 is the generalized section according to a kind of electronic element packaging structure that first embodiment of the invention illustrated.
Please with reference to Fig. 1, electronic element packaging structure 10a comprises semiconductor element 14, first protective layer 16, the first conductor weld pad 18, the second conductor weld pad 20, at least one conducting structure 22, first projection 24 and second projection 26.
The material of emitter-base bandgap grading 28 can be a metal, for example is aluminium, copper or gold.The material of the collection utmost point 30 for example is to have the epitaxial silicon that first conductivity type mixes.The material of grid 32 for example is to have the polysilicon that second conductivity type mixes.In one embodiment, described first conductivity type of this specification embodiment/second conductivity type for example is P type/N type.In another embodiment, described first conductivity type of this specification embodiment/second conductivity type for example is N type/P type.It for example is phosphorus, arsenic or antimony that the P type mixes.It for example is boron, indium or gallium that the N type mixes.
In one embodiment, semiconductor element 14 also comprises the first conductivity type matrix area 40 and the second conductivity type doped region 42.The first conductivity type matrix area 40 is arranged in the first surface 12a of semiconductor base stage 12.Grid 32 is understood the cover parts first conductivity type matrix area 40 and the part second conductivity type doped region 42, and is isolated with first surface 12a, the first conductivity type matrix area 40 and the second conductivity type doped region 42 of first dielectric layer 34 with semiconductor base stage 12.In addition, semiconductor element 14 also has opening 38, and it is arranged in second dielectric layer 36, and runs through the second conductivity type doped region 42, and the bottom that extends to opening 38 is to expose the first conductivity type matrix area 40.The degree of depth of opening 38 for example is 20000 dust to 40000 dusts.
On the first surface 12a of the first conductivity type matrix area 40 and the second conductivity type doped region 42 and semiconductor base stage 12, be sequentially provided with first dielectric layer 34, grid 32, second dielectric layer 36.Wherein in the first conductivity type matrix area 40, the second conductivity type doped region 42, second dielectric layer 36 opening 38 is set promptly; Make the emitter-base bandgap grading 28 can the shape setting of T font and be formed in the opening 38, and emitter-base bandgap grading 28 is directly contacted with the first conductivity type matrix area 40 of opening 38 bottoms, the second conductivity type doped region 42 and second dielectric layer 36 of opening 38 sidewalls respectively.
The first surface 12a that first protective layer 16 is arranged at the semiconductor base stage 12 around the grid 32 upward and with first dielectric layer 34 is connected.The material of first protective layer 16 can be a dielectric material, for example is silicon dioxide, silicon nitride or aluminium nitride.The thickness of first protective layer 16 for example is 5000 dust to 20000 dusts.
The first conductor weld pad 18 is positioned on first protective layer 16 of first surface 12a top of semiconductor base stage 12.The first conductor weld pad 18 comprises projection lower metal layer (UBM), and its material for example is nickel or gold.The second conductor weld pad 20 is positioned on the collection utmost point 30 of second surface 12b of semiconductor base stage 12.The second conductor weld pad, 20 materials comprise metal or metal alloy, for example are copper or aluminium.
Conducting structure 22 is positioned among the via 19, and via 19 runs through first surface 12a, second surface 12b and the collection utmost point 30 of first protective layer 16, semiconductor base stage 12.Conducting structure 22 comprises the conductor pin 21 and second protective layer 17.Conductor pin 21 runs through first protective layer 16 and is electrically connected the first conductor weld pad 18 respectively and the second conductor weld pad 20.The material of conductor pin 21 comprises metal or metal alloy, for example is copper, tungsten or aluminium or its alloy.Wherein conducting structure 22 can be one or most individual with via 19, represent with two in the accompanying drawings, but the present invention is not as limit.Second protective layer 17 is between conductor pin 21 and semiconductor base stage 12.The material of second protective layer 17 can be identical with the material of first protective layer 16 or different.The material of second protective layer 17 can be a dielectric material, for example is silicon dioxide, silicon nitride or aluminium nitride.The thickness of second protective layer 17 for example is 5000 dust to 20000 dusts.
Above-mentioned electronic element packaging structure 10a can also comprise fin (heatsink) 50.Fin 50 can be arranged at a side of electrode 20.The material of fin 50 can be metal or insulating material.If the material of fin 50 is a metal, between electrode 20 and fin 50, can be connected with heat-conducting glue 60.If the material of fin 50 is an insulating material, for example be pottery or high heat radiation organic material, then fin 50 can directly contact with electrode 20.
Fig. 2 is the generalized section according to a kind of electronic element packaging structure that second embodiment of the invention illustrated.
Please with reference to Fig. 2; The member of the electronic element packaging structure 10b of present embodiment and the electronic element packaging structure 10a of above-mentioned first embodiment are closely similar, and it comprises semiconductor element 14, first protective layer 16, second protective layer 17, the first conductor weld pad 18, the second conductor weld pad 20, at least one conducting structure 22 equally.Electronic element packaging structure 10b also can comprise fin 50 again.Electronic element packaging structure 10b is different with electronic element packaging structure 10a be in: the first conductor bonding wire (conductive bond wire), the 44 and second conductor bonding wire 46 replaces first projection 24 and second projection 26 respectively.The first conductor bonding wire 44 is electrically connected with conductor weld pad 18.The second conductor bonding wire 46 is electrically connected with emitter-base bandgap grading 28.The material of the first conductor bonding wire (conductive bond wire), the 44 and second conductor bonding wire 46 comprises metal or metal alloy, for example is gold, aluminium or copper.
Fig. 3 is the generalized section according to a kind of electronic element packaging structure that third embodiment of the invention illustrated.
Please with reference to Fig. 3, the present invention proposes a kind of electronic element packaging structure 110a again, comprising: semiconductor element 114, protective layer 116, conductor weld pad 118, first projection 124 and second projection 126.
In one embodiment, semiconductor element 114 also comprises the first conductivity type matrix area 140 and the second conductivity type doped region 142.The first conductivity type matrix area 140 is arranged in first district 150 of the first surface 12a of semiconductor base stage 112.Grid 132 is understood the cover parts first conductivity type matrix area 140 and the part second conductivity type doped region 142, and is isolated with first surface 112a, the first conductivity type matrix area 140 and the second conductivity type doped region 142 of first dielectric layer 134 with semiconductor base stage 112.In addition, semiconductor element 114 also has opening 138, and it is arranged in second dielectric layer 136, and runs through the second conductivity type doped region 142, and the bottom that extends to opening 138 is to expose the first conductivity type matrix area 140.The degree of depth of opening 138 for example is 20000 dust to 40000 dusts.
In other words, on the first surface 112a of the first conductivity type matrix area 140 and the second conductivity type doped region 142 and semiconductor base stage 112, be sequentially provided with first dielectric layer 134, grid 132, second dielectric layer 136.Wherein in the first conductivity type matrix area 140, the second conductivity type doped region 142, second dielectric layer 136 opening 138 is set promptly; Make the emitter-base bandgap grading 128 can the shape setting of T font and be formed in the opening 138, and emitter-base bandgap grading 128 is directly contacted with the first conductivity type matrix area 140, the second conductivity type doped region, 142 second dielectric layers 136 respectively.
The material of the semiconductor base stage 112 of the semiconductor element 114 of present embodiment, emitter-base bandgap grading 128, the collection utmost point 130 and grid 132, protective layer 116, conductor weld pad 118, first projection 124 and second projection 126; Can adopt the material of semiconductor base stage 12, emitter-base bandgap grading 28, the collection utmost point 30 and grid 32, protective layer 16, conductor weld pad 18, first projection 24 and second projection 26 of the semiconductor element 14 of the foregoing description, repeat no more in this.
In addition, above-mentioned electronic element packaging structure 110a can also comprise fin 170.Fin 170 can be arranged on the surperficial 100a of substrate 100.If the material of fin 170 is a metal, between substrate 100 and fin 170, can be connected with heat-conducting glue 160.If the material of fin 170 is an insulating material, for example be pottery or high heat radiation organic material, then fin 170 can directly contact with the surperficial 100a of substrate 100.
Fig. 4 is the generalized section according to a kind of electronic element packaging structure that fourth embodiment of the invention illustrated.
Please with reference to Fig. 4, the member of the electronic element packaging structure 110b of present embodiment and the electronic element packaging structure 110a of above-mentioned the 3rd embodiment are closely similar, and it comprises semiconductor element 114, protective layer 116, the first conductor weld pad 118 equally.Electronic element packaging structure 110b also can comprise fin 170 again.Electronic element packaging structure 110b is different with electronic element packaging structure 110a be in: the first conductor bonding wire 144 and the second conductor bonding wire 146 replace first projection 124 and second projection 126 respectively.The first conductor bonding wire 144 is electrically connected with conductor weld pad 118.The second conductor bonding wire 146 is electrically connected with emitter-base bandgap grading 128.The material of the first conductor bonding wire 144 and the second conductor bonding wire 146 for example is gold, aluminium or copper.
The present invention changes the packaged type of existing top-bottom electrode structures; Utilization runs through conducting structure (TSV) structure on two surfaces of semiconductor base stage; Or the electrode of semiconductor element is arranged on the same one side of chip, can cover crystal type power chip is arranged on the substrate.The another side that chip is not provided with electrode can be connected with fin, makes it have more heat dissipation design.Compare with existing power model, existing is to encapsulate with the routing mode and seal with the silica gel mode in the upper end of chip, fully only dispels the heat with the substrate bottom surface, and structure of the present invention then has more area of dissipation, can promote the reliability of chip.
Though disclosed the present invention in conjunction with above embodiment; Yet it is not in order to limit the present invention; Be familiar with this operator in the technical field under any; Do not breaking away from the spirit and scope of the present invention, can do a little change and retouching, thus protection scope of the present invention should with enclose claim was defined is as the criterion.
Claims (21)
1. electronic element packaging structure comprises:
Semiconductor element comprises:
Semiconductor-based have first surface and a second surface, and said first surface is relative with said second surface;
The collection utmost point is positioned on the said second surface of said semiconductor base stage;
The first conductivity type matrix area is arranged in the said first surface of said semiconductor base stage;
The second conductivity type doped region is arranged in the said first conductivity type matrix area;
Grid is positioned on the said first surface of said semiconductor base stage; Said first conductivity type matrix area in cover part and the said second conductivity type doped region of part, and said grid is isolated with the said first surface of first dielectric layer and said semiconductor base stage, the said first conductivity type matrix area and the said second conductivity type doped region;
Second dielectric layer covers said grid, has an opening in said second dielectric layer, and said opening runs through the said second conductivity type doped region, and the bottom that extends to said opening is to expose the said first conductivity type matrix area; And
Emitter-base bandgap grading is positioned on said second dielectric layer of said semiconductor base stage, and is filled in the said opening, is electrically connected said second conductivity type doped region and the said first conductivity type matrix area;
First protective layer is positioned on the said first surface of said grid said semiconductor base stage on every side, and is connected with said first dielectric layer;
The first conductor weld pad is positioned on said first protective layer;
The second conductor weld pad is positioned at the said collection of the said second surface top of said semiconductor base stage and extremely goes up; And
At least one conducting structure runs through the said first surface of said first protective layer, said semiconductor base stage, said second surface and the said collection utmost point, and is electrically connected said first conductor weld pad and the said second conductor weld pad, and said conducting structure comprises:
Conductor pin is positioned among the said semiconductor base stage; And
Second protective layer is between said conductor pin and said semiconductor base stage.
2. electronic element packaging structure as claimed in claim 1 is characterized in that also comprising:
First projection is electrically connected with the said first conductor weld pad; And
Second projection is electrically connected with said emitter-base bandgap grading.
3. electronic element packaging structure as claimed in claim 2 is characterized in that the said first conductor weld pad comprises the projection lower metal layer.
4. electronic element packaging structure as claimed in claim 3 is characterized in that the material of the said first conductor weld pad comprises nickel or gold, or its alloy.
5. electronic element packaging structure as claimed in claim 1 is characterized in that the material of the said second conductor weld pad comprises metal or metal alloy.
6. electronic element packaging structure as claimed in claim 1, the material of the wherein said second conductor weld pad comprises copper or aluminium, or its alloy.
7. electronic element packaging structure as claimed in claim 1 is characterised in that also to comprise:
The first conductor bonding wire is electrically connected with the said first conductor weld pad; And
The second conductor bonding wire is electrically connected with said emitter-base bandgap grading.
8. electronic element packaging structure as claimed in claim 1 is characterized in that the material of said conductor pin comprises metal or metal alloy.
9. electronic element packaging structure as claimed in claim 1 is characterized in that the material of said conductor pin comprises copper, tungsten or aluminium, or its alloy.
10. electronic element packaging structure as claimed in claim 1 is characterized in that the material of said first protective layer comprises silicon dioxide, silicon nitride or aluminium nitride.
11. electronic element packaging structure as claimed in claim 1 is characterized in that the material of said second protective layer comprises silicon dioxide, silicon nitride or aluminium nitride.
12. electronic element packaging structure as claimed in claim 1; It is characterized in that the said first conductivity type matrix area comprises that P type body region and the said second conductivity type doped region comprise N type doped region, or the said first conductivity type matrix area comprises that N type body region and the said second conductivity type doped region comprise P type doped region.
13. an electronic element packaging structure comprises:
Semiconductor element comprises:
Semiconductor base stage, the first surface of said semiconductor base stage comprise first district, second district and the 3rd district, and said the 3rd district is positioned between said first district and said second district;
The collection utmost point is positioned in said second district of said semiconductor base stage;
The first conductivity type matrix area is arranged in the said first surface of said semiconductor base stage;
The second conductivity type doped region is arranged in the said first conductivity type matrix area;
Grid is positioned at the top, said first district of said semiconductor base stage; Said first conductivity type matrix area in cover part and the said second conductivity type doped region of part, and said grid is isolated with the said first surface of one first dielectric layer and said semiconductor base stage, the said first conductivity type matrix area and the said second conductivity type doped region;
Second dielectric layer covers said grid, has an opening in said second dielectric layer, and said opening runs through the said second conductivity type doped region, and the bottom that extends to said opening is to expose the said first conductivity type matrix area; And
Emitter-base bandgap grading is positioned on said second dielectric layer of said semiconductor base stage, and is filled in the said opening, is electrically connected said second conductivity type doped region and the said first conductivity type matrix area;
Protective layer is positioned in said the 3rd district; And
The conductor weld pad is positioned at said collection and extremely goes up.
14. electronic element packaging structure as claimed in claim 13 is characterized in that also comprising:
First projection is electrically connected with said conductor weld pad; And
Second projection is electrically connected with said emitter-base bandgap grading.
15. electronic element packaging structure as claimed in claim 14 is characterized in that said conductor weld pad comprises the projection lower metal layer.
16. electronic element packaging structure as claimed in claim 15 is characterized in that the material of said conductor weld pad comprises nickel or gold, or its alloy.
17. electronic element packaging structure as claimed in claim 13 is characterised in that also to comprise:
The first conductor bonding wire is electrically connected with said conductor weld pad; And
The second conductor bonding wire is electrically connected with said emitter-base bandgap grading.
18. electronic element packaging structure as claimed in claim 13 is characterized in that the material of said protective layer comprises silicon dioxide, silicon nitride or aluminium nitride.
19. electronic element packaging structure as claimed in claim 13 is characterized in that the material of said protective layer is identical with the material of said first dielectric layer.
20. electronic element packaging structure as claimed in claim 13 is characterized in that the material of material and said first dielectric layer of said protective layer is different.
21. electronic element packaging structure as claimed in claim 13; It is characterized in that the said first conductivity type matrix area comprises that P type body region and the said second conductivity type doped region comprise N type doped region, or the said first conductivity type matrix area comprises that N type body region and the said second conductivity type doped region comprise P type doped region.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161481750P | 2011-05-03 | 2011-05-03 | |
| US61/481,750 | 2011-05-03 |
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| CN102769004A true CN102769004A (en) | 2012-11-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2012100237357A Pending CN102769004A (en) | 2011-05-03 | 2012-02-03 | Electronic component packaging structure |
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| CN (1) | CN102769004A (en) |
| TW (1) | TWI489601B (en) |
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| CN111009507A (en) * | 2018-10-05 | 2020-04-14 | 南亚科技股份有限公司 | Semiconductor structure and preparation method thereof |
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| JP5258207B2 (en) * | 2007-05-29 | 2013-08-07 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Semiconductor device |
| US8299566B2 (en) * | 2008-08-08 | 2012-10-30 | International Business Machines Corporation | Through wafer vias and method of making same |
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| CN105514077A (en) * | 2014-10-13 | 2016-04-20 | 通用电气公司 | Power overlay structure having wirebonds and method of manufacturing same |
| EP3010038A3 (en) * | 2014-10-13 | 2016-07-20 | General Electric Company | Power overlay structure having wirebonds and method of manufacturing same |
| CN105514077B (en) * | 2014-10-13 | 2020-03-31 | 通用电气公司 | Power overlay structure with wire bonds and method of making the same |
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| US11011468B2 (en) | 2018-10-05 | 2021-05-18 | Nanya Technology Corporation | Semiconductor structure and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201246479A (en) | 2012-11-16 |
| TWI489601B (en) | 2015-06-21 |
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Application publication date: 20121107 |