CN102791075B - Manufacture method of loader with three-dimensional inductance and structure of loader - Google Patents

Manufacture method of loader with three-dimensional inductance and structure of loader Download PDF

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Publication number
CN102791075B
CN102791075B CN201110134743.4A CN201110134743A CN102791075B CN 102791075 B CN102791075 B CN 102791075B CN 201110134743 A CN201110134743 A CN 201110134743A CN 102791075 B CN102791075 B CN 102791075B
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inductance
inductance department
department
height
appears
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CN102791075A (en
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郭志明
徐佑铭
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Chipbond Technology Corp
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Chipbond Technology Corp
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Abstract

The invention relates to a manufacture method of a loader with three-dimensional inductance and a structure of the loader. The manufacture method of the loader with three-dimensional inductance comprises the following steps that a base plate is provided; a first light resistance layer is formed; the first light resistance layer is patternized; a first metal layer is formed, and the first metal layer is provided with a plurality of first inductance parts with first height; the first light resistance layer is removed; a first dielectric layer is formed; a second light resistance layer is formed; the second light resistance layer is patternized; a second metal layer is formed, and the second metal layer is provided with a second inductance part with second height, a plurality of third inductance parts with third height and a plurality of fourth inductance parts with fourth height; the second light resistance layer is removed; a second dielectric layer is formed; a third light resistance layer is formed; and the third light resistance layer is patternized, and a third metal layer is provided with a fifth inductance part with fifth height and a plurality of sixth inductance parts with sixth height, wherein the second height, the third height and the fourth height are greater than the first height, the fifth height and the sixth height.

Description

There is carrier manufacture method and the structure thereof of three-dimensional inductance
Technical field
The present invention relates to a kind of carrier manufacture method, particularly relate to a kind of carrier manufacture method and the structure thereof with three-dimensional inductance.
Background technology
Existing known inductance mostly is planar inductor, it designs inductive patterns and line pattern at grade, and because inductance and circuit are when same plane, the problem of parasitic capacitance must be overcome, therefore cause the size of chip to reduce, and planar inductor cannot surround several circle with same radius and only can become the structure that turbine-like radius becomes large.
As can be seen here, above-mentioned existing inductance is at product structure and use, and obviously still has inconvenience and defect, and is urgently further improved.In order to solve above-mentioned Problems existing, relevant manufactures there's no one who doesn't or isn't seeks solution painstakingly, but have no applicable design for a long time to be completed by development, and common product does not have appropriate structure to solve the problem, this is obviously the anxious problem for solving of relevant dealer always.Therefore how to found a kind of new carrier manufacture method with three-dimensional inductance and structure thereof, belong to one of current important research and development problem in fact, also become the target that current industry pole need be improved.
Summary of the invention
The object of the invention is to, overcome the defect that existing inductance exists, and a kind of new carrier manufacture method with three-dimensional inductance and structure thereof are provided, technical problem to be solved makes it by the design of three-dimensional inductance, conplane wiring area can be reduced, and therefore can reduce the size of chip further, in addition, because three-dimensional inductance is the design of Different Plane, thus the flow direction of inductance is also from vertically becoming level, it contributes to covering the designs such as the electromagnetic coupled covering crystal module in brilliant technique, is very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of carrier manufacture method with three-dimensional inductance that the present invention proposes, it at least comprises the following step: provide a substrate, this substrate has a surface, one first weld pad and an overcoat, this first weld pad is arranged at this surface, this overcoat is formed at this surface, and this overcoat has one first welding pad opening, one first connects a setting area and multiple first inductance department setting area, this first welding pad opening appears this first weld pad and this first welding pad opening is positioned at this first to connect a setting area, form one first photoresist layer in this overcoat, this first photoresist layer of patterning is to form one first opening and multiple first inductance department slotted eye, and this first opening appears this first to connect a setting area, and those the first inductance department slotted eyes appear those the first inductance department setting areas, form a first metal layer in this first opening and those the first inductance department slotted eyes, to make this first metal layer, there is one first connection pad and multiple first inductance department, respectively this first inductance department has one first connection end point and one second connection end point, and this first inductance department has one first height, remove this first photoresist layer, forming one first dielectric layer in this overcoat covers this first metal layer, this first dielectric layer has one first connection pad opening, multiple first connection end point opening and multiple second connection end point opening, this the first connection pad opening appears this first connection pad, respectively this first connection end point opening appears respectively this first connection end point, and respectively this second connection end point opening appears respectively this second connection end point, form one second photoresist layer in this first dielectric layer, this second photoresist layer of patterning is to form one second inductance department providing holes, multiple 3rd inductance department providing holes and multiple 4th inductance department providing holes, this the second inductance department providing holes appears this first connection pad, respectively the 3rd inductance department providing holes appears respectively this first connection end point, and respectively the 4th inductance department providing holes appears respectively this second connection end point, form one second metal level in this second inductance department providing holes, those the 3rd inductance department providing holes and those the 4th inductance department providing holes, to make this second metal level, there is one second inductance department, multiple 3rd inductance department and a plurality of 4th inductance department, this second inductance department connects this first connection pad and this second inductance department has one first end face and one second height, respectively the 3rd inductance department connect respectively this second connection end point and respectively the 3rd inductance department there is one second end face and a third high degree, respectively the 4th inductance department connect respectively this first connection end point and respectively the 4th inductance department have one the 3rd end face and one the 4th height, this second height, this third high degree and the 4th height are greater than this first height, remove this second photoresist layer, forming one second dielectric layer in this first dielectric layer covers this second metal level, this second dielectric layer has that one second inductance department appears hole, multiple 3rd inductance department appears hole and multiple 4th inductance department appears hole, it is appear this first end face that this second inductance department appears hole, respectively the 3rd inductance department appears hole is appear respectively this second end face, and respectively the 4th inductance department appears hole is appear respectively the 3rd end face, form one the 3rd photoresist layer in this second dielectric layer, patterning the 3rd photoresist layer is to form one the 5th inductance department and arrange slotted eye and multiple 6th inductance department arranges slotted eye, it is appear this first end face and this second end face that 5th inductance department arranges slotted eye, and respectively the 6th inductance department arranges slotted eye is appear respectively this second end face and respectively the 3rd end face, and form one the 3rd metal level and in the 5th inductance department slotted eye is set and those the 6th inductance departments arrange slotted eye, to make the 3rd metal level, there is one the 5th inductance department and multiple 6th inductance department, 5th inductance department connects this second inductance department and the 3rd inductance department, respectively the 6th inductance department connects the 3rd inductance department and the 4th inductance department, 5th inductance department has one the 5th height, respectively the 6th inductance department has one the 6th height, and this second height, this third high degree and the 4th height are greater than the 5th height and the 6th height.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The aforesaid carrier manufacture method with three-dimensional inductance, it separately includes the second connection pad that is formed at this overcoat, and this substrate has one second weld pad in addition, and this second connection pad is electrically connected this second weld pad.
The aforesaid carrier manufacture method with three-dimensional inductance, the second wherein said metal level has one the 7th inductance department, and this second connection pad connects the 7th inductance department.
The aforesaid carrier manufacture method with three-dimensional inductance, the 3rd wherein said metal level has one the 8th inductance department, and the 8th inductance department connects the 7th inductance department and the 4th inductance department.
The aforesaid carrier manufacture method with three-dimensional inductance, it separately includes the second connection pad that is formed at this second dielectric layer, and the 3rd metal level has one the 8th inductance department, and the 8th inductance department connects this second connection pad and the 4th inductance department.
The aforesaid carrier manufacture method with three-dimensional inductance, it separately includes: the step removing the 3rd photoresist layer.
The aforesaid carrier manufacture method with three-dimensional inductance, it separately includes: form one the 3rd dielectric layer in the step of this second dielectric layer, and the 3rd dielectric layer covers the 3rd metal level.
The aforesaid carrier manufacture method with three-dimensional inductance, it separately includes: form a nickel gold overcoat in the step of the 3rd metal level.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of carrier structure with three-dimensional inductance that the present invention proposes, it at least comprises: a substrate, it has a surface, one first weld pad and an overcoat, this first weld pad is arranged at this surface, this overcoat is formed at this surface, and this overcoat has one first welding pad opening and this first welding pad opening appears this first weld pad, one the first metal layer, it is formed at this overcoat, and this first metal layer has one first connection pad and multiple first inductance department, and respectively this first inductance department has one first connection end point and one second connection end point, and this first inductance department has one first height, one first dielectric layer, it is formed at this overcoat and covers this first metal layer, this first dielectric layer has one first connection pad opening, multiple first connection end point opening and multiple second connection end point opening, this the first connection pad opening appears this first connection pad, respectively this first connection end point opening appears respectively this first connection end point, and respectively this second connection end point opening appears respectively this second connection end point, one second metal level, it is formed at this first dielectric layer, this second metal level has one second inductance department, multiple 3rd inductance department and multiple 4th inductance department, this second inductance department connects this first connection pad and this second inductance department has one first end face and one second height, respectively the 3rd inductance department connect respectively this first connection end point and respectively the 3rd inductance department there is one second end face and a third high degree, respectively the 4th inductance department connect respectively this second connection end point and respectively the 4th inductance department have one the 3rd end face and one the 4th height, this second height, this third high degree and the 4th height are greater than this first height, one second dielectric layer, it is formed at this first dielectric layer and covers this second metal level, this second dielectric layer has that one second inductance department appears hole, multiple 3rd inductance department appears hole and multiple 4th inductance department appears hole, it is appear this first end face that this second inductance department appears hole, respectively the 3rd inductance department appears hole is appear respectively this second end face, and respectively the 4th inductance department appears hole is appear respectively the 3rd end face, and one the 3rd metal level, it is formed at this second dielectric layer, 3rd metal level has one the 5th inductance department and multiple 6th inductance department, 5th inductance department connects this second inductance department and the 3rd inductance department, respectively the 6th inductance department connects the 3rd inductance department and the 4th inductance department, 5th inductance department has one the 5th height, and respectively the 6th inductance department has one the 6th height, and this second height, this third high degree and the 4th height are greater than the 5th height and the 6th height.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The aforesaid carrier structure with three-dimensional inductance, it separately includes the second connection pad that is formed at this overcoat, and this substrate has one second weld pad in addition, and this second connection pad is electrically connected this second weld pad.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, the present invention has the carrier manufacture method of three-dimensional inductance and structure at least has following advantages and beneficial effect: because inductance of the present invention is three-dimensional inductance, it has the effect reducing conplane wiring area, therefore the size of chip can reduce further, in addition, because three-dimensional inductance is the design of Different Plane, therefore the flow direction of inductance is also from vertically becoming level, contributes to covering the designs such as the electromagnetic coupled covering crystal module in brilliant technique.
In sum, the present invention is a kind of carrier manufacture method and structure thereof with three-dimensional inductance.The carrier manufacture method of the three-dimensional inductance of this tool comprises: provide a substrate; Form one first photoresist layer; Patterning first photoresist layer; Form a first metal layer and make the first metal layer have multiple first inductance department with the first height; Remove the first photoresist layer; Form one first dielectric layer; Form one second photoresist layer; Patterning second photoresist layer; Form one second metal level and make the second metal level have the second height the second inductance department, multiple there is third high degree the 3rd inductance department and multiple 4th inductance department with the 4th height; Remove the second photoresist layer; Form one second dielectric layer; Form one the 3rd photoresist layer; Patterning the 3rd photoresist layer also makes the 3rd metal level have the 5th inductance department of the 5th height and multiple 6th inductance department with the 6th height, and wherein the second height, third high degree and the 4th are highly greater than the first height, the 5th height and the 6th height.The present invention has significant progress technically, has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Figure 1A-Fig. 1 P is a kind of stereogram with the carrier manufacture method of three-dimensional inductance according to a preferred embodiment of the present invention.
Fig. 2 A-Fig. 2 P is the schematic cross-section according to this of a preferred embodiment of the present invention with the carrier manufacture method of three-dimensional inductance.
Fig. 3 is the schematic cross-section according to the another kind of another preferred embodiment of the present invention with the carrier structure of three-dimensional inductance.
Fig. 4 is the schematic cross-section according to another of another preferred embodiment of the present invention with the carrier structure of three-dimensional inductance.
Fig. 5 is the stereogram according to another of still another preferred embodiment of the present invention with the carrier structure of three-dimensional inductance.
100: the carrier structure 110 with three-dimensional inductance: substrate
111: surface 112: the first weld pads
113: overcoat 113a: the first welding pad opening
113b: the first connects inductance department setting area, setting area 113c: the first
114: the second weld pad 120: the first photoresist layers
121: the first opening 122: the first inductance department slotted eyes
130: the first metal layer 131: the first connection pad
132: the first inductance department 132a: the first connection end points
132b: the second connection end point 133: the first metal layer surface
140: the first dielectric layer 141: the first connection pad openings
142: the first connection end point opening 143: the second connection end point openings
144: the first dielectric layer surface 150: the second photoresist layers
151: the second inductance department providing holes 152: the three inductance department providing holes
153: the four inductance department providing holes 160: the second metal levels
161: the second inductance department 161a: the first end faces
162: the three inductance department 162a: the second end faces
163: the four inductance department 163a: the three end faces
164: the seven inductance department 170: the second dielectric layers
171: the second inductance departments appear hole 172: the three inductance department and appear hole
173: the four inductance departments appear hole 174: the second dielectric layer surface
180: the three photoresist layer 181: the five inductance departments arrange slotted eye
182: the six inductance departments arrange slotted eye 190: the three metal level
191: the five inductance department 192: the six inductance departments
193: the second layer on surface of metal 194: the eight inductance departments
D: the three dielectric layer D1: the five inductance department appears slotted eye
D2: the six inductance department appears slotted eye D3: the three dielectric layer surface
H1: the first height H 2: the second height
H3: third high degree H4: the four height
H5: the five height H 6: the six height
M: nickel gold protective layer P: the second connection pad
S: solder protection layer
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to the carrier manufacture method with three-dimensional inductance proposed according to the present invention and its embodiment of structure, method, step, structure, feature and effect thereof, be described in detail as follows.
Aforementioned and other technology contents, Characteristic for the present invention, can know and present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, should to the present invention for the technological means reaching predetermined object and take and effect obtain one more deeply and concrete understanding, but institute's accompanying drawings is only to provide with reference to the use with explanation, is not used for being limited the present invention.
Refer to shown in Figure 1A to Fig. 1 P and Fig. 2 A to Fig. 2 P, Figure 1A-Fig. 1 P is a kind of stereogram with the carrier manufacture method of three-dimensional inductance according to a preferred embodiment of the present invention.Fig. 2 A-Fig. 2 P is the schematic cross-section according to this of a preferred embodiment of the present invention with the carrier manufacture method of three-dimensional inductance.A kind of carrier manufacture method with three-dimensional inductance of a preferred embodiment of the present invention, it at least comprises the following step: first, refer to shown in Figure 1A and Fig. 2 A, one substrate 110 is provided, this substrate 110 has a surface 111, one first weld pad 112 and an overcoat 113, this first weld pad 112 is arranged at this surface 111, this overcoat 113 is formed at this surface 111, and this overcoat 113 has one first welding pad opening 113a, one first connects a setting area 113b and multiple first inductance department setting area 113c, this first welding pad opening 113a appears this first weld pad 112 and this first welding pad opening 113a is positioned at this first to connect a setting area 113b, the material of this substrate 110 can be selected from aluminum oxide substrate, aluminium nitride substrate, GaAs substrate or glass substrate one of them, this overcoat can be protective layer (passivation layer) or repeats protective layer (repassivation layer), then, refer to shown in Figure 1B and Fig. 2 B, form one first photoresist layer 120 in this overcoat 113, then, refer to shown in Fig. 1 C and Fig. 2 C, this first photoresist layer 120 of patterning is to form one first opening 121 and multiple first inductance department slotted eye 122, this first opening 121 appears this first to connect a setting area 113b, and those the first inductance department slotted eyes 122 appear those first inductance departments setting area 113c, afterwards, refer to shown in Fig. 1 D and Fig. 2 D, form a first metal layer 130 in this first opening 121 and those the first inductance department slotted eyes 122, to make this first metal layer 130, there is one first connection pad 131 and multiple first inductance department 132, respectively this first inductance department 132 has one first connection end point 132a and one second connection end point 132b, and this first inductance department 132 has one first height H 1, then, refer to shown in Fig. 1 E and Fig. 2 E, remove this first photoresist layer 120, afterwards, refer to shown in Fig. 1 F and Fig. 2 F, forming one first dielectric layer 140 in this overcoat 113 covers this first metal layer 130, this first dielectric layer 140 has one first connection pad opening 141, multiple first connection end point opening 142 and multiple second connection end point opening 143, this the first connection pad opening 141 appears this first connection pad 131, respectively this first connection end point opening 142 appears respectively this first connection end point 132a, respectively this second connection end point opening 143 appears respectively this second connection end point 132b, in addition, in the present embodiment, this first dielectric layer 140 has one first dielectric layer surface 144 in addition, this the first metal layer 130 has a first metal layer surface 133 in addition, this first dielectric layer surface 144 and this first metal layer surface 133 coplines, then, refer to shown in Fig. 1 G and Fig. 2 G, form one second photoresist layer 150 in this first dielectric layer 140, afterwards, refer to shown in Fig. 1 H and Fig. 2 H, this second photoresist layer 150 of patterning is to form one second inductance department providing holes 151, multiple 3rd inductance department providing holes 152 and multiple 4th inductance department providing holes 153, this the second inductance department providing holes 151 appears this first connection pad 131, respectively the 3rd inductance department providing holes 152 appears respectively this first connection end point 132a, and respectively the 4th inductance department providing holes 153 appears respectively this second connection end point 132b, then, refer to shown in Fig. 1 I and Fig. 2 I, form one second metal level 160 in this second inductance department providing holes 151, those the 3rd inductance department providing holes 152 and those the 4th inductance department providing holes 153, to make this second metal level 160, there is one second inductance department 161, multiple 3rd inductance department 162 and multiple 4th inductance department 163, this second inductance department 161 is this first connection pad 131 of connection and this second inductance department 161 has one first end face 161a and one second height H 2, respectively the 3rd inductance department 162 be connect respectively this second connection end point 132b and respectively the 3rd inductance department 162 there is an one second end face 162a and third high degree H 3, respectively the 4th inductance department 163 be connect respectively this first connection end point 132a and respectively the 4th inductance department 163 there is one the 3rd end face 163a and the 4th height H 4, this second height H 2, this third high degree H3 and the 4th height H 4 are greater than this first height H 1, afterwards, refer to shown in Fig. 1 J and Fig. 2 J, remove this second photoresist layer 150, then, refer to shown in Fig. 1 K and Fig. 2 K, forming one second dielectric layer 170 in this first dielectric layer 140 covers this second metal level 160, this second dielectric layer 170 has one second inductance department and appears hole 171, multiple 3rd inductance department appears hole 172 and multiple 4th inductance department appears hole 173, it is appear this first end face 161a that this second inductance department appears hole 171, respectively the 3rd inductance department appears hole 172 is appear respectively this second end face 162a, respectively the 4th inductance department appears hole 173 is appear respectively the 3rd end face 163a, in the present embodiment, this second dielectric layer 170 has one second dielectric layer surface 174 in addition, this first end face 161a, this second end face 162a, 3rd end face 163a and this second dielectric layer surface 174 copline, afterwards, refer to shown in Fig. 1 L and Fig. 2 L, form one the 3rd photoresist layer 180 in this second dielectric layer 170, then, refer to shown in Fig. 1 M and Fig. 2 M, patterning the 3rd photoresist layer 180 is to form one the 5th inductance department and arrange slotted eye 181 and multiple 6th inductance department arranges slotted eye 182, it is appear this first end face 161a and this second end face 162a that 5th inductance department arranges slotted eye 181, and respectively the 6th inductance department arranges slotted eye 182 is appear respectively this second end face 162a and respectively the 3rd end face 163a, afterwards, refer to shown in Fig. 1 N and Fig. 2 N, form one the 3rd metal level 190 and in the 5th inductance department slotted eye 181 is set and those the 6th inductance departments arrange slotted eye 182, to make the 3rd metal level 190, there is one the 5th inductance department 191 and multiple 6th inductance department 192, 5th inductance department 191 connects this second inductance department 161 and the 3rd inductance department 162, respectively the 6th inductance department 192 connects the 3rd inductance department 162 and the 4th inductance department 163, 5th inductance department 191 has one the 5th height H 5, respectively the 6th inductance department 192 has one the 6th height H 6, this second height H 2, this third high degree H3 and the 4th height H 4 are greater than the 5th height H 5 and the 6th height H 6, then, refer to shown in Figure 10 and Figure 20, remove the 3rd photoresist layer 180, finally, refer to shown in Fig. 1 P and Fig. 2 P, forming one the 3rd dielectric layer D in this second dielectric layer 170 covers the 3rd metal level 190, 3rd dielectric layer D has one the 5th inductance department and appears slotted eye D1 and multiple the 6th inductance departments appear slotted eye D2, 5th inductance department appears slotted eye D1 and appears the 5th inductance department 191, respectively the 6th inductance department appear slotted eye D2 be appear respectively the 6th inductance department 192 to form the carrier structure 100 that has three-dimensional inductance, in the present embodiment, 3rd dielectric layer D has one the 3rd dielectric layer surface D3 in addition, 3rd metal level 190 has one second layer on surface of metal 193 in addition, 3rd dielectric layer surface D3 and this second layer on surface of metal 193 copline, or, refer to shown in Fig. 3, Fig. 3 is the schematic cross-section according to the another kind of another preferred embodiment of the present invention with the carrier structure of three-dimensional inductance.In another embodiment; it can form a nickel gold protective layer M and form the 3rd dielectric layer D in the step of this second dielectric layer 170 in the 3rd metal level 190 to replace; preferably; refer to shown in Fig. 4, Fig. 4 is the schematic cross-section according to another of another preferred embodiment of the present invention with the carrier structure of three-dimensional inductance.In another embodiment, it more can form a solder protection layer S on this nickel gold protective layer M, the material of this solder protection layer can be solder or lead-free solder one of them.
In addition, shown in Fig. 1 P, this carrier structure 100 with three-dimensional inductance includes the second connection pad P that is formed at this overcoat 113 in addition, shown in Figure 1A, this substrate 110 has one second weld pad 114 in addition, this second connection pad P is electrically connected this second weld pad 114, and referring again to shown in Fig. 1 P, this second metal level 160 has one the 7th inductance department 164, 3rd metal level 190 has one the 8th inductance department 194, this second connection pad P connects the 7th inductance department 164, 8th inductance department 194 connects the 7th inductance department 164 and the 4th inductance department 163.Or refer to shown in Fig. 5, Fig. 5 is the stereogram according to another of still another preferred embodiment of the present invention with the carrier structure of three-dimensional inductance.In another embodiment, this second connection pad P is the 8th inductance department 194 being formed at this second dielectric layer the 170, three metal level 190 is connect this second connection pad P and the 4th inductance department 163.Inductance of the present invention is three-dimensional inductance, it has the effect reducing conplane wiring area, therefore the size of chip can reduce further, in addition, because three-dimensional inductance is the design of Different Plane, therefore the flow direction of inductance is also from vertically becoming level, contributes to covering the designs such as the electromagnetic coupled covering crystal module in brilliant technique.
This carrier structure 100 with three-dimensional inductance includes a substrate 110, one the first metal layer 130, one first dielectric layer 140, one second metal level 160, one second dielectric layer 170, one the 3rd metal level 190 and one second connection pad P, this substrate 110 has a surface 111, one first weld pad 112, one overcoat 113 and one second weld pad 114, this first weld pad 112 is arranged at this surface 111, this overcoat 113 is formed at this surface 111, this overcoat 113 has one first welding pad opening 113a and this first welding pad opening 113a appears this first weld pad 112, this the first metal layer 130 is formed at this overcoat 113, this the first metal layer 130 has one first connection pad 131 and multiple first inductance department 132, respectively this first inductance department 132 has one first connection end point 132a and one second connection end point 132b, and this first inductance department 132 has one first height H 1, this first dielectric layer 140 is formed at this overcoat 113 and covers this first metal layer 130, this first dielectric layer 140 has one first connection pad opening 141, multiple first connection end point opening 142 and multiple second connection end point opening 143, this the first connection pad opening 141 appears this first connection pad 131, respectively this first connection end point opening 142 appears respectively this first connection end point 132a, respectively this second connection end point opening 143 appears respectively this second connection end point 132b, this second metal level 160 is formed at this first dielectric layer 140, this second metal level 160 has one second inductance department 161, multiple 3rd inductance department 162 and multiple 4th inductance department 163, this second inductance department 161 connects this first connection pad 131 and this second inductance department 161 has one first end face 161a and one second height H 2, respectively the 3rd inductance department 162 connect respectively this first connection end point 132a and respectively the 3rd inductance department 162 there is an one second end face 162a and third high degree H3, respectively the 4th inductance department 163 connect respectively this second connection end point 132b and respectively the 4th inductance department 163 there is one the 3rd end face 163a and the 4th height H 4, this second height H 2, this third high degree H3 and the 4th height H 4 are greater than this first height H 1, this second dielectric layer 170 is formed at this first dielectric layer 140 and covers this second metal level 160, this second dielectric layer 170 has one second inductance department and appears hole 171, multiple 3rd inductance department appears hole 172 and multiple 4th inductance department appears hole 173, it is appear this first end face 161a that this second inductance department appears hole 171, respectively the 3rd inductance department appears hole 172 is appear respectively this second end face 162a, respectively the 4th inductance department appears hole 173 is appear respectively the 3rd end face 163a, 3rd metal level 190 is formed at this second dielectric layer 170, 3rd metal level 190 has one the 5th inductance department 191 and multiple 6th inductance department 192, 5th inductance department 191 connects this second inductance department 161 and the 3rd inductance department 162, respectively the 6th inductance department 192 connects the 3rd inductance department 162 and the 4th inductance department 163, 5th inductance department 191 has one the 5th height H 5, respectively the 6th inductance department 192 has one the 6th height H 6, this second height H 2, this third high degree H3 and the 4th height H 4 are greater than the 5th height H 5 and the 6th height H 6.In addition, shown in Fig. 1 P, this second connection pad P is electrically connected this second weld pad 114, this second metal level 160 has one the 7th inductance department 164,3rd metal level 190 has one the 8th inductance department 194, this second connection pad P is connection the 7th inductance department the 164, eight inductance department 194 is connect the 7th inductance department 164 and the 4th inductance department 163.Or refer to shown in Fig. 5, in another embodiment, this second connection pad P is the 8th inductance department 194 being formed at this second dielectric layer the 170, three metal level 190 is connect this second connection pad P and the 4th inductance department 163.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solution of the present invention content, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.

Claims (8)

1. there is a carrier manufacture method for three-dimensional inductance, it is characterized in that it comprises the following steps:
One substrate is provided, this substrate has a surface, one first weld pad and an overcoat, this first weld pad is arranged at this surface, this overcoat is formed at this surface, and this overcoat has one first welding pad opening, one first connects a setting area and multiple first inductance department setting area, this first welding pad opening appears this first weld pad and this first welding pad opening is positioned at this first to connect a setting area;
Form one first photoresist layer in this overcoat;
This first photoresist layer of patterning is to form one first opening and multiple first inductance department slotted eye, and this first opening appears this first to connect a setting area, and those the first inductance department slotted eyes appear those the first inductance department setting areas;
Form a first metal layer in this first opening and those the first inductance department slotted eyes, to make this first metal layer, there is one first connection pad and multiple first inductance department, respectively this first inductance department has one first connection end point and one second connection end point, and this first inductance department has one first height;
Remove this first photoresist layer;
Forming one first dielectric layer in this overcoat covers this first metal layer, this first dielectric layer has one first connection pad opening, multiple first connection end point opening and multiple second connection end point opening, this the first connection pad opening appears this first connection pad, respectively this first connection end point opening appears respectively this first connection end point, and respectively this second connection end point opening appears respectively this second connection end point;
Form one second photoresist layer in this first dielectric layer;
This second photoresist layer of patterning is to form one second inductance department providing holes, multiple 3rd inductance department providing holes and multiple 4th inductance department providing holes, this the second inductance department providing holes appears this first connection pad, respectively the 3rd inductance department providing holes appears respectively this first connection end point, and respectively the 4th inductance department providing holes appears respectively this second connection end point;
Form one second metal level in this second inductance department providing holes, those the 3rd inductance department providing holes and those the 4th inductance department providing holes, to make this second metal level, there is one second inductance department, multiple 3rd inductance department and multiple 4th inductance department, this second inductance department connects this first connection pad and this second inductance department has one first end face and one second height, respectively the 3rd inductance department connect respectively this second connection end point and respectively the 3rd inductance department there is one second end face and a third high degree, respectively the 4th inductance department connect respectively this first connection end point and respectively the 4th inductance department have one the 3rd end face and one the 4th height, this second height, this third high degree and the 4th height are greater than this first height,
Remove this second photoresist layer;
Forming one second dielectric layer in this first dielectric layer covers this second metal level, this second dielectric layer has that one second inductance department appears hole, multiple 3rd inductance department appears hole and multiple 4th inductance department appears hole, it is appear this first end face that this second inductance department appears hole, respectively the 3rd inductance department appears hole is appear respectively this second end face, and respectively the 4th inductance department appears hole is appear respectively the 3rd end face;
Form one the 3rd photoresist layer in this second dielectric layer;
Patterning the 3rd photoresist layer is to form one the 5th inductance department and arrange slotted eye and multiple 6th inductance department arranges slotted eye, it is appear this first end face and this second end face that 5th inductance department arranges slotted eye, and respectively the 6th inductance department arranges slotted eye is appear respectively this second end face and respectively the 3rd end face; And
Form one the 3rd metal level and in the 5th inductance department slotted eye is set and those the 6th inductance departments arrange slotted eye, to make the 3rd metal level, there is one the 5th inductance department and multiple 6th inductance department, 5th inductance department connects this second inductance department and the 3rd inductance department, respectively the 6th inductance department connects the 3rd inductance department and the 4th inductance department, 5th inductance department has one the 5th height, respectively the 6th inductance department has one the 6th height, and this second height, this third high degree and the 4th height are greater than the 5th height and the 6th height.
2. the carrier manufacture method with three-dimensional inductance according to claim 1, it is characterized in that it separately includes the second connection pad that is formed at this overcoat, this substrate has one second weld pad in addition, and this second connection pad is electrically connected this second weld pad.
3. the carrier manufacture method with three-dimensional inductance according to claim 2, is characterized in that the second wherein said metal level has one the 7th inductance department, and this second connection pad connects the 7th inductance department.
4. the carrier manufacture method with three-dimensional inductance according to claim 3, is characterized in that the 3rd wherein said metal level has one the 8th inductance department, and the 8th inductance department connects the 7th inductance department and the 4th inductance department.
5. the carrier manufacture method with three-dimensional inductance according to claim 1, it is characterized in that it separately includes the second connection pad that is formed at this second dielectric layer, 3rd metal level has one the 8th inductance department, and the 8th inductance department connects this second connection pad and the 4th inductance department.
6. the carrier manufacture method with three-dimensional inductance according to claim 1, is characterized in that it separately includes: the step removing the 3rd photoresist layer.
7. the carrier manufacture method with three-dimensional inductance according to claim 1, is characterized in that it separately includes: form one the 3rd dielectric layer in the step of this second dielectric layer, and the 3rd dielectric layer covers the 3rd metal level.
8. the carrier manufacture method with three-dimensional inductance according to claim 1, is characterized in that it separately includes: form a nickel gold overcoat in the step of the 3rd metal level.
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CN103325765A (en) * 2013-06-21 2013-09-25 江阴长电先进封装有限公司 Silicon substrate inductance structure with magnetic core
CN108879083B (en) * 2017-05-09 2020-05-26 昌泽科技有限公司 Method for manufacturing chip signal element
CN107403789B (en) * 2017-08-09 2020-10-16 上海华虹宏力半导体制造有限公司 Method for improving inductive performance of high-resistance substrate and semiconductor structure
CN115050539A (en) * 2022-06-07 2022-09-13 江南大学 IPD-based 3D inductor with ultrahigh self-resonant frequency and application thereof

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