CN102880441B - First in-first out device and realizing method thereof - Google Patents
First in-first out device and realizing method thereof Download PDFInfo
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- CN102880441B CN102880441B CN201110195140.5A CN201110195140A CN102880441B CN 102880441 B CN102880441 B CN 102880441B CN 201110195140 A CN201110195140 A CN 201110195140A CN 102880441 B CN102880441 B CN 102880441B
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Abstract
The invention discloses a first in-first out device and a realizing method of the first in-first out device. The first in-first out device comprises a plurality of input buffers, a first controller, a multiplexer, a second controller and an output buffer, wherein the plurality of input buffers belong to a power supply domain and is used for receiving input signals, and each input buffer has the first output data; the first controller belongs to the first power supply domain, is used for enabling the input buffers in a sequence, and also for generating a starting signal; the multiplexer is coupled with the input buffers, is used for receiving the first output data and outputting the output data in the sequence so as to generate the second output data; the second controller belongs to a second power supply domain, is used for receiving the starting signal through an asynchronous interface and generating a control signal according to the starting signal so as to control the multiplexer to output the second output data; the output buffer belongs to the second power supply domain and is used for receiving the second output data; the first power supply domain acts according to a first clock signal; the second power supply domain acts according to a second clock signal; and the second clock signal is not synchronous with the first clock signal.
Description
Technical field
The present invention relates to a kind of first-in first-out (First In First Out, FIFO) device, espespecially a kind of for the first-in first-out device across different electrical power territory.
Background technology
In digital circuit, usual use clock signal (Clock Signal, or be called for short clock) define time reference for data mobile in circuit, and be enable each assembly that in circuit, subject clock signal drives receive clock signal, usual meeting from this clock signal wherein or its source produce Clock Tree (Clock Tree) for integrated circuit (Integrated Circuit, hereinafter referred to as IC) intraware use, but a delay (delay) can be had between the clock signal before Clock Tree produces and after producing, thus hold time (the Hold Time) of data is caused must to do corresponding adjustment.
Along with the lifting of environmental consciousness, if when IC is under power supply shutdown (Power Down) or power supply saving (Power Saving) state, it is also more and more harsh to the low wasted work demand of IC, and current technology is that IC cutting is divided into different power domain (Power Domain).As shown in Figure 1A, IC is divided into three different power domain PD1 ~ PD3, power domain PD1 ~ PD3 has the supply power supply P1 ~ P3 of its correspondence separately.Under power supply shutdown (Power Down) or power supply save (PowerSaving) state, perform the power domain needed for enable action and corresponding power supply after only retaining, the demand of minimum wasted work can be reached.
Please refer to Figure 1B, Figure 1B shows the partial circuit in different electrical power territory.As shown in Figure 1B, in figure, 10 and 11 represent a virtual impact damper (buffer) or delay cell, be used for representing the delay produced between the Clock Tree of origin source clock generating and source clock, it is noted that, impact damper in figure or delay cell 10 and 11 are only that the delay of Clock Tree is illustrated, the impact damper of non-real or delay cell, and the impact damper of actual Clock Tree does not mark.
Source terminal (power domain PD1) is in fig. ib provided with input buffer 13, it receives input signal In and the first clock signal TC1 that clock SC delayed unit 10 in origin source produces drives, the data of input signal In are sent to the output state 15 of rear end by input buffer 13, and export an output signal Out.Wherein, the circuit of the first clock signal TC1 that delay cell 10 and 11 exports and second clock signal TC2, can utilize Clock Tree to synthesize (clock tree synthesis) and produce.The first desirable clock signal TC1 and second clock signal TC2 can equal in fact (close to aliging), as shown in sequential below Figure 1B.
But even if the voltage that different independent current source territory was originally planned is identical, in fact because the difference of the wasted work of different power domain, the voltage of power domain also can produce different pressure drop, and enable clock tree produces different changes time delay.As shown in Figure 1 C, for meeting with a schematic diagram of the problems referred to above, due in different power domain, still there is the transmission of data, if synchronous data transmission, due to the difference of the wasted work of different power domain, the time delay of meeting enable clock tree produces and changes.Can be understood by the sequential below Fig. 1 C, because the supply voltage of power domain PD1 is higher than power domain PD2, make the first clock signal TC1 comparatively second clock signal TC2 fast (shown in dotted line), then can produce the situation of fault of holding time (Hold Time Violation).
On the contrary, please refer to Fig. 1 D, can be understood by the sequential below Fig. 1 D, when the supply voltage of power domain PD2 is higher than power domain PD1, second clock signal TC2 comparatively soon (shown in dotted line), also can produce the situation generation of setting-up time fault (Set Up Time Violation) by the first clock signal TC1.
Summary of the invention
An object of the present invention is to provide a kind of first-in first-out (First In First Out, FIFO) apparatus and method, when solving across different electrical power territory, setting-up time fault (Set Up Time Violation) produced because of voltage difference or the situation of fault of holding time (Hold Time Violation).
One embodiment of the invention provide a kind of across the first-in first-out device of one first power domain (Power Domain) with a second source territory, wherein, first-in first-out device receives an input signal, and first-in first-out device comprises multiple input buffer, one first controller, a multiplexer, a second controller and an output state.Multiple input buffer, belongs to the first power domain, and in order to receive this input signal, and each input buffer has one first output data separately; First controller belongs to this first power domain, in order to foundation one order with enable input buffer, and produces a start signal; Multiplexer couples input buffer, receives first and exports data and export data according to this Sequential output first, exports data to produce one second; Second controller belongs to second source territory, and it receives start signal by an asynchronous interface, and produces a control signal to control multiplexer output second output data according to start signal; Output state belongs to second source territory, in order to receive the second output data.Wherein, the first power domain operates according to one first clock signal, and second source territory operates according to a second clock signal, and second clock signal is asynchronous with the first clock signal.
One embodiment of the invention provide a kind of implementation method of the first-in first-out device across one first power domain and a second source territory, comprise following steps: receive an input signal by multiple input buffer, wherein input buffer has one first output data separately; By one first controller, according to an order with enable input buffer, and produce a start signal; By a multiplexer, receive first and export data, and export data according to Sequential output first, export data to produce one second; By a second controller, receive start signal by an asynchronous interface, and produce a control signal to control multiplexer output second output data according to start signal; And by an output state, receive second and export data.
Wherein, multiple input buffer and this first controller belong to the first power domain; Multiplexer, second controller, asynchronous interface and output state belong to second source territory; And first power domain operate according to one first clock signal, second source territory operates according to a second clock signal, and second clock signal is asynchronous with the first clock signal.
Accompanying drawing explanation
Figure 1A shows the schematic diagram that IC is divided into different power domain.
Figure 1B is the schematic diagram of prior art in perfect condition.
Fig. 1 C is that the supply voltage of the power domain PD1 of prior art is higher than schematic diagram during power domain PD2.
Fig. 1 D is that the supply voltage of the power domain PD2 of prior art is higher than schematic diagram during power domain PD1.
Fig. 2 A is the schematic diagram of first-in first-out device one embodiment of the present invention.
Fig. 2 B is the schematic diagram of the asynchronous interface of one embodiment of the invention.
Fig. 2 C shows the sequential chart (supply voltage of power domain PD1 is higher than the supply voltage of power domain PD2) that FIFO device one of the present invention is implemented.
Fig. 2 D shows the sequential chart (supply voltage of power domain PD2 is higher than the supply voltage of power domain PD1) that FIFO device one of the present invention is implemented.
Fig. 3 is the schematic diagram of first-in first-out device one embodiment of the present invention.
Fig. 4 shows the process flow diagram of FIFO device one embodiment of the present invention.
Primary clustering symbol description
200,300 first-in first-out device 13,201 ~ 203 input buffers
204,206 controller 205 multiplexers
15,207 output state 208a, 208b, 10,11 delay cells
209 asynchronous interface PD1 ~ PD3 power domain
P1 ~ P3 supply voltage S301 ~ S305 step
Embodiment
Refer to Fig. 2 A, Fig. 2 A is the schematic diagram of first-in first-out of the present invention (First In First Out, hereinafter referred to as FIFO) device 200 1 embodiment.Wherein, FIFO device 200 includes power domain PD1 and PD2, and power domain PD1 and PD2, and because of the supply voltage of planning originally, just supply voltage that is not identical or planning originally is identical but make them different because of different pressure drops, and makes its supply voltage not identical.
In the present embodiment, FIFO device 200 comprises input buffer 201 ~ 203, first controller 204, multiplexer 205, second controller 206, output state 207, delay cell 208a ~ 208b and asynchronous interface 209.In one embodiment, the first controller 204 is located at power domain PD1 with input buffer 201 ~ 203; And multiplexer 205, second controller 206, output state 207, delay cell 208b and asynchronous interface 209 are located at power domain PD2.
Note that delay cell 208a at this, 208b represents that source clock signal SC is because the voltage of two power domain is different or the different delay produced of load (line length etc.).Therefore, between source clock signal SC and the clock signal of Clock Tree and clock signal between different electrical power territory asynchronous and there is a phase differential (such as: the clock signal of originate clock signal SC and Clock Tree can be identical clock but has a phase differential, therefore can be considered asynchronous).And due to the power consumption difference of power domain PD1 and PD2 or the supply voltage of originally planning just not identical, make the delay of Clock Tree produce change along with the supply voltage difference of power domain PD1 and PD2.Therefore, power domain PD1 is according to the first clock signal PS1 running, and power domain PD2 is according to second clock PS2 running.Wherein, the Clock Tree that produces for the clock signal SC that originates of the first clock signal PS1 and second clock signal PS2.
Note that input buffer 201 ~ 203 and the first controller 204 are driven by the first clock signal PS1, second controller 206 and output state 207 are driven by second clock signal PS2.
Input buffer 201 ~ 203 is in order to receive an input signal IS, wherein, input signal IS can be a single position (Bit) or comprises long numeric data, and the present invention is not as limit, and input buffer 201 ~ 203 produces first output data OS1 ~ OS3 respectively.Input buffer 201 ~ 203 is coupled to the input end of multiplexer 205 respectively.
First controller 204 is coupled to input buffer 201 ~ 203 respectively, and drives input buffer 201 ~ 203 according to a preset order, and the data of input signal are write in input buffer 201 ~ 203 in order.
When the first controller 204 produces a start signal ES, and when being sent to second controller 206, represent that the first controller 204 starts action.Because the first controller 204 belongs to power domain PD1, and second controller 206 belongs to power domain PD2, therefore receives start signal ES by second controller 206 by asynchronous interface 209.
Second controller 206 produces a control signal CS according to start signal ES, produces first output data OS1 ~ OS3 to control multiplexer 205.After second controller 206 receives start signal ES, drive multiplexer 205 to export these first output data OS1 ~ OS3 in order by control signal.Output state 207 receives first output data OS1 ~ OS3 and exports data OS4 to produce one second.
In one embodiment of the invention, input buffer 201 ~ 203 and output state 207 are D flip-flop (D Flip-Flop).In addition, in the first controller 204, comprise one first counter 204a, in second controller 206, comprise one second counter 206a.First counter 204a and the second counter 206a basis source clock signal SC counts, and the second counter 206a is after second controller 206 receives start signal ES, from an initial value (such as: count zero).First controller 204 and second controller 206 are respectively according to the value that the first counter 204a and the second counter 206a counts, and control inputs buffer 201 ~ 203 reads the order of input signal IS.
Fig. 2 B is the schematic diagram of the asynchronous interface of display one embodiment of the invention.Asynchronous interface 209 can be realized by a two-stage triggering device in one example.
Please also refer to Fig. 2 C, Fig. 2 D, Fig. 2 C shows the sequential chart (supposing the supply voltage of supply voltage higher than power domain PD2 of power domain PD1) that FIFO device one of the present invention is implemented, and Fig. 2 D shows the sequential chart (supposing the supply voltage of supply voltage higher than power domain PD1 of power domain PD2) that FIFO device one of the present invention is implemented.
As shown in Figure 2 C, in the present embodiment, three groups of input buffers 201 ~ 203 in FIFO device 200, by the control of the first controller 204, are sequentially stored in buffer 201 ~ 203 by input signal IS.Such as: as T=0, the count value of the first counter is 0, and now, the first controller controls buffer 201 and reads input signal IS (D00).As T=1, the count value of the first counter is that the 1, first controller control buffer 202 reads input signal IS (D01), and buffer 201 exports data OS1 (D00).As T=2, the count value of the first counter is 2, first controller controls buffer 203 and reads input signal IS (D02), and buffer 201 exports data OS1 (D00) and buffer 202 exports data OS2 (D01).Then, as T=3, the count value of the first counter gets back to 0, now, first controller controls buffer 201 and reads input signal IS (D10), and buffer 201 exports data OS1 (D00), buffer 202 exports data OS2 (D01) and buffer 203 exports data OS3 (D02), by that analogy.Therefore, three groups of input buffers 201 ~ 203 sequentially read input signal IS respectively, and sequentially output signal output.Because FIFO device 200 has three groups of input buffers 201 ~ 203, therefore the output often organizing input buffer can maintain three cycles.
For enabling input signal IS successfully be sent to power domain PD2 by power domain PD1, one embodiment of the invention control the output of multiplexer 205 by asynchronous interface 209 and the first controller 206.Detailed principle of operation is as described below.
In Fig. 2 C, the supply voltage of power domain PD1 is higher than the supply voltage of power domain PD2, and therefore, the first clock signal PS1 can advanced second clock signal PS2.In addition, according to an embodiment, asynchronous interface 209 is made up of two-stage D flip-flop.Asynchronous interface 209 can sample the start signal ES that the first controller 204 exports according to second clock signal PS2 and export second controller 206 to.Such as: in Fig. 2 C during T=0, after asynchronous interface 209 is sampled to the start signal ES of the first controller 204 output by second clock signal PS2, second controller 206 is passed to when T=1, the second counter 206a in second controller 206 is made to start by 0 counting, the same time, second controller 206 also controls multiplexer 205 and exports its output data OS1 (D00).Then, when T=2, output state 207 exports it again and exports data OS4 (D00).Thus, when supply voltage higher than power domain PD2 of the supply voltage of power domain PD1, the input signal IS (D00) entering FIFO device 200 when T=0 can be exported by power domain PD2 when T=2.In other words, the second counter 206 in FIFO device 200 trigger by start signal ES after, start to carry out counting (0 ~ 2) according to second clock signal PS2, make second controller 206 control the output data D00 ~ Dnm of multiplexer 205 sequentially (0 ~ 2) output state 201 ~ 203.Finally, then by output state 207 export.Therefore, framework of the present invention, can solve the problem because of hold time between the first clock signal PS1 of power domain PD1 and the second clock signal PS2 of power domain PD2 (hold time).It is noted that in this embodiment when first-in first-out device 200 has three input buffer 201 ~ 203, the second output data OS4 that output state 207 produces falls behind the clock period of input signal IS at least two the first clock signal PS1.And in another embodiment, first-in first-out device 200 also can have the input buffer of more than three, but input buffer is more, and the second time exporting the backward input signal IS of data OS4 also can be longer.
The difference of Fig. 2 D and Fig. 2 C is the supply voltage of supply voltage lower than power domain PD2 of power domain PD1, therefore the advanced first clock signal PS1 of second clock signal PS2.Because asynchronous interface 209 samples the time relationship of start signal ES, in fact the second counter 206a can fall behind two cycles of the first counter 204a.Therefore the input signal IS (D00) entering FIFO device 200 when T=0 can be exported by power domain PD2 when T=3.And under this design, can find out that output state 207 still correctly can access the data of existence three grades of input buffers 201 ~ 203 by sequential chart.Therefore, the problem because of setting-up time (setup time) between the first clock signal PS1 of power domain PD1 and the second clock signal PS2 of power domain PD2 can be solved.It is noted that in this embodiment when first-in first-out device 200 has three input buffer 201 ~ 203, the second output data OS4 that output state 207 produces falls behind the clock period of input signal IS at least three the first clock signal PS1.And in another embodiment, first-in first-out device 200 also can have the input buffer of more than three, but input buffer is more, and the second time exporting the backward input signal IS of data OS4 also can be longer.
Please refer to Fig. 3, Fig. 3 shows the schematic diagram of a kind of first-in first-out device across one first power domain and a second source territory of one embodiment of the invention.First-in first-out device 300 is with the difference of first-in first-out device 200, its source clock signal SC also can belong to another power domain PD3, the now clock that produces according to the clock signal SC that originates of the first clock signal PS1 and second clock signal PS2, but three is respectively by different power drives, all the other principle of operation as hereinbefore, do not repeat separately at this.Please refer to Fig. 4, Fig. 4 shows the one of one embodiment of the invention across the implementation method of one first power domain (PowerDomain) with the first-in first-out device in a second source territory, comprises following steps
Step S401: receive an input signal by multiple input buffer, wherein, these input buffers have one first separately and export data;
Step S402: by one first controller, according to an order with these input buffers enable, and produces a start signal;
Step S403: by a second controller, receives start signal by an asynchronous interface, and produces a control signal to control multiplexer output second output data according to this start signal;
Step S404: by a multiplexer, receives these the first output data, and exports data according to this Sequential output first, to produce the second output data; And
Step S405: by an output state, receives this second output data;
Wherein, multiple input buffer and the first controller belong to the first power domain; Multiplexer, second controller, asynchronous interface and output state belong to second source territory; And the first power domain operates according to one first clock signal, second source territory operates according to a second clock signal, and second clock signal and this first clock signal can be asynchronous or out of phase.In one embodiment, second clock signal PS2 and the first clock PS1 signal are respectively the clock signal produced according to the clock signal SC that originates.
In sum, the present invention passes through multiple buffer across first-in first-out (FIFO) device of two power domain, in the first power domain, first input signal carrying out sequentially is kept in, the storage cycle of every input signal is increased, therefore, the well-to-do time can be had data to be read by buffer at the circuit of the second electrical domain.Therefore solve across different electrical power territory, because the setting-up time that produces of voltage difference breaks rules (Set Up Time Violation) and the situation of (Hold Time Violation) of breaking rules of holding time.
Claims (12)
1., across first-in first-out (First In First Out, the FIFO) device of one first power domain (Power Domain) with a second source territory, it comprises:
Multiple input buffer, belongs to described first power domain, and in order to receive an input signal, and each input buffer exports one first output data separately;
One first controller, it belongs to described first power domain, in order to foundation one order with enable described multiple input buffer, and produces a start signal;
One multiplexer, belongs to described second source territory, exports data in order to receive described multiple first and according to the first output data described in described Sequential output, exports data to produce one second;
One second controller, belong to described second source territory, it receives described start signal by an asynchronous interface, and produces a control signal to control the described second output data of described multiplexer output according to described start signal; And
One output state, belongs to described second source territory, exports data in order to receive described second;
Wherein, described first power domain operates according to one first clock signal, and described second source territory operates according to a second clock signal, and described second clock signal is asynchronous with described first clock signal.
2. first-in first-out device according to claim 1, wherein, described multiple input buffer comprises at least three input buffers.
3. first-in first-out device according to claim 1, wherein, when described multiple input buffer comprises three input buffers, and during the supply voltage of the supply voltage of described first power domain higher than described second source territory, described second exports the clock period that data fall behind described first clock signal of described input signal at least two.
4. first-in first-out device according to claim 1, wherein, when described multiple input buffer comprises three input buffers, and during the supply voltage of the supply voltage of described first power domain lower than described second source territory, described second exports the clock period that data fall behind described first clock signal of described input signal at least three.
5. first-in first-out device according to claim 1, wherein, each input buffer in described output state and described multiple input buffer is a D flip-flop (DFlip-Flop).
6. first-in first-out device according to claim 1, wherein, described first controller comprises one first counter, and described first counter is triggered by described first clock signal and counts according to described order, makes described first controller according to the enable described multiple input buffer of described order.
7. first-in first-out device according to claim 1, wherein, described second controller comprises one second counter, described second counter is triggered by described second clock signal, and start to count according to described order according to described start signal, make described second controller control described multiplexer, make described multiplexer according to the first output data multiple described in described Sequential output.
8. first-in first-out device according to claim 1, wherein, described asynchronous interface comprises a secondary D flip-flop, and described asynchronous interface belongs to described second source territory and receives described start signal, and has an output terminal described start signal is sent to described second controller.
9., across the implementation method of one first power domain (Power Domain) with the first-in first-out device in a second source territory, comprise following steps:
Receive an input signal by multiple input buffer, wherein, described multiple input buffer has one first separately and exports data;
By one first controller, according to an order with enable described multiple input buffer, and produce a start signal;
By a multiplexer, receive described multiple first and export data, and according to the first output data described in described Sequential output, export data to produce one second;
By a second controller, receive described start signal by an asynchronous interface, and produce a control signal to control the described second output data of described multiplexer output according to described start signal; And
By an output state, receive described second and export data;
Wherein, described multiple input buffer and described first controller belong to described first power domain; Described multiplexer, described second controller, described asynchronous interface and described output state belong to described second source territory; And described first power domain operates according to one first clock signal, described second source territory operates according to a second clock signal, and the supply voltage of described first power domain is different from the supply voltage in a described second source territory.
10. method according to claim 9, wherein, receives described input signal by least three input buffers.
11. methods according to claim 9, also comprise following steps:
Counted by one first counter, and described first counter trigger according to described first clock signal and counts according to described order, making described first controller according to the enable described multiple write buffer of described order.
12. methods according to claim 9, also comprise following steps:
Counted by one second counter, and described second counter triggers according to described second clock signal and starts to count according to described order according to described start signal, make described second controller control described multiplexer, make described multiplexer according to the first output data multiple described in described Sequential output.
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| CN103490757B (en) * | 2013-08-28 | 2018-10-30 | 华为技术有限公司 | A kind of signal output method and device based on I/O interfaces |
| US10928850B2 (en) * | 2019-04-25 | 2021-02-23 | Realtek Semiconductor Corporation | First in and first out apparatus and driving method thereof |
| CN111399802B (en) * | 2020-03-24 | 2022-08-19 | 飞腾信息技术有限公司 | Multi-power-domain multi-clock-domain first-in first-out queue, integrated circuit chip and computer equipment |
| CN114077415A (en) * | 2020-08-12 | 2022-02-22 | 长鑫存储技术(上海)有限公司 | First-in first-out memory and storage device |
| EP4033347B1 (en) | 2020-08-12 | 2023-07-05 | Changxin Memory Technologies, Inc. | First in first out memory and storage device |
| CN113093899B (en) * | 2021-04-09 | 2022-03-22 | 思澈科技(上海)有限公司 | Cross-power domain data transmission method |
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| US7065001B2 (en) * | 2004-08-04 | 2006-06-20 | Micron Technology, Inc. | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM |
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| EP1442550B1 (en) * | 2001-10-31 | 2006-12-13 | Koninklijke Philips Electronics N.V. | Clock domain crossing fifo |
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