CN102938383A - 标准芯片尺寸封装 - Google Patents

标准芯片尺寸封装 Download PDF

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Publication number
CN102938383A
CN102938383A CN2012104149764A CN201210414976A CN102938383A CN 102938383 A CN102938383 A CN 102938383A CN 2012104149764 A CN2012104149764 A CN 2012104149764A CN 201210414976 A CN201210414976 A CN 201210414976A CN 102938383 A CN102938383 A CN 102938383A
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chip
circuit board
contact
printed circuit
pcb
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CN2012104149764A
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CN102938383B (zh
Inventor
冯涛
安荷·叭剌
何約瑟
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Alpha and Omega Semiconductor Inc
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Alpha and Omega Semiconductor Inc
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Publication of CN102938383A publication Critical patent/CN102938383A/zh
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Abstract

本发明公开了一种标准芯片尺寸封装。所述标准芯片尺寸封装提供了与芯片两侧上的凸点装置触点的电连接。所述封装在一个标准构型上连接在一个印刷电路板上。本发明同时公开了制造所述标准芯片封装的方法。

Description

标准芯片尺寸封装
技术领域
本发明一般涉及半导体封装，特别是一种标准芯片尺寸封装。
背景技术
电子设备的小型化引导了更小型的半导体装置的设计和制造。半导体装置一般被封装用于电连接印刷电路板的布线。芯片尺寸封装提供了半导体装置尺寸上的封装，从而最小化封装所消耗的电路板空间。
如MOSFETs(metallic oxide semiconductor field effecttransistor金属氧化物半导体场效应晶体管 )的这类垂直传导功率半导体装置具有在装置的第一表面上形成的两个电极或接头以及在装置的第二表面上形成的一第三个电极或接头。为了把电极焊接到印刷电路板上，一些传统的芯片尺寸封装所用的方法是把所有的电极布置在装置的同一侧。例如，美国第6,646,329号专利公开了一个封装，包括导线架及其上结合的晶片。该晶片被连接到所述导线架上，其背面（漏极接点）与从导线架上延伸出的源极引脚和栅极引脚共面。所公开的这个结构非常复杂。
另一个优先技术的芯片尺寸封装包括一个晶片，其漏极侧安装在一个金属夹下，或者其源极和栅极电极被设置与该金属夹的延伸区域的边缘表面共平面，或者其如美国第6,624,522.号专利所公开。所公开的封装使得在其被镶嵌到电路板上后，很难视觉检测焊点。
 美国第6,653,740号专利所公开的倒装式芯片MOSFET结构具有一个垂直传导半导体晶片，通过一个扩散器或传导电极，该晶片的漏极层连接该晶片顶部的漏极电极。所公开的上述结构存在电阻增加以及活跃区域减少的问题。
同样已知，可以通过传导阻滞和传导层来使得装置电极与印刷电路板相连接。像这样的一个结构在美国第6,392,305号专利中被公开，其中电极的芯片连接传导阻滞焊接，后者进一步通过其侧表面与印刷电路板相连接。美国第6,841,416号专利公开了一个芯片尺寸封装，其具有上下两个传导层与芯片终端相连接。在上下传导层同一侧的表面上形成的电极表面与印刷电路板相应链接焊点相连接。在这些案例中，对于低成本生产结构或制造过程都过于复杂。
这就需要一种芯片尺寸封装技术，其可以提供在芯片双面都可装置接触的电连接、能看见清楚的焊点、减小的印刷电路板安装面积。并且该芯片尺寸封装的制造方法允许适量的批量生产。该芯片尺寸封装只需要简单的生产步骤并具有较低的生产成本。
发明内容
本发明公开的一种标准芯片尺寸封装克服了先前技术的不足，为了实现本发明的目的，其具有一个能够在标准构型下与印刷电路板适配连接的芯片尺寸封装，例如芯片的上下表面的平面直立于印刷电路板所在平面。凸起的芯片通过其两侧的电引脚连接到印刷电路板上。
本发明的一方面是公开一种标准芯片尺寸封装，其具有两侧都设有引脚的晶片，所述每一引脚都包含电连接其上的焊接球，从而形成一个突起的芯片。
本发明的另一方面是公开一种标准芯片尺寸封装，其具有两侧都设有引脚的晶片，晶片第一侧面上的每一引脚包含电连接其上的焊接球从而形成一个凸点芯片，晶片第二侧面由一个焊接层组成，其电连接第二侧面和一个印刷电路板上形成的传道杆。
本发明的另一方面，一个标准芯片尺寸封装包括一个第一芯片和一个第二芯片，二者相连形成共漏极配置，第一和第二芯片都具有形成在非漏极侧的栅极触点、源极触点，每一栅极触点和每一源极触点都包括一个与其电连接的焊接球，从而形成一个凸点共漏极芯片。
本发明的另一方面，一个标准芯片尺寸封装包括串联相连的第一、第二、第三芯片，上述芯片中的每一个都具有栅极触点、源极触点和漏极接触点，每一栅极触点、每一源极触点和每一漏极接触点都包括一个与其电连接的焊接球，从而形成一个凸点串联芯片。
本发明的另一方面，一个标准芯片尺寸封装包括一个触点形成在其两侧的芯片，形成在芯片的第一侧的每一触点都包括一个与其电连接的焊接球，从而形成一个凸点芯片
本发明的另一方面，制造一个标准芯片尺寸封装的过程包括以下步骤：
提供一个前侧具有铝衬垫而后侧具有背侧金属的晶圆；
在所述晶圆后侧形成钝化层；
在晶圆后侧打开窗口；
在铝衬垫和打开的窗口上化学镀镍/金镀层（Ni/Au），以形成下部凸点金属镀层；
在下部凸点金属镀层上设置焊接球；
切割晶圆形成一组凸点芯片。
在本发明的另一方面，制造一个共漏极标准芯片尺寸封装的过程包括以下步骤：
提供前侧具有铝衬垫而后侧具有背侧金属的两个晶圆；
化学镀每一晶圆的前侧并保护每一晶圆的后侧，从而形成下部凸点金属镀层；
测定两个晶圆的晶片布局是否相互匹配；
如相互匹配，则焊接晶圆后侧；
否则当第二晶圆比第一晶圆小时，切割第二晶圆；
将从第二晶圆上切割的晶片附在第一晶圆的后侧；
在下部凸点金属镀层上设置焊接球；
切割晶圆形成一组共漏极凸点芯片。
本发明的另一方面，制造一个表面安装标准芯片尺寸封装的过程包括以下步骤：
提供一个假片基底，其具有一组晶片区域；
蚀刻穿透位于每一晶片区域的角的孔洞；
采用铜表面电镀假片基底；
凹槽化每一晶片区域的顶部表面，以形成一个凹槽和一组触点；
凹槽化每一晶片区域的底部表面，以形成一组触点；
底部表面的该组触点中的每一个电连接相对应的顶部表面的那组触点中的一个；
在每一个晶片区域的顶部表面上安装一组凸点芯片；
成型封装该组凸点芯片；
切割假片基底，形成表面安装标准芯片封装。
以上是本发明的大纲，更重要的一些技术特征将在后面的具体实施例中采用细节加以描述，以有助于本发明的技术可以被更好的理解。本发明的其他附加技术特征会被在后面的具体实施例中加以详述，并且其构成本发明的附加权利要求。
在解释本发明的实施例之前，必须清楚的是参考以下附图及实施例来详述的本发明的具体应用并不对本发明构成限制，其仅仅是用于描绘。
因此，本领域的技术人员基于本发明所公开之内容可以设计处其他方法和系统来实现本发明的若干目的，然而根据本发明的权利要求，这些装置、结构并未脱离本发明的精神范围。
附图说明
通过以下的实施例和相应的附图对本发明的目的以及技术特征进一步描述：
图1A是沿图1E的A-A线的标准芯片尺寸封装的横截面结构示意图，其描述了本发明第一实施例中的与凹槽印刷电路板相连的封装结构。
图1B是本发明第一实施例的晶片的前表面的俯视结构示意图。
图1C是本发明第一实施例的晶片的后表面的俯视结构示意图。
图1D是本发明第一实施例的凹槽印刷电路板的俯视结构示意图。
图1E是本发明第一实施例的与凹槽印刷电路板相连的标准芯片尺寸封装的俯视结构示意图。
图2A是沿图2E的A-A线的标准芯片尺寸封装的横截面结构示意图，其描述了本发明第二实施例中的与凹槽印刷电路板相连的封装结构。
图2B是本发明第二实施例的晶片的前表面的俯视结构示意图。
图2C是本发明第二实施例的晶片的后表面的俯视结构示意图。
图2D是本发明第二实施例的凹槽印刷电路板的俯视结构示意图。
图2E是本发明第二实施例的与凹槽印刷电路板相连的标准芯片尺寸封装的俯视结构示意图。
图3A是沿图3E的A-A线的标准芯片尺寸封装的横截面结构示意图，其描述了本发明第三实施例中的与非凹槽印刷电路板相连的封装结构。
图3B是本发明第三实施例的晶片的前表面的俯视结构示意图。
图3C是本发明第三实施例的晶片的后表面的俯视结构示意图。
图3D是本发明第三实施例的非凹槽印刷电路板的俯视结构示意图。
图3E是本发明第三实施例的与非凹槽印刷电路板相连的标准芯片尺寸封装的俯视结构示意图。
图4A是沿图4E的A-A线的标准芯片尺寸封装的横截面结构示意图，其描述了本发明第四实施例中的与印刷电路板相连的封装结构。
图4B是本发明第四实施例的晶片的前表面的俯视结构示意图。
图4C是本发明第四实施例的晶片的后表面的俯视结构示意图。
图4D是本发明第四实施例的印刷电路板的俯视结构示意图。
图4E是本发明第四实施例的与印刷电路板相连的标准芯片尺寸封装的俯视结构示意图。
图5A是沿图5E的A-A线的双芯片共漏极标准芯片尺寸封装的横截面结构示意图，其描述了本发明第五实施例中的与印刷电路板相连的封装结构。
图5B是本发明第五实施例的第一晶片的前表面的俯视结构示意图。
图5C是本发明第五实施例的第二晶片的前表面的俯视结构示意图。
图5D是本发明第五实施例的印刷电路板的俯视结构示意图。
图5E是本发明第五实施例的与印刷电路板相连的双芯片共漏极标准芯片尺寸封装的俯视结构示意图。
图6是本发明第六实施例的与印刷电路板相连的标准芯片尺寸封装的俯视结构示意图。
图7是标准芯片尺寸封装的横截面结构示意图，其描述了本发明第七实施例中的与印刷电路板相连的封装结构。
图8A-8F描述了制造本发明的表面安装式封装的方法。
图9是本发明的标准芯片尺寸封装的制备过程的流程图。
图10是本发明的双芯片共漏极标准芯片尺寸封装的制备过程的流程图。
图11是本发明的引线架封装的横截面示意图。
具体实施方式
 
本发明以下将会参考附图并以实施例的方式进一步阐述本发明。然而，所采用的附图及实施例并不用于限制本发明的范围。附图中省略了本发明所采用的为本领域技术人员所熟知的元件，仅绘出为阐述本发明所必须的元件。此外，本发明包括图中示出和未示出的元件。
本发明公开了一种标准芯片尺寸封装，其向芯片两侧上突起的装置连接点提供电连接。所述封装以固定的配置电连接刷电路板。
图1A描述了本发明第一实施例的标准芯片尺寸封装100，其电连接凹槽印刷电路板150（printed circuit board，PCB）。图1E描述了安装在凹槽PCB150上的标准芯片尺寸封装的俯视图，图1A描述了沿图1E的A-A线的横截面视图。所述标准芯片尺寸封装100包含一个芯片105，该芯片105包括一个功率垂直传导半导体装置，如MOSFET。
所述芯片105具有一个前表面115（图1B）和一个后表面117（图1C）。在前表面115上设置有一个栅极120和一个源极130。在后表面117上设置有一个漏极140。
通过如图9所示的制造过程900，在芯片100上形成栅极触点120，源极触点130，漏极触点140，所述制造过程900包括步骤910，在该步骤中，在晶圆的前侧形成铝焊垫（Al）并在晶圆上形成一个钛/铝合金的背侧金属。在步骤920中，在晶圆背侧形成一个钝化层，在步骤930中，在所述钝化层上形成至少一个窗口以暴露背侧金属。在第一实施例中，形成有一个单一的窗口。在步骤940中，在晶圆的两侧化学镀镍/金（Ni/Au）以进一步提供凸点下金属层（under bump metallization，UBM）作为焊接球的金属触点。在本发明中，除非另有说明，否则所述栅极、源极和漏极触点包括所述UBM。同样，为了简单明了，钝化层图中未示出。
芯片尺寸固定封装100有凸起的触点用于焊接到印刷电路板150上。在步骤950中，将所述焊接球固定在金属触点上，在步骤960中，将凸点晶圆切割成一组凸点芯片110。所述切割可以通过一个特殊的锯子完成。如图1E所示，凸点栅极触点120和凸点源极触点130设置与所述凸点芯片110的前表面115上并被栅极焊接凸点165和源极焊接凸点170覆盖。一个凸点漏极触点140设置在所述凸点芯片110的后表面117上并被一个漏极焊接凸点175覆盖。位于所述金属触点上方的焊接球的轮廓在图1B和图1C中以虚线示出。
参考图1D，所示的是印刷电路板150的俯视图。线迹160a、160b和160c在表面151上形成，并分别包括独立的圆形端163a、163b和163c。线迹160a和160b分别提供与栅极触点120和与源极触点130的电连接，同样线迹160c提供与漏极触点140的电连接。当凸点芯片110被布置在沿印刷电路板的一部分形成的凹槽或缺口155中时，所述圆形端163a、163b和163c尺寸适配的分别铺衬在焊接球165、170和175下。
所述凹槽155尺寸及形状适配地接收凸点芯片110的一个侧部111。所述凹槽155为凸点芯片110提供线性排列，从而使得焊接球165、170和175如图1A和1E所示地分别相应覆盖铺在所述圆形端163a、163b和163c。此外，凹槽155将凸点芯片110保持在一个标准位置上，从而使得在焊接回流时该凸点芯片110的侧部111被设置在凹槽155中。有利的是，非导电印刷电路板150尽可能减少在芯片110的漏极触点140与栅极触点120、源极接触点130之间的短路。此外，当采用激光来切割凸点芯片110时，凸点芯片的侧表面上可以形成二氧化硅来提供进一步的短路保护。
图2E描述了安装在凹槽PCB250上的标准芯片尺寸封装200的俯视图，图2A描述了沿图2E的A-A线的横截面视图。所述标准芯片尺寸封装200包含一个芯片205，该芯片205包括一个功率垂直传导半导体装置，如MOSFET。本实施例与图1A-1E的第一实施例相似，只是其源极和漏极具有多个金属触点而不是一个金属触点。
所述芯片205有一个前表面215（图2B）和一个后表面217(图2C).在前表面215上设置有一个栅极触点220、源极触点230a和230b。漏极触点240a和240b设置在所述后表面217上。随后要被设置在上述触点上的焊接球的轮廓用虚线示出。
如图9所示，在制造过程900中，在芯片205上设置栅极触点220、源极触点230a和230b、漏极触点240a和240b。在本实施例中，在步骤930中，为源极和漏极设置二个窗口。在相应设置有焊接球265，270a和270b的芯片205的前表面215上形成凸点栅极触点220、凸点源极触点230a和230b，在相应设置有焊接球275a 和275b的芯片205的后表面217上形成凸点漏极触点240a和240b，从而形成一个凸点芯片210（如图2E所示）。
图2D是印刷电路板250的俯视图。在表面251上形成线迹260a、 260b、 260c、 260d和260e，其分别相应包括圆形端263a、 263b、 263c、 263d和263e。线迹260a提供与栅极触点220的电连接。线迹260b 和 260c分别提供与源极触点230a和230b的电连接。线迹260d和 260e分别提供与漏极触点240a和240b的电连接。当凸点芯片210被布置在沿印刷电路板的一部分形成的凹槽或缺口255中时，所述圆形端263a、 263b和263c、263d和 263e尺寸适配的分别铺衬在上述焊接球下。
所述凹槽255尺寸及形状适配地接收凸点芯片210的一个侧部211。所述凹槽255为凸点芯片210提供线性排列，从而使得焊接球265、270a和270b、275a和275b如图2A和2E所示地分别相应覆盖铺在所述圆形端263a、 263b和263c、263d和 263e上。此外，凹槽255将凸点芯片210保持在一个标准位置上，从而使得在焊接回流时该凸点芯片210的侧部211被设置在凹槽255中。有利的是，非导电印刷电路板250尽可能减少在芯片210的漏极触点240a、240b与栅极触点220、源极接触点230a、230b之间的短路。
图3A-3E描述了安装本发明第三实施例的标准芯片尺寸封装300，其电连接一个印刷电路板350.所述标准芯片尺寸封装300包含一个芯片305，该芯片305包括一个功率垂直传导半导体装置，如MOSFET。
所述标准芯片尺寸封装300在各方面都与第一实施例中的标准芯片尺寸封装100相同，只是本实施中的标准芯片尺寸封装300电连接一个不具有凹槽的印刷电路板350.
因此，相较于芯片105的触点，芯片305的触点设置在邻近芯片305的边缘处。如图3B 和3C所示，在芯片305的一个前表面315上、邻近芯片305的一个边缘307的位置上形成一个栅极触点320和一个源极触点330。同样的，在后表面317上、邻近边缘304的位置上形成一个漏极触点340。
如图3D所示的印刷电路板350具有与线迹160a、160b、160c（如图1D所示）相同的线迹360a、360b、360c。没有凹槽并且所述凸点芯片310通过焊接回流在圆形端363a、363b、363c处电连接所述线迹360a、360b、360c。
如图3A-3E所示,封装300电连接印刷电路板350。焊接球365、 370 和375被相应逐个焊接到金属层320、330和340。焊接球365、 370 和375的焊接回流分别将栅极触点320连接至线迹360a、将源极触点330连接至线迹360b、将漏极触点340连接至线迹360c。
图4A-4D描述了本发明第四实施例的标准芯片尺寸封装400，其电连接一个印刷电路板450.所述标准芯片尺寸封装400包含一个芯片405，该芯片405包括一个功率垂直传导半导体装置，如MOSFET。
所述芯片405有一个前表面415（图4B）和一个后表面417(图4C)。在前表面415上、邻近芯片405边缘407处设置有一个栅极触点420、一个源极触点430。在所述后表面217上设置有一个漏极触点440，其进一步包括一个厚焊接层。
如图9所示，在制造过程900中，在芯片405上设置栅极触点420、源极触点430、漏极触点440。在芯片405的后表面417上设置一个厚焊接层475。在所述后表面417上不需要钝化层。
图4D是印刷电路板450的俯视图。在表面451上形成线迹460a、 460b，其分别相应包括圆形端463a、 463b。线迹460a提供与栅极触点420的电连接。线迹460b 提供与源极触点430的电连接。线迹460c的传导杆490提供与漏极触点440的电连接。当凸点芯片410被布置在印刷电路板450上时，所述圆形端463a、 463b尺寸适配的分别铺衬在焊接球465、470下，所述印刷电路板450的凸点芯片410的后表面417上的焊接层475邻接所述传导杆490。
图5A-5D描述了本发明第五实施例的标准芯片尺寸封装500，其电连接一个凹槽印刷电路板550。所述标准芯片尺寸封装500包含两个芯片510和520，二者都进一步包括功率垂直传导半导体装置，如MOSFET。芯片510的尺寸大于或等于芯片520的尺寸，并且所述芯片510和芯片520相互连接共漏极配置。
芯片510具有一个前表面511（图5B）和一个后表面（图中未示出）一个栅极触点530和一个源极触点535设置在所述前表面511上。一个漏极触点（图中未示出）包括一个钛/镍/银背侧金属（Ti/Ni/Ag）。芯片520具有一个前表面521（图5B）和一个后表面（图中未示出）一个栅极触点540和一个源极触点545设置在所述前表面521上。一个漏极触点（图中未示出）包括一个钛/镍/银背侧金属（Ti/Ni/Ag）。
在如图10所示的制造过程1000中，芯片510和520的漏极触点可以相互电连接。在步骤1010中，采用了两个晶圆。第一晶圆包括一组芯片510，第二晶圆包括一组芯片520.所述两个晶圆的后侧包括芯片510和520的后表面并包括钛/镍/银背侧金属（Ti/Ni/Ag）。在步骤1020中，所述两个晶圆的前侧都化学镀有镍/金镀层（Ni/Au）作为保护。在步骤1030中，测量芯片510的尺寸是否与芯片520的尺寸相等。如果尺寸相等，则两个晶圆的布局相互匹配，并在随后的步骤1040中，两个晶圆的背侧焊接在一起。在步骤1040中，放置两个晶圆的位置，以使得芯片510和芯片520一一相互匹配。如果芯片510比芯片520打，则在步骤1050中，将第二晶圆切割成若干芯片520，并在步骤1060中，以共漏极的结构将所述芯片520附在第一晶圆的芯片510上。为了实现该目的，匹配过程宜采用红外照相机或激光。在步骤1040和1060中，可以使用导电环氧胶551。可选地，可采用回流温度高于焊接球565、570、575和580的焊接。
在步骤1070中，焊接球位于两个晶圆的前侧，以提供与芯片510和520的栅极触点、源极触点的电连接。如图5A和5E所示，焊接球565、570、575和580分别电连接并位于金属触点530、535、540和545下。最后，在步骤1080中，切割晶圆以形成凸点双芯片共漏极芯片590。
凸点双芯片共漏极芯片590电连接印刷电路板550。参考图5D，印刷电路板550具有线迹560a、560b、560c和560d，其分别相应包括圆形端563a、563b、563c和563d。线迹560a和560b分别提供与第一芯片510的栅极触点530和源极触点535的电连接。线迹560c和560d 提供与第二芯片520的栅极触点540和源极触点545的电连接。当凸点双芯片共漏极芯片590被布置在沿印刷电路板550的一部分形成的凹槽或缺口555上时，所述圆形端563a、563b、563c和563d尺寸适配的分别铺衬在焊接球565、570、575和580下。
所述凹槽555的尺寸适配
所述凹槽555尺寸及形状适配地接收凸点芯片590的一个侧部511。所述凹槽555为凸芯片590提供线性排列，从而使得焊接球565、570、575和580如图5A和5E所示地分别相应覆盖铺在所述圆形端563a、563b、563c和563d上。此外，凹槽555将凸点芯片590保持在一个标准位置上，从而使得在焊接回流时该凸点芯片590的侧部511被设置在凹槽555中。有利的是，非导电印刷电路板550尽可能减少在芯片590的栅极触点与源极触点之间的短路。此外，此外，如果采用激光来切割凸点芯片590，则凸点芯片的侧表面上可以形成二氧化来提供进一步的短路保护。
根据本发明第六实施例，多个标准芯片可以安装在一个PCB上。如图6所示，一个标准芯片尺寸封装600包含一系列连接的三个MOSFET，其电连接至一个印刷电路板650上。第一MOSFET610包括一个栅极触点，其通过焊接球615电连接线迹651a。第一MOSFET610的源极触点通过焊接球617电连接线迹651e。第一MOSFET610的漏极触点通过焊接球619电连接线迹651f。
第二MOSFET620包括一个栅极触点，其通过焊接球621电连接线迹651b。第二MOSFET620的源极触点通过焊接球619电连接线迹651f和第一MOSFET610的漏极。第二MOSFET620的漏极触点通过焊接球623电连接线迹651g。
第三MOSFET630包括一个栅极触点，其通过焊接球625电连接线迹651c。第三MOSFET630的源极触点通过焊接球623电连接线迹651g和第二MOSFET620的漏极。第三MOSFET630的漏极触点通过焊接球627电连接线迹651d。
通过如前所述的制备过程900，形成第一、第二、第三MOSDET610、620、630的栅极、源极和漏极。印刷电路板650最好包括一组凹槽，其尺寸及形状适配的接受MOSFET610、620、630的侧部，从而使得MOSFET610、620、630以标准位置设置在所述印刷电路板650上，该标准位置允许焊接连接具有清楚的视角并减少印刷电路板被占用面积。
如图7所示，本发明的第七实施例中，标准芯片尺寸封装700包括一个芯片705，其电连接一个印刷电路板750。该芯片705包括一个功率垂直传导半导体装置，如MOSFET。
芯片705仅仅在其一侧边710处具有凸点，从而形成凸点芯片710。印刷电路板750上的凹槽755接收凸点芯片710。如前所述，凸点芯片710的触点730通过焊接球770连接印刷电路板的线迹760。线迹760的圆形端763尺寸和形状适配的铺衬在焊接球770下。
流程图8A-8F描述了一个表面安装封装800的形成过程。参考图8A，采用具有一组晶片区域815（仅示出其中一个）的一个假片（dummy wafer）或基底。通过在一组晶片区域815的角上蚀刻出空洞820，形成曲线接触路由823a、823b、823c、823d（如图8B所示）。接下来，如图8C所示，在假片的所有表面上镀上一层铜层825。假片没有被切割成单独的晶片区域815，因此晶片区域815的直边没有暴露，故没有镀上铜层825。然而，蚀刻的接触路由823a-823d提供了晶片815的顶部和底部之间的电连接。
假片和基底的顶部表面和底部表面随后被蚀刻或更简便地被机械半切穿。底部表面830上的铜层凹槽化，提供触点如图8D-2所示的835a、835b、、835c和835d。顶部表面840（图8D-1）被分割以提供顶部接触点847a、847b、847c和847d，上述接触点电分别相应通过蚀刻的接触路由823a、823b、823c、823d连接底部接触点835a、835b、、835c和835d。顶部表面840同样凹槽化，以提供凹槽845。这样就形成了路由晶片850。在图8E中，一个凸点芯片860被安装在凹槽845中的路由晶片850上，如前述实施例一样。凸点芯片860采用焊接回流通过其焊接球电连接触点847a、847b、847c和847d。
组成安装在凸点芯片860上的路由晶片850的假片或基底的顶部采用成型化合物870封装，并被切割形成如图8F所示的表面安装封装800，其中所述成型化合物具有一个适配的成型凹槽并。所述表面安装封装800可以表面安装在一个具有线迹890的印刷电路板880上。
在另一个实施例中，图11描述了与本发明的标准芯片尺寸封装连用的一个引线架1100。一个凸点芯片1110安装在引线架1150的标准位置上，其焊接球1170电连接该引线架。该引线架被包裹在一个塑料模型1190中。这种配置允许小型封装，并减小电线焊接及减小与感应系数和电阻有关的电线。
在之前的实施例中，可以采用任意非传导基底来替代印刷电路板，只要该基底具有适合安装本发明的标准芯片尺寸封装的特征。所述特征包括，用于连接标准芯片尺寸封装的焊接球的线迹，以及用于接收芯片的凹槽。
本发明的标准芯片尺寸封装提供了在芯片两侧与装置触点的电连接、一个清楚地焊接视野和减小的印刷电路安装面积。
上述实施例的具体应用可以通过多种方式实现，然而其仍未脱离本发明的范围。例如，与芯片尺寸封装的底部填充金属上具有涂层相似，可以在印刷电路板的表面做涂层从而提供额外的保护以防止短路。进一步而言，某一实施例的一些方面可以包含部分专利内容，而不使用同一实施例的其他内容。此外，不同实施例的一些方面可以合并使用。本发明的范围应该以其权利要求书所要求的内容加以确定。

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1.一种制造表面安装标准芯片尺寸封装的方法，其特征在于，包括以下步骤：
提供一个假片基底，其具有一组晶片区域；
蚀刻穿透位于每一晶片区域的角的孔洞；
采用铜表面电镀假片基底；
凹槽化每一晶片区域的顶部表面，以形成一个凹槽和一组触点；
凹槽化每一晶片区域的底部表面，以形成一组触点；
底部表面的该组触点中的每一个电连接相对应的顶部表面的那组触点中的一个；
在每一个晶片区域的顶部表面上安装一组凸点芯片；
成型封装该组凸点芯片；
切割假片基底，形成表面安装标准芯片封装。
CN201210414976.4A 2008-06-30 2009-06-05 标准芯片尺寸封装 Expired - Fee Related CN102938383B (zh)

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