CN103021876B - The manufacture method of a kind of high-density QFN packaging - Google Patents
The manufacture method of a kind of high-density QFN packaging Download PDFInfo
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- CN103021876B CN103021876B CN201210549526.6A CN201210549526A CN103021876B CN 103021876 B CN103021876 B CN 103021876B CN 201210549526 A CN201210549526 A CN 201210549526A CN 103021876 B CN103021876 B CN 103021876B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The present invention discloses the manufacture method of a kind of high-density QFN packaging. The chip load of the high-density QFN packaging that manufacture is formed and pin are without the need to based on making shaping lead frame structure in advance, but in potting process, combination etching, plating, chemical plating method form chip carrier and the pin with ledge structure, injection moulding or method for printing screen is adopted outside groove between chip carrier and outer pin and between outer pin and outer pin to configure insulation filling material, capsulation material is adopted to encapsulate, after plastic packaging completes, etching or mechanical grinding method is adopted to form independent chip carrier and pin. Manufacture the QFN with multi-turn pin arrangements formed and there is high I/O density and good reliability.<!--1-->
Description
Technical field
The present invention relates to high-density QFN components and parts manufacturing technology field, refer more particularly to the manufacture method of the four limit flat leadless package parts with high I/O density.
Background technology
Along with electronic product is if mobile phone, notebook computer etc. are towards miniaturization, portable, ultrathin, multimedization and meet popular required low cost direction and develop, the packing forms of high-density, high-performance, high reliability and low cost and package technique thereof obtain and develop fast. Compared with the packing forms such as expensive BGA, novel encapsulated technology fast-developing in recent years, i.e. four limit flat non-pin QFN(QuadFlatNon leadPackage) encapsulation, owing to having good thermal characteristics and electrical property, size is little, cost is low and numerous advantage such as high productivity, has caused a new revolution in microelectronic packaging technology field.
Figure 1A and Figure 1B is respectively the schematic rear view of tradition without the QFN encapsulation structure of staircase structural model design and the diagrammatic cross-section along I-�� section, this QFN encapsulates structure and comprises lead frame 11, capsulation material 12, adhesive material 13, IC chip 14, metal wire 15, wherein lead frame 11 comprises chip carrier 111 and the pin 112 around the arrangement of chip carrier 111 surrounding, IC chip 14 is fixed on chip carrier 111 by adhesive material 13, IC chip 14 realizes electrical connection with the pin 112 of surrounding arrangement by metal wire 15, capsulation material 12 is to IC chip 14, metal wire 15 and lead frame 11 carry out the effect encapsulating to reach protection and support, the exposed bottom surface at capsulation material 12 of pin 112, it is welded on the circuit cards such as PCB by solder to realize the electrical connection with the external world. the exposed chip carrier 111 in bottom surface is welded on by solder on the circuit cards such as PCB, has direct heat dissipation channel, it is possible to the heat that effectively release IC chip 14 produces. as compared to traditional TSOP with SOIC encapsulation, QFN encapsulation does not have gull wing lead-in wire, and conductive path is short, and coefficient of self-induction and impedance are low, thus can provide good electrical property, can meet at a high speed or the application of microwave. exposed chip carrier provides remarkable heat dispersion.
Along with the raising of IC integrated level and the continuous enhancing of function, the I/O number of IC increases thereupon, the also corresponding increase of the I/O number of pins of corresponding Electronic Packaging, but four traditional limit flat leadless package parts, the pin of single circle is periphery arrangement around chip carrier, limit the raising of I/O quantity, can not meet high-density, have the needs of the IC of more I/O numbers. Even if traditional QFN encapsulation without ledge structure design has the pin of multi-turn arrangement, owing to cannot effectively pin capsulation material, cause lead frame and capsulation material bonding strength low, the layering being easy to cause lead frame and capsulation material even the coming off of pin or chip carrier, and cannot effectively stop moisture to be diffused into Electronic Packaging inside along lead frame and capsulation material bonding interface, seriously have impact on the reliability of package. Even if traditional QFN encapsulation has ledge structure design, can only be realize based on single circle pin or staggered multi-turn pin, each outer end of all pins must extend to package side, it is exposed in outside atmosphere, moisture is caused very easily to diffuse to encapsulation inner, affect the reliability of product, and the restriction due to space, more highdensity encapsulation cannot be realized at all. The chip load of traditional Q FN encapsulation and pin must make shaping lead frame structure based on prior, otherwise chip load and pin cannot complete all potting process due to shortage mechanical support and connection. Need when traditional Q FN is encapsulated in plastic package process in advance at lead frame back side Continuous pressing device for stereo-pattern to prevent flash phenomena, also need to carry out to remove the cleaning such as adhesive tape, plastic cement overlap after plastic packaging, add packaging cost and increase. Therefore, in order to break through the bottleneck of the low I/O quantity that traditional Q FN encapsulates, solve the above-mentioned reliability of traditional Q FN encapsulation and reduce packaging cost, the QFN packaging of urgent need a kind of high reliability of research and development, low cost, high I/O density and manufacture method thereof.
Summary of the invention
The present invention provides the manufacture method of a kind of high-density QFN packaging, to reach the object breaking through the low I/O quantity of traditional Q FN encapsulation, the bottleneck of high packaging cost and improving the reliability of package.
In order to realize above-mentioned purpose, the present invention adopts following technical proposals, comprises the following steps:
Step 1: adopt exposure imaging method, surface forms the mask layer with window on metal base.
Step 2: using there is window mask layer as resist layer, metal base upper surface is etched, forms outer chip carrier, outer pin and groove.
Step 3: remove the mask layer being configured at metal base upper surface.
Step 4: adopt in injection moulding or the method for printing screen groove outside between chip carrier and outer pin, between outer pin and outer pin and configure insulation filling material.
Step 5: adopt exposure imaging method, the surface location at insulation filling material makes the mask layer with window.
Step 6: chip carrier and interior pin in adopting electroless plating and electro-plating method to make in the window of mask layer successively, form the chip carrier pin with ledge structure, wherein chip carrier comprises interior chip carrier and outer chip carrier, and pin comprises interior pin and outer pin.
Step 7: adopt plating or chemical plating method to configure the first metal material layer on the surface of interior chip carrier and interior pin.
Step 8: the mask layer removing the surface being configured at insulation filling material.
Step 9: by adhesive material by IC chip configuration on the first metal material layer of interior chip carrier or interior pin surface.
Multiple bonding welding pads on step 10:IC chip are connected to the first metal material layer of interior chip carrier and interior pin configuration respectively by metal wire.
Step 11: adopt the coated sealing IC chip of injection moulding process capsulation material, adhesive material, metal wire, internal sheet carrier, interior pin and the first metal material layer.
Step 12: require to carry out after fixing according to the after fixing of selected capsulation material.
Step 13: adopt mechanical grinding method or engraving method to be subtracted by metal base thin, form independent chip carrier and pin.
Step 14: adopt and make the 2nd metal material layer on the surface of chemical plating method chip carrier and outer pin outside.
Step 15: cutting and separating product, forms independent single package.
According to embodiments of the invention, the chip carrier of formation is made up of interior chip carrier and outer chip carrier, manufactures the pin formed and is made up of interior pin and outer pin.
According to embodiments of the invention, metal base is subtracted thin before, the chip carrier of formation is connected with metal base with pin.
According to embodiments of the invention, mechanical grinding method or engraving method is adopted to be subtracted by metal base thin, it is achieved independent chip carrier and pin.
According to embodiments of the invention, the size of interior chip carrier and interior pin is greater than outer chip carrier and the size of outer pin respectively.
According to embodiments of the invention, adopt insulation filling material and capsulation material to carry out two coated sealings and form packaging.
According to embodiments of the invention, manufacture formed packaging have multiple around chip carrier be multi-turn arrange pin.
According to embodiments of the invention, manufacture the pin that the packaging formed has the arrangement in face battle array.
According to embodiments of the invention, the arrangement mode manufacturing the multiple pins formed is not limit, and can be arranged in parallel, it is possible to for being staggered.
According to embodiments of the invention, the cross section shape manufacturing the multiple pins formed is not limit, and can be circle, it is possible to be rectangle.
According to embodiments of the invention, the chip carrier and the pin that manufacture the packaging formed have ledge structure.
Based on above-mentioned, according to the present invention, the chip load of the high-density QFN packaging that manufacture is formed and pin are without the need to based on making shaping lead frame structure in advance, namely without the need to relying on traditional lead frame to provide mechanical support and connection, but in potting process, first adopt to have and make precision height, the engraving method of the features such as control property is strong makes outer pin and outer chip carrier, then insulation filling material is configured in a groove, then adopt successively to have and make precision height, planeness is good, the electroless plating of the features such as control property is strong and electro-plating method make interior pin and interior chip carrier, it is last after plastic package process completes, it is low that employing has cost, the mechanical grinding method of the features such as planeness is good, or adopt to have and make precision height, the engraving method entirety of the features such as control property is strong subtracts the thickness of thin metal matrix material, form the independent chip carrier with ledge structure and pin. the present invention adopts two encapsulating methods, namely insulation filling material and capsulation material is adopted to carry out two coated sealings, wherein insulation filling material be configured in the groove of chip carrier and ledge structure below, region more than staircase structural model adopts capsulation material to carry out coated sealing, this filling, clad structure feature can realize encapsulating without cavity of encapsulation, eliminate the defects such as the bubble because encapsulating not exclusively generation, cavity. the high-density QFN packaging that the present invention manufactures formation has high I/O density, the staircase structural model of chip carrier and pin adds the bonded area with capsulation material, there is the effect mutually locked with capsulation material, can effectively prevent coming off of the layering of chip carrier and pin and capsulation material and pin or chip carrier, effectively stop moisture to encapsulation internal divergence, the generation of bridging phenomenon when the outer pin of small area size can effectively prevent surface mount, chip carrier and pin upper, the metal material layer of lower surface configuration can effectively improve metal lead wire bonding quality and surface mount quality, there is good reliability, and the arrangement mode of pin do not limit, can be arranged in parallel, can also for being staggered, all pins are without the need to extending to package side.
Special embodiment below, and coordinate accompanying drawing the above-mentioned feature and advantage of the present invention to be elaborated.
Accompanying drawing explanation
Figure 1A is the schematic rear view that traditional Q FN encapsulates structure;
Figure 1B is the diagrammatic cross-section along the I-�� section in Figure 1A;
Fig. 2 A be the pin cross section drawn according to embodiments of the invention 1 for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of high-density QFN packaging arranged in parallel;
Fig. 2 B is along the I-in Fig. 2 AIThe diagrammatic cross-section of section;
Fig. 3 A to Fig. 3 O is the manufacturing process diagrammatic cross-section of the high-density QFN packaging drawn according to embodiments of the invention 1, and all diagrammatic cross-sections are all along the diagrammatic cross-section shown in Fig. 2 B section.
Fig. 4 is the schematic rear view with the high-density QFN packaging in face battle array pin arrangements drawn according to embodiments of the invention 2;
Fig. 5 A is along the I-in Fig. 4IFirst diagrammatic cross-section of section.
Fig. 5 B is along the I-in Fig. 4I2nd diagrammatic cross-section of section.
Number in the figure: 100. traditional four limit flat non-pin encapsulation, 11. lead frames, 111. chip carrier, 112. pin, 12. capsulation materials, 13. adhesive materials, 14.IC chip, 15. metal wires, 200. have the high-density QFN encapsulation of multi-turn pin arrangements, 300. have the high-density QFN in face battle array pin arrangements encapsulates, 20. metal bases, 20a. metal base upper surface, 20b. metal base lower surface, 21. mask layer, 22. chip carriers, the outer chip carrier of 22a., chip carrier in 22b., 23. pins, the outer pin of 23a., pin in 23b., 24. grooves, 25. insulation filling materials, 26. mask layer, 27. ledge structures, 28. first metal material layers, 29. adhesive materials, 30.IC chip, 31. metal wires, 32. capsulation materials, 33. the 2nd metal material layers.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in detail:
Fig. 2 A be the pin cross section drawn according to embodiments of the invention for circular, and the pin arrangements mode on the every limit of chip carrier is the schematic rear view of the high-density QFN packaging with multi-turn pin arrangements arranged in parallel.
Can find out with reference to above-mentioned Fig. 2 A, in the present embodiment, the high-density QFN packaging 200 with multi-turn pin arrangements has chip carrier 22 and the pin 23 around chip carrier 22 arrangement in multi-turn, the arrangement mode of the pin 23 on the every limit of chip carrier 22 is arranged in parallel, the cross section of pin 23 is circular, there is the 2nd metal material layer 33 in the surface configuration of chip carrier 22 and pin 23, high-density QFN packaging 200 is configured with insulation filling material 25. In the present embodiment, the arrangement mode of pin 23 is not defined as arranged in parallel, it is possible to being other arrangement modes, the cross section shape of pin 23 is not defined as circle, it is possible to be rectangle.
Fig. 2 B is along the I-in Fig. 2 AIThe diagrammatic cross-section of section. Composition graphs 2A, with reference to Fig. 2 B, in the present embodiment, the high-density QFN packaging 200 with multi-turn pin arrangements comprises chip carrier 22, pin 23, insulation filling material 25, ledge structure 27, first metal material layer 28, adhesive material 29, IC chip 30, metal wire 31, capsulation material 32 and the 2nd metal material layer 33, wherein chip carrier 22 comprises outer chip carrier 22a and interior chip carrier 22b, and pin 23 comprises outer pin 23a and interior pin 23b.
Chip carrier 22 is configured at the central part of the high-density QFN packaging 200 with multi-turn pin arrangements, its rectangular shape of cross section shape. Pin 23 is around chip carrier 22 arrangement in multi-turn, and its cross section shape is rounded or rectangular-shaped. Chip carrier 22 and pin 23, as the passage of conduction, heat radiation, connection external circuit, have ledge structure 27. Insulation filling material 25 is configured at below the ledge structure 27 of chip carrier 22 and pin 23. First metal material layer 28 and the 2nd metal material layer 33 are configured at upper surface and the lower surface of chip carrier 22 and pin 23 respectively. The first metal material layer 28 position that IC chip 30 is configured on chip carrier 22 by adhesive material 29, multiple bonding welding pads on IC chip 30 are connected to the first metal material layer 28 of interior chip carrier 22b and interior pin 23b configuration respectively by metal wire 31, it is achieved electrical interconnection and ground connection. The coated sealing of capsulation material 32 above-mentioned IC chip 30, adhesive material 29, metal wire 31, interior chip carrier 22b, interior pin 23b and the first metal material layer 28; expose the 2nd metal material layer 33 being configured on outer chip carrier 22a and outer pin 23a, the high-density QFN packaging 200 with multi-turn pin arrangements is played and supports and the effect of protection.
The manufacturing process of the high-density QFN packaging with multi-turn pin arrangements will be described in detail with Fig. 3 A to Fig. 3 O below.
Fig. 3 A to Fig. 3 O is the manufacturing process diagrammatic cross-section of the high-density QFN packaging with multi-turn pin arrangements drawn according to embodiments of the invention 1, and all diagrammatic cross-sections are all along the diagrammatic cross-section shown in Fig. 2 B section.
Please refer to Fig. 3 A, there is provided and there is upper surface 20a and the metal base 20 of the lower surface 20b relative to upper surface 20a, the material of metal base 20 can be copper, copper alloy, iron, iron alloy, nickel, nickelalloy and other metallic substance being applicable to make chip carrier and pin, prioritizing selection copper or Cu alloy material. The thickness range of metal base 20 is 0.1mm-0.3mm. The upper surface 20a and lower surface 20b of metal base 20 is cleaned and pre-treatment, such as, deoils dirt, dust etc. with plasma water, with the object that to realize the upper surface 20a and lower surface 20b of metal base 20 cleaning.
Please refer to Fig. 3 B, the upper surface 20a of metal base 20 is made the mask layer 21 with window by exposure imaging method, window described here refers to the part region of the metal base 20 not covered by mask layer 21, the part region of the metal base 20 that mask layer 21 protection is entirely covered. mask layer 21 requires to be combined firmly with metal base 20, has thermostability, as against corrosion, plating resist layer, has etching resistence and plating resist. for exposure imaging making method, first it is coated with photic wet film at the upper surface 20a of metal base 20, coating process can be curtain coating, roller coating and spraying etc., or paste photic dry film at the upper surface 20a of metal base 20, and then under being exposed to certain light source, such as UV-light, electron beam or X-ray, utilize the light sensitive characteristic of the chemistry sensitive materialss such as photic wet film and photic dry film, photic wet film or photic dry film are optionally exposed, mask plate patterns is duplicated on photic wet film or photic dry film, finally on the upper surface 20a of metal base 20, mask layer 21 is formed after using developing solution to carry out developing process.
Please refer to Fig. 3 C, using there is window mask layer 21 as resist layer, select the etching solution of only etching metal base material 20, spray pouring mode is adopted to be etched by metal base upper surface 20a, forming outer chip carrier 22a, outer pin 23a and groove 24, the outer chip carrier 22a formed through etching and the thickness range of outer pin 23a are 0.03mm-0.15mm. In the present embodiment, the spray of etching solution is drenched mode and is preferentially adopted spray pouring mode, and in etching solution, add a small amount of organism, to reduce etching solution to the lateral erosion effect of metal base 20, it is the polymer materials such as wet film or dry film with light sensitive characteristic due to mask layer 21, acid resistance not alkali resistance, as the resist layer of etching, etching solution prioritizing selection acidic etching liquid, such as acid copper chloride etching liquid, iron(ic) chloride etching solution, to reduce etching solution to the destruction of mask layer 21.
Please refer to Fig. 3 D, mask layer 21 on the upper surface 20a of metal base 20 is removed, removing method in the present embodiment can be chemical reaction method and mechanical means, chemical reaction method is the basic solution selecting solubility, such as potassium hydroxide (KOH), sodium hydroxide (NaOH), the mask layer 21 on the upper surface 20a of the modes such as spray pouring and metal base 20 is adopted to carry out chemical reaction, dissolved thus reached the effect removed, also can select organic to go film liquid to be removed by mask layer 21, after removing mask layer 21, metal base 20 only exists outer chip carrier 22a and outer pin 23a, outside between chip carrier 22a and outer pin 23a, groove 24 is formed between outer pin 23a and outer pin 23a.
Please refer to Fig. 3 E, adopt injection moulding or method for printing screen outside groove 24 between chip carrier 22a and outer pin 23a, between outer pin 23a and outer pin 23a to configure insulation filling material 25. in the present embodiment, insulation filling material 25 is thermoset capsulation material, plug socket resin, the insulating material such as ink and welding resistance green oil, insulation filling material 25 has enough acidproof, alkali resistance, to ensure that follow-up technique can not damage being formed insulation filling material 25, fill the insulation filling material 25 that after fixing forms suitable hardness, photocuring insulation filling material 25 is needed to carry out ultraviolet exposure, insulation filling material 25 after hardening has certain intensity, with outer chip carrier 22a and outer pin 23a, there is the effect of locking mutually, too much insulation filling material 25 is removed with mechanical grinding method or chemical treatment method, to eliminate the excessive material of insulation filling material 25, for insulation filling materials 25 such as photosensitive type welding resistance green oils, the material that overflows is removed by developing method.
Please refer to Fig. 3 F, made the mask layer 26 with window by exposure imaging method on the surface of insulation filling material 25, window described here refers to the part region on table 20a and insulation filling material 25 surface on the metal base not covered by mask layer 26, and mask layer 26 protects the part region being entirely covered. mask layer 26 requires to be combined firmly with insulation filling material 25, has thermostability, as against corrosion, plating resist layer, has etching resistence and plating resist. for exposure imaging making method, first at the photic wet film of surface coating of insulation filling material 25, coating process can be curtain coating, roller coating and spraying etc., or the photic dry film of surface stickup at insulation filling material 25, and then under being exposed to certain light source, such as UV-light, electron beam or X-ray, utilize the light sensitive characteristic of the chemistry sensitive materialss such as photic wet film and photic dry film, photic wet film or photic dry film are optionally exposed, mask plate patterns is duplicated on photic wet film or photic dry film, finally on the surface of insulation filling material 25, mask layer 26 is formed after using developing solution to carry out developing process.
Please refer to Fig. 3 G, chip carrier 22b and interior pin 23b in adopting electroless plating and electro-plating method to make in the window of mask layer 26 successively, form chip carrier 22 and multiple pin 23 with ledge structure 27, wherein chip carrier comprises interior chip carrier 22b and outer chip carrier 22a, and pin 23 comprises interior pin 23b and outer pin 23a. First adopt chemical plating method to form one layer of extremely thin metal level in the window of mask layer 26, then adopt electro-plating method to be formed and there is certain thickness interior chip carrier 22b and interior pin 23b. The material of interior chip carrier 22b and interior pin 23b is metallic substance and the alloys thereof such as copper (Cu), nickel (Ni), iron (Fe), aluminium (Al), and allow to be made up of different metallic substance, prioritizing selection copper or copper alloy are as the material of interior chip carrier 22b and interior pin 23b, it is possible to be identical material with outer chip carrier 22a and outer pin 23a. Electroless plating and electro-plating method have the features such as high precision, high-flatness, controllability be strong, can being used for making ultra-thin interior chip carrier 22b and interior pin 23b, the interior chip carrier 22b formed through electroless plating and electro-plating method and the thickness range of interior pin 23b are 0.03mm-0.15mm.
Please refer to Fig. 3 H, adopt plating or chemical plating method to make the first metal material layer 28 on the surface of interior chip carrier 22b and interior pin 23b. The material of the first metal material layer 28 is nickel (Ni), palladium (Pd), gold (Au), silver metallic substance and the alloy thereof such as (Ag), tin (Sn). The thickness range of the first metal material layer 28 is 0.002mm-0.03mm. In the present embodiment, first metal material layer 28 is such as nickel-palladium-gold plate, the gold plate of outside and middle palladium coating ensure bond ability on interior chip carrier 22b and interior pin 23b of in lead-in wire bonding technology metal wire 31 and bonding quality, the nickel coating of the inside is as diffusion impervious layer to prevent the generation of the thick cocrystalization compound of the mistake caused by Elements Diffusion-chemical reaction, and excessively thick cocrystalization compound affects the reliability of surface mount welding region.
Please refer to Fig. 3 I, mask layer 26 is removed, removing method in the present embodiment can be chemical reaction method and mechanical means, chemical reaction method is the basic solution selecting solubility, such as potassium hydroxide (KOH), sodium hydroxide (NaOH), adopt the spray mode such as pouring and mask layer 26 to carry out chemical reaction, dissolved thus reach the effect removed, it is possible to select organic to go film liquid to be removed by mask layer 26.
Please refer to Fig. 3 J, by adhesive material 29, IC chip 30 is configured at first metal material layer 28 position of interior chip carrier 22b. In the present embodiment, adhesive material 29 can be sticky sheet adhesive tape, the material such as epoxy resin containing Argent grain, after configuration IC chip 30, adhesive material 29 need to carry out high bake solidification, to strengthen and the bonding strength of IC chip 30, first metal material layer 28.
Please refer to Fig. 3 K, the multiple bonding welding pads on IC chip 30 are connected to the first metal material layer 28 of interior chip carrier 22b and interior pin 23b configuration by metal wire 31, it is achieved electrical interconnection and ground connection. In the present embodiment, metal wire 31 is gold thread, aluminum steel, copper cash and plating palladium copper cash etc.
Please refer to Fig. 3 L, adopt injection moulding process, by heat, with the environment-friendly type plastic closure material 32 of low water absorption, low-stress coated sealing IC chip 30, adhesive material 29, metal wire 31, interior chip carrier 22b, interior pin 23b and the first metal material layer 28. In the present embodiment, capsulation material 32 can be the materials such as thermosetting polymer, the insulation filling material 25 filled has the physical properties similar to capsulation material 32, such as thermal expansivity, to reduce the product failure caused by thermal mismatching, improving the reliability of product, insulation filling material 25 and capsulation material 32 can be same materials. Baking after fixing is carried out after plastic packaging, capsulation material 32 and insulation filling material 25 have mutual lock function with the chip carrier 22 and pin 23 with ledge structure 27, can effectively prevent coming off of the layering of chip carrier 22 and pin 23 and capsulation material 32 and insulation filling material 25 and pin 23 or chip carrier 22, and effectively stop the moisture to be diffused into package interior along the bonding interface of chip carrier 22 and pin 23 with capsulation material 32 and insulation filling material 25, it is to increase the reliability of package. After after fixing, product array is carried out Laser Printing.
Please refer to Fig. 3 M, adopting mechanical grinding method or engraving method to subtract thin to metal base 20 from lower surface 20b, until exposing insulation filling material 25, forming independent chip carrier 22 and pin 23. In mechanical grinding method, successively lower surface 20b to metal base 20 roughly grind, fine grinding and fine grinding, in the process of grinding, can suitably add chemical medicinal liquid, in conjunction with the quality of method for chemially etching with elevating gear grinding. In engraving method, select the etching solution of only etching metal base material 20, adopt spray pouring mode that metal base 20 lower surface 20b carries out overall etching.
Please refer to Fig. 3 N, adopt chemical plating method outside chip carrier 22a and outer pin 23a surface making the 2nd metal material layer 33. The material of the 2nd metal material layer 33 is nickel (Ni), palladium (Pd), gold (Au), silver metallic substance and the alloy thereof such as (Ag), tin (Sn). The thickness range of the 2nd metal material layer 33 is 0.002mm-0.03mm. In the present embodiment, 2nd metal material layer 33 is such as nickel-palladium-gold plate, the gold plate of outside and middle palladium coating be ensure solder outside chip carrier 22a and outer pin 23a can wetting property, improve the quality of package in circuit card upper surface attachments such as PCB, the nickel coating of the inside is as diffusion impervious layer to prevent the generation of the thick cocrystalization compound of the mistake caused by Elements Diffusion-chemical reaction, and excessively thick cocrystalization compound affects the reliability of surface mount welding region.
Please refer to Fig. 3 O, cutting has the product array of the high-density QFN packaging 200 of multi-turn pin arrangements, thorough cutting and separating insulation filling material 25 and capsulation material 32 form the single high-density QFN packaging 200 with multi-turn pin arrangements, in the present embodiment, single product separation method is the methods such as blade cuts, laser cutting or high pressure waterjet, and only cut insulation filling material 25 and capsulation material 31, not cutting metal material, 2 after only drawing out cutting and separating in Fig. 3 O have the high-density QFN packaging 200 of multi-turn pin arrangements.
Fig. 4 is the schematic rear view with the high-density QFN packaging 300 in face battle array pin arrangements drawn according to embodiments of the invention 2, its middle-high density QFN packaging 300 has the pin 23 of face battle array arrangement, surface configuration at pin 23 has the 2nd metal material layer 33, high-density QFN packaging 300 is configured with insulation filling material 25, the arrangement mode of pin 23 is not limit, can be arranged in parallel, can also for being staggered, the cross section shape of pin 23 can be circle or rectangle, identical with cross section shape with the arrangement mode of multi-turn pin 23 in embodiment 1. in the present embodiment, the arrangement mode of the face battle array pin 23 of high-density QFN packaging 300 is arranged in parallel, and the cross section shape of pin 23 is circular.
Fig. 5 A is along the I-in Fig. 4IFirst diagrammatic cross-section of section. Composition graphs 4, with reference to Fig. 5 A, in the present embodiment, high-density QFN packaging 300 in face battle array pin arrangements comprises pin 23, first metal material layer 28, the 2nd metal material layer 33, insulation filling material 25, ledge structure 27, adhesive material 29, IC chip 30, metal wire 31 and capsulation material 32, wherein pin 23 comprises outer pin 23a and interior pin 23b. The manufacture method of the high-density QFN packaging 300 in face battle array pin arrangements and flow process and embodiment 1 have high-density QFN packaging 200 completely the same of multi-turn pin arrangements.
Fig. 5 B is along the I-in Fig. 4ISection the 2nd diagrammatic cross-section. Composition graphs 4, with reference to Fig. 5 B, in the present embodiment, high-density QFN packaging 300 in face battle array pin arrangements comprises interior chip carrier 22b, pin 23, insulation filling material 25, first metal material layer 28, the 2nd metal material layer 33, ledge structure 27, adhesive material 29, IC chip 30, metal wire 31 and capsulation material 32, wherein pin 23 comprises outer pin 23a and interior pin 23b. The manufacture method of the high-density QFN packaging 300 in face battle array pin arrangements and flow process and embodiment 1 have high-density QFN packaging 200 completely the same of multi-turn pin arrangements.
It is for the object effectively illustrating and describing the present invention to the description of embodiments of the invention, and be not used to limit the present invention, belonging to any, the technician of this area is it is understood that when not departing from invention design and the scope of the present invention, can change above-described embodiment. Therefore the present invention is not limited to disclosed specific embodiment, but cover the amendment in the spirit and scope of the invention that define of claim.
Claims (1)
1. a manufacture method for high-density QFN packaging, comprises the following steps:
A () adopts exposure imaging method, surface forms the mask layer with window on metal base;
(b) using there is window mask layer as resist layer, metal base upper surface is etched, forms outer chip carrier, outer pin and groove;
C () removes the mask layer being configured at metal base upper surface;
D () adopts in injection moulding or the method for printing screen groove outside between chip carrier and outer pin, between outer pin and outer pin and configures insulation filling material;
E () adopts exposure imaging method, the surface location at insulation filling material makes the mask layer with window;
(f) adopt electroless plating and electro-plating method to make in the window of mask layer successively in chip carrier and interior pin, form chip carrier and the pin with ledge structure, wherein chip carrier comprises interior chip carrier and outer chip carrier, and pin comprises interior pin and outer pin;
G () adopts plating or chemical plating method at surface configuration first metal material layer of interior chip carrier and interior pin;
H () removes the mask layer being configured at insulation filling material surface;
(i) by adhesive material by IC chip configuration on the first metal material layer of interior chip carrier or interior pin configuration;
J the multiple bonding welding pads on () IC chip are connected to the first metal material layer of interior chip carrier and interior pin configuration respectively by metal wire;
K () adopts the coated sealing IC chip of injection moulding process capsulation material, adhesive material, metal wire, interior chip carrier, interior pin and the first metal material layer, carry out baking after fixing after plastic packaging; Adopting insulation filling material and capsulation material to carry out two coated sealings, capsulation material and insulation filling material have mutual lock function with the chip carrier and pin with ledge structure;
L () adopts mechanical grinding method or engraving method to subtract thin from lower surface to metal base, until exposing insulation filling material, form chip carrier and the pin with ledge structure;
M () adopts chemical plating method chip carrier and the surperficial of outer pin make the 2nd metal material layer outside;
N () separation forms independent single package.
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| CN104701290A (en) * | 2013-12-06 | 2015-06-10 | 上海北京大学微电子研究院 | QFN (quad flat no-lead) package structure for multiple circles of lead frames |
| CN109037077B (en) * | 2018-06-13 | 2020-12-25 | 南通通富微电子有限公司 | Semiconductor chip packaging method |
| CN109002806A (en) * | 2018-07-27 | 2018-12-14 | 星科金朋半导体（江阴）有限公司 | A kind of rear road packaging method of QFN product |
| CN109256367B (en) * | 2018-10-24 | 2024-03-22 | 嘉盛半导体(苏州)有限公司 | Pre-plastic package lead frame, semiconductor package structure, unit and package method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101131980A (en) * | 2006-08-23 | 2008-02-27 | 南茂科技股份有限公司 | Wafer packaging construction with array connecting pad and method of manufacturing the same |
| US7482690B1 (en) * | 1998-06-10 | 2009-01-27 | Asat Ltd. | Electronic components such as thin array plastic packages and process for fabricating same |
| CN102354691A (en) * | 2011-11-04 | 2012-02-15 | 北京工业大学 | Quad flat non-lead (QFN) package with high density and manufacturing method |
| CN102446882A (en) * | 2011-12-30 | 2012-05-09 | 北京工业大学 | Semiconductor PiP (package in package) system structure and manufacturing method thereof |
| CN202384324U (en) * | 2011-12-30 | 2012-08-15 | 北京工业大学 | Semiconductor package-in-package (PiP) system structure |
-
2012
- 2012-12-17 CN CN201210549526.6A patent/CN103021876B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7482690B1 (en) * | 1998-06-10 | 2009-01-27 | Asat Ltd. | Electronic components such as thin array plastic packages and process for fabricating same |
| CN101131980A (en) * | 2006-08-23 | 2008-02-27 | 南茂科技股份有限公司 | Wafer packaging construction with array connecting pad and method of manufacturing the same |
| CN102354691A (en) * | 2011-11-04 | 2012-02-15 | 北京工业大学 | Quad flat non-lead (QFN) package with high density and manufacturing method |
| CN102446882A (en) * | 2011-12-30 | 2012-05-09 | 北京工业大学 | Semiconductor PiP (package in package) system structure and manufacturing method thereof |
| CN202384324U (en) * | 2011-12-30 | 2012-08-15 | 北京工业大学 | Semiconductor package-in-package (PiP) system structure |
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