CN103094339A

CN103094339A - N-channel metal oxide semiconductor (NMOS) device and manufacturing method thereof

Info

Publication number: CN103094339A
Application number: CN2011103405330A
Authority: CN
Inventors: 刘冬华; 胡君; 钱文生; 韩峰; 石晶; 陈雄斌
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-11-01
Filing date: 2011-11-01
Publication date: 2013-05-08

Abstract

The invention discloses an N-channel metal oxide semiconductor (NMOS) device. The NMOS device comprises a P type lining, shallow groove isolation, a P trap, a thermal oxidation layer, a silica dielectric layer, a silicon nitride hard mask layer, an isolation lateral wall and a compensation region. The shallow groove isolation, the thermal oxidation layer, the P trap and the compensation region are arranged at the top of the P type lining in parallel, the thermal oxidation layer and the compensation region are arranged between the shallow groove isolation and the P trap, the silica dielectric layer is arranged at the top of the P trap, the isolation lateral wall is arranged at the top of the compensation region and is adjacent to the silica dielectric layer, the silicon nitride hard mask layer is arranged at the top of the silica dielectric layer and is adjacent to the isolation lateral wall, and the thermal oxidation layer is provided with P type impurities. The invention further discloses a manufacturing method of the NMOS device, through the NMOS device and the manufacturing method of the NMOS device, narrow groove effect of the NMOS device in a deep submicron process can be restrained.

Description

A kind of nmos device and manufacture method thereof

Technical field

The present invention relates to integrated circuit and make the field, particularly relate to a kind of nmos device.The invention still further relates to a kind of manufacture method of nmos device.

Background technology

In producing process of deep submicron integrated circuit, due to the employing of narrow trench isolation process (Shallow Trench Isolation), narrow channel device presents the characteristic different from wide channel device.Be mainly reflected in the threshold voltage step-down, cut-off leakage current increases, and forms narrow channel effect.Particularly in the stochastic and dynamic memory (SRAM) in the market that is widely used, six devices that memory cell adopts are all narrow ditch devices.Add the characteristics at a high speed that have of stochastic and dynamic memory, device all requires to have the output characteristic of drive current.These two factors are superimposed, and the quiescent dissipation that reduces SRAM just becomes a challenge of present producing process of deep submicron integrated circuit.Particularly for NMOS, its groove is the doping of P type, and impurity is boron.Due to boron at the segregation coefficient of silicon dioxide and silicon interface greater than 1, the thermal process of back can cause touching of active area side to extend out, and causes the impurity concentration at active area edge to become lower than the centre.Therefore the narrow channel effect of nmos device is more serious than PMOS device.

In order to suppress the narrow channel effect of MOSFET device, industry each company carried out many trials.Two kinds of more common methods are: method one, the angle of control groove side when controlling narrow etching groove.In general side more tilts, and narrow trench bottom corners is round, and the electric leakage meeting of device is less.Method two carries out corners to the corner of active area and processes (Corner Rounding).Improve the performance of narrow trench device by the electric field concentration effect that alleviates the corner.Above two kinds of methods are all by industry-wide adoption, but the shortcoming of himself is also arranged.First method, side are too oblique, will cause two isolation performance variation between active area, and an oxygen is filled also can become more difficult.Second method can cause the developed width of active area large with the mutation of design stand out.

Summary of the invention

The technical problem to be solved in the present invention is to provide the narrow channel effect that a kind of nmos device structure can suppress nmos device in deep submicron process.For this reason, the present invention also provides a kind of manufacture method of nmos device.

For solving the problems of the technologies described above, nmos device of the present invention comprises:

P type substrate, shallow trench isolation are from, P trap, thermal oxide layer, titanium dioxide dielectric layer, silicon nitride hard mask layer, isolation side walls and compensating basin, described shallow trench isolation is listed in P type substrate top from, thermal oxide layer, P trap and compensating basin, described thermal oxide layer and compensating basin are between shallow-trench isolation and P trap, described silica dioxide medium layer is positioned at above the P trap, it is adjacent with the silica dioxide medium layer that described isolation side walls is positioned at compensating basin top, and described silicon nitride hard mask layer is positioned at above the silica dioxide medium layer adjacent with isolation side walls; Wherein, described thermal oxide layer has p type impurity.

Described thermal oxide layer thickness is 100 dust to 300 dusts.

During implementation step (4), injecting p type impurity is boron or boron fluoride, and injecting p type impurity dosage is 1e13cm ^-2To 5e14cm ^-2, energy is 5keV to 50keV.

Nmos device manufacture method of the present invention comprises:

(1) inject formation P trap on P type substrate;

(2) growth silica dioxide medium layer, the deposit silicon nitride hard mask layer is made the etching shallow-trench isolation;

(3) Heat of Formation oxide layer;

(4) thermal oxide layer being carried out p type impurity injects;

(5) heat treatment, etching is made the compensating basin;

(6) make isolation side walls.

During implementation step (3), the Heat of Formation oxidated layer thickness is 100 dust to 300 dusts.

During implementation step (4), injecting p type impurity is boron or boron fluoride.

During implementation step (4), injecting p type impurity dosage is 1e13cm ^-2To 5e14cm ^-2, energy is 5keV to 50keV.

The thermal oxide layer of nmos device of the present invention has p type impurity, forms the narrow channel effect that the middle high or suitable active area of side concentration ratio can suppress nmos device.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is the schematic cross-section one of nmos device of the present invention, and it shows the device mechanism of parallel groove direction.

Fig. 2 is the schematic cross-section two of nmos device of the present invention, and it shows the device mechanism of vertical trench direction.

Fig. 3 is the flow chart of manufacture method of the present invention.

Fig. 4 is the schematic diagram one of manufacture method of the present invention, the device architecture that its step display (1), (2) form.

Fig. 5 is the schematic diagram two of manufacture method of the present invention, the device architecture that its step display (3) forms.

Fig. 6 is the schematic diagram three of manufacture method of the present invention, and the injection direction of p type impurity in step (4) is shown in its demonstration.

Fig. 7 is the schematic diagram four of manufacture method of the present invention, the device architecture that the injection of its step display (4) p type impurity forms afterwards.

Description of reference numerals

The 1st, P type substrate 2 is shallow-trench isolation

The 3rd, P trap 4 is silica dioxide medium layers

The 5th, silicon nitride hard mask layer 6 is thermal oxide layers

The 7th, isolation side walls 8 is compensating basins.

Embodiment

As shown in Figure 1 and Figure 2, nmos device of the present invention comprises:

P type substrate 1, shallow trench isolation from 2, P trap 3, silica dioxide medium layer 4, silicon nitride hard mask layer 5, thermal oxide layer 6, isolation side walls 7 and compensating basin 8, described shallow trench isolation from 2, thermal oxide layer 6, P trap 3 and compensating basin 8 be listed in P type substrate 1 top, described thermal oxide layer 6 and compensating basin 8 are between shallow-trench isolation 2 and P trap 3, described silica dioxide medium layer 4 is positioned at P trap 3 tops, it is adjacent with silica dioxide medium layer 4 that described isolation side walls 7 is positioned at 8 tops, compensating basin, and it is adjacent with isolation side walls 7 that described silicon nitride hard mask layer 5 is positioned at silica dioxide medium layer 4 top; Wherein, described thermal oxide layer 6 has p type impurity.

As shown in Figure 3, nmos device manufacture method of the present invention comprises:

(1) as shown in Figure 4, inject formation P trap 3 on P type substrate 1;

(2) growth silica dioxide medium layer 4, deposit silicon nitride hard mask layer 5, silicon nitride hard mask layer 5 is made etching shallow-trench isolation 2 as hard mask plate;

(3) as shown in Figure 5, growth thermal oxide layer 6;

(4) as Fig. 6, shown in Figure 7, thermal oxide layer 6 is carried out p type impurity inject;

(5) heat treatment, etching is made compensating basin 8;

(6) make isolation side walls 7, form device as shown in Figure 1 and Figure 2.

Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that do not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims

1. nmos device, comprise: P type substrate, shallow trench isolation are from, P trap, thermal oxide layer, silica dioxide medium layer, silicon nitride hard mask layer, isolation side walls and compensating basin, described shallow trench isolation is listed in P type substrate top from, thermal oxide layer, P trap and compensating basin, described thermal oxide layer and compensating basin are between shallow-trench isolation and P trap, described silica dioxide medium layer is positioned at above the P trap, it is adjacent with the silicon nitride medium layer that described isolation side walls is positioned at compensating basin top, and described silicon nitride hard mask layer is positioned at above the silica dioxide medium layer adjacent with isolation side walls; It is characterized in that: described thermal oxide layer has p type impurity.

2. nmos device as claimed in claim 1, it is characterized in that: described thermal oxide layer thickness is 100 dust to 300 dusts.

3. the manufacture method of a nmos device, is characterized in that, comprising:

(1) inject formation P trap on P type substrate;

(2) growth silica dioxide medium layer, the deposit hard mask layer is made the etching shallow-trench isolation;

(3) Heat of Formation oxide layer;

(4) thermal oxide layer being carried out p type impurity injects;

(5) heat treatment, etching is made the compensating basin;

(6) make isolation side walls.

4. nmos device manufacture method as claimed in claim 3, it is characterized in that: during implementation step (3), Heat of Formation pad oxide thickness is 100 dust to 300 dusts.

5. nmos device manufacture method as claimed in claim 3 is characterized in that: during implementation step (4), injecting p type impurity is boron or boron fluoride.

6. nmos device manufacture method as claimed in claim 3 is characterized in that: during implementation step (4), injecting p type impurity dosage is 1e13cm ^-2To 5e14cm ^-2, energy is 5keV to 50keV.