CN103187289A - Manufacturing method for multi-gate field effect transistor - Google Patents
Manufacturing method for multi-gate field effect transistor Download PDFInfo
- Publication number
- CN103187289A CN103187289A CN2011104580394A CN201110458039A CN103187289A CN 103187289 A CN103187289 A CN 103187289A CN 2011104580394 A CN2011104580394 A CN 2011104580394A CN 201110458039 A CN201110458039 A CN 201110458039A CN 103187289 A CN103187289 A CN 103187289A
- Authority
- CN
- China
- Prior art keywords
- sacrifice layer
- field effect
- effect transistor
- gate field
- fin structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a manufacturing method for a multi-gate field effect transistor. The manufacturing method for the multi-gate field effect transistor includes the following steps: a fin-shaped structure is formed on a substrate; a first sacrificial layer is formed; a welding pad structure is formed beside the fin-shaped structure of the first sacrificial layer; the first sacrificial layer is removed, and a second sacrificial layer covers the substrate; gates arranged on the top face and the side wall of the fin-shaped structure in a bridged mode are formed and connected with the welding pad structure at the same time; and the second sacrificial layer is removed According to the manufacturing method for the multi-gate field effect transistor, the first sacrificial layer and the second sacrificial layer are respectively used for defining the welding pad structure and the gates, requirements on window sizes are lowered, and the fin-shaped structure and the welding pad structure are protected when the gates are formed through an etching process and a filling process; and moreover, vertex angle regions in a source electrode region and a drain electrode region are protected from damage in the etching process, and therefore the fin-shaped structure with a good interface outline is formed, a pass-through effect is prevented from happening, and performance of the multi-gate field effect transistor is improved.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, relate in particular to a kind of manufacture method of multiple gate field effect transistor.
Background technology
Metal-oxide semiconductor fieldeffect transistor (MOSFET) is constantly to the trend development of minification in recent years, be in order to gather way, improve assembly integrated level and the cost that reduces integrated circuit, along with transistorized size reduces constantly, the transistorized limit that has reached the various performances of device of dwindling, wherein, the thickness of gate oxide and source/drain junction depth have all reached the limit.
Therefore, industry has been developed a plurality of grids or multi gate fet (Multi-Gate Transistors).Wherein, the multiple gate field effect transistor technology is a kind of novel circuit configuration technology, multiple gate field effect transistor is the device architecture among a kind of MOSFET that an above grid is incorporated into individual devices, this means, raceway groove is surrounded by several grids on a plurality of surfaces, thereby the leakage current in the time of can suppressing " ending " state more, and can strengthen drive current under " conducting " state, so just obtained the device architecture that lower power consumption and performance strengthen.Conventional transistor be each transistor have only grid be used for controlling electric current between two construction units by or interrupt, and then form calculate in required " 0 " and " 1 ".And the multiple-gate transistor technology is each transistor two or three grid are arranged, thereby improved the ability of transistor controls electric current, i.e. computing capability, and significantly reduced power consumption, reduced the phase mutual interference between electric current.
J.P. Colinge is called one piece of name in the Americana of " FinFETs and other Multi-Gate Transistors " and has introduced polytype multiple gate field effect transistor, comprise double-gated transistor (Double-Gate, FinFET), tri-gate transistors (Tri-Gate), ohm shape gate transistor (Ω-Gate) and quadrangle gate transistor (Quad-Gate) etc.Wherein, be example with the double-gated transistor, double-gated transistor has used two grids with the control raceway groove, has greatly suppressed short-channel effect.A concrete distortion of double-gated transistor is exactly fin transistor npn npn (FinFET), FinFET comprises vertical fin structure and across the grid in described fin structure side, both ends at the fin structure of grid both sides are respectively source electrode and drain electrode, form raceway groove in the fin structure under the grid.As nonplanar device, the size of the fin structure of FinFET has determined the length of effective channel of transistor device.FinFET compares compacter with the MOS transistor on conventional plane, can realize higher transistor density and littler whole microelectric technique.In addition, tri-gate transistors is another Common Shape of multiple-gate transistor, and wherein said grid to form three control raceway grooves, further improves the overall performance of device across side and top surface at described fin structure.
Fin structure, the interface profile of grid (Profile) has very big influence to the device performance of multiple gate field effect transistor, in the manufacture process that forms multiple gate field effect transistor, because formation fin structure and grid need carry out etching technics repeatedly, wherein especially dry etching is very big to the interface profile influence of fin structure and grid, the relatively poor grid of interface profile can influence the cut-in voltage of grid, the interface profile of fin structure can influence the size of its middle regional raceway groove, the vertical interface profile of fin structure is relatively poor even can cause the source area at its two ends and drain region to form punchthrough effect (Punch Trough), and, in the process of carrying out gate etch, can certain etching injury be arranged to fin structure, make the last dihedral of fin structure become the drift angle of certain circular arc degree, make the interface surface out-of-flatness of fin structure, thereby form wedge angle zone (Top Corner Area), in the subsequent technique, the metal of Xing Chenging is drawn and is produced the cavity between line and the fin structure thereon, cause metal to draw the line poor electrical contact, influence the performance of multiple gate field effect transistor.
Summary of the invention
The purpose of this invention is to provide a kind of manufacture method that reduces the multiple gate field effect transistor of fin structure and grid etch damage.
For addressing the above problem, the manufacture method of a kind of multiple gate field effect transistor of the present invention may further comprise the steps:
Substrate is provided, forms fin structure in described substrate;
Form first sacrifice layer at described fin structure and described substrate;
In the first other sacrifice layer of described fin structure, form welding pad structure;
Remove first sacrifice layer, and cover second sacrifice layer in described fin structure, welding pad structure and substrate;
In described second sacrifice layer, form to stride and be located at grid on fin structure end face and the sidewall and that link to each other with described welding pad structure;
Remove second sacrifice layer.
Further, in the first other sacrifice layer of described fin structure, form in the step of welding pad structure, may further comprise the steps: utilize photoetching and etching technics, in described first sacrifice layer, form first groove; The deposition bonding pad materials is filled described first groove; Carry out cmp, until exposing described fin structure, in first groove, to form welding pad structure.
Further, in described second sacrifice layer, form and stride in the step of being located at grid on fin structure end face and the sidewall and that link to each other with described welding pad structure, comprise: utilize photoetching and etching technics, in described second sacrifice layer, form second groove, described second groove exposes the zone line of described fin structure, and the described welding pad structure of expose portion; Deposition of gate material is filled described second groove; Carry out cmp, until exposing described second sacrifice layer, stride with formation and to be located at grid on fin structure end face and the sidewall and that link to each other with described welding pad structure.
Further, the material of described first sacrifice layer is the high silicon content polymer, and described first sacrifice layer adopts the method that applies to form, and adopts wet etching to remove.
Further, in the described high silicon content polymer molar content of silicon greater than 35%.
Further, the material of described first sacrifice layer is amorphous carbon, and described first sacrifice layer adopts chemical vapour deposition technique to form, and adopts the plasma ashing method to remove.
Further, the thickness of described first sacrifice layer is greater than the thickness of described fin structure, and thickness difference is 10～20nm.
Further, the material of described second sacrifice layer is the high silicon content polymer, and described second sacrifice layer adopts the method that applies to form, and adopts wet etching to remove.
Further, in the described high silicon content polymer molar content of silicon greater than 35%.
Further, the material of described second sacrifice layer is amorphous carbon, and described second sacrifice layer adopts chemical vapour deposition technique to form, and adopts the plasma ashing method to remove.
Further, the thickness of described second sacrifice layer is than the big 10～20nm of thickness of described fin structure.
Further, the material of described fin structure is monocrystalline silicon, germanium or silicon Germanium compound.
Further, the height of described fin structure is 30nm～100nm, and the width of described fin structure is 10nm～30nm.
Further, described grid is polysilicon gate or metal gates.
Further, the thickness of described grid is greater than the thickness of described welding pad structure.
Further, described substrate comprises silicon substrate and is positioned at and buries the oxygen insulating barrier on the silicon substrate.
In sum; multiple gate field effect transistor of the present invention is by utilizing first sacrifice layer and second sacrifice layer definition welding pad structure and grid; reduced the requirement of window size; simultaneously; when forming welding pad structure; first sacrifice layer blocks fin structure; protected fin structure; when forming grid; second sacrifice layer has blocked two end regions of fin structure, has avoided the etching injury of the top corner regions in source area and the drain region, thereby can form the good fin structure of interface profile and grid; reduce the generation of punchthrough effect, improved the performance of multiple gate field effect transistor.
In addition, because the material of first sacrifice layer and second sacrifice layer is selected high silicon content polymer or amorphous carbon material, can the using plasma ashing method in the removal process or wet etching remove, avoid adopting dry etching, reduced the damage to fin structure, welding pad structure and grid, thereby make said structure can form good interface profile and regular size, improved the performance of multiple gate field effect transistor.
Description of drawings
Fig. 1 is the schematic flow sheet of the manufacture method of multiple gate field effect transistor in one embodiment of the invention.
Fig. 2～Figure 12 is the cross-sectional view in the manufacture process of multiple gate field effect transistor in one embodiment of the invention.
Figure 13～Figure 14 is the vertical view in the manufacture process of multiple gate field effect transistor in one embodiment of the invention.
Figure 15 is the perspective view of multiple gate field effect transistor in one embodiment of the invention.
Embodiment
For making content of the present invention clear more understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
Fig. 1 is the schematic flow sheet of the manufacture method of multiple gate field effect transistor in one embodiment of the invention.As shown in Figure 1, the invention provides a kind of manufacture method of multiple gate field effect transistor, may further comprise the steps:
Step S01: substrate is provided, forms fin structure in described substrate;
Step S02: form first sacrifice layer at described fin structure and described substrate;
Step S03: in the first other sacrifice layer of described fin structure, form welding pad structure;
Step S04: remove first sacrifice layer, and cover second sacrifice layer in described fin structure, welding pad structure and substrate;
Step S05: in described second sacrifice layer, form to stride and be located at grid on fin structure end face and the sidewall and that link to each other with described welding pad structure;
Step S06: remove second sacrifice layer.
Fig. 2～Figure 12 is the cross-sectional view in the manufacture process of multiple gate field effect transistor in one embodiment of the invention.Figure 13～Figure 14 is the vertical view in the manufacture process of multiple gate field effect transistor in one embodiment of the invention.Figure 15 is the perspective view of multiple gate field effect transistor in one embodiment of the invention.Describe the manufacture method of multiple gate field effect transistor in detail below in conjunction with Fig. 2～Figure 15.
As shown in Figure 2, in step S01, provide substrate 100, form fin structure 103 in described substrate 100; In the present embodiment, described substrate 100 comprises silicon substrate 101 and is positioned at buries oxygen insulating barrier (BOX) 102 on the silicon substrate 101, form semiconductor layer (not indicating among the figure) at the described oxygen insulating barrier 102 that buries, the material of described semiconductor layer can be silicon, germanium or silicon Germanium compound etc., then, utilize the electron beam lithography process that described semiconductor layer is carried out photoetching and etching technics, the described semiconductor layer of patterning vertically stands on the described fin structure 103 that buries on the oxygen insulating barrier 102 to form.In follow-up technology, will form source area, drain region and channel region, source area and drain region are positioned at fin structure 103 both ends, and channel region is positioned at the middle part of fin structure 103, will form grid on the middle part sidewall of fin structure 103 and the top surface in addition.
As shown in Figure 2, the thickness H of fin structure 103
1Preferable scope is 30nm～100nm, the width W of described fin structure 103
1Preferable scope is 10nm～30nm.Fin structure 103 in the size range of above-mentioned height and width has good drive current performance, and can suppress short-channel effect and leakage current.
Then as shown in Figure 2, in step S02, form first sacrifice layer 105 at described fin structure 103 and described substrate 102; The thickness H of first sacrifice layer 105 in the substrate 102
2Thickness H than described fin structure 103
1Big 10nm～20nm is with the damage that is not etched of protection fin structure 103 in the subsequent technique process.In one embodiment, the material of described first sacrifice layer 105 is the high silicon content polymer, for example be the bottom antireflective coating of the fluidised form high silicon content that is easy to solidify, the method that can adopt rotation to apply is formed at described fin structure 103 and described substrate 102, solidify fixing afterwards, wherein the molar content of silicon is greater than 35% in the high silicon content polymer, and the polymer of high silicon content has and better solidifies character, and is easier to be removed in subsequent technique.In another embodiment; the material of described first sacrifice layer 105 is amorphous carbon; APF (Advanced Pattern Film) material for example; can adopt the mode of chemical vapour deposition (CVD) to form, amorphous carbon has certain mechanical strength, can resist follow-up chemical mechanical milling tech better; protect fin structure 103 better; and controlling dimension accurately, method that can plasma ashing in subsequent technique is removed, and can reduce the damage to fin structure 103.
In step S03, the fin structure 105 other formation welding pad structures 107 in described first sacrifice layer 105, and expose described fin structure 103.Concrete steps comprise: as shown in Figure 3, at first utilize photoetching and etching technics, form first bottom antireflective coating 201 and first photoresist layer 203 of patterning at described first sacrifice layer 105, be described first sacrifice layer 105 of mask etching with first bottom antireflective coating 201 and first photoresist layer 203 then, thereby in first sacrifice layer 105, form first groove 106 as shown in Figure 4, after the etching, remove remaining first photoresist layer 203 and first bottom antireflective coating 201; Then, as shown in Figure 5, deposition bonding pad materials 107a fills described first groove 106, and the material of welding pad structure 107a can be polysilicon or metal material, and is identical with the grid material of follow-up formation, for example copper; Then, carry out cmp, until exposing described fin structure 103, form structure as shown in Figure 6.
As shown in Figure 7, in step S04, remove remaining first sacrifice layer 105, cover second sacrifice layer 109 in described fin structure 103, welding pad structure 107 and substrate 100; First sacrifice layer 105 for the high silicon content polymer can adopt wet etching to remove; first sacrifice layer 105 for amorphous carbon can adopt the plasma ashing method to remove; above-mentioned two kinds of methods can both avoid using dry etching; reduce the etching injury of fin structure 103 and welding pad structure 107; the good interface profile of protection fin structure 103 and welding pad structure 107; avoid the etching injury of the top corner regions in source area and the drain region, improved the performance of multiple gate field effect transistor.
After removing described first sacrifice layer 105, at described substrate 102, fin structure 103 and welding pad structure 107 surface coverage second sacrifice layer 109, the thickness H of second sacrifice layer 109 in the substrate 102
3Thickness H than described fin structure 103
1Big 10nm～20nm, with in the subsequent technique process, the damage that is not etched of protection fin structure 103 and welding pad structure 107.In one embodiment, the material of second sacrifice layer 109 is the high silicon content polymer, the method that can adopt rotation to apply is solidified after being formed at described fin structure 103 and described substrate 102, wherein in the high silicon content polymer molar content of silicon greater than 35%, the polymer of high silicon content has and better solidifies character, and is easier to be removed in subsequent technique.In another embodiment, the material of described second sacrifice layer 109 is amorphous carbon, and for example APF (Advanced Pattern Film) material can adopt chemical vapour deposition technique to be formed in described fin structure 103 and the described substrate 102.
In step S05, in described second sacrifice layer 109, form to stride and be located at grid 111 on fin structure 103 end faces and the sidewall and that link to each other with described welding pad structure 107.Specifically may further comprise the steps: as shown in Figure 8, at first utilize photoetching and etching technics, form second bottom antireflective coating 205 and second photoresist 207 of patterning at described second sacrifice layer 109, be mask with described second bottom antireflective coating 205 and second photoresist 207, described second sacrifice layer 109 of etching, thereby in second sacrifice layer 109, form the second groove 109a as shown in Figure 9, in conjunction with shown in Figure 13, the described second groove 109a exposes the zone line of described fin structure 103, and the described welding pad structure 107 of expose portion; Then, as shown in figure 10, deposition of gate material 111a fills the described second groove 109a; Then, carry out cmp, until exposing described second sacrifice layer 109, thereby formation grid 111 as shown in figure 11, in conjunction with shown in Figure 14, described grid 111 is across on the described fin structure 103, and links to each other with described welding pad structure 107, and grid 111 can be polysilicon gate or metal gates.Wherein, the thickness H of described grid 111
4Thickness H greater than described welding pad structure 107
5, grid 111 is taken on Welding Structure 107.
In step S06, remove described second sacrifice layer 109, form structure as shown in figure 12.Second sacrifice layer 109 for the high silicon content polymer can adopt wet etching to remove; second sacrifice layer 109 for amorphous carbon can adopt the plasma ashing method to remove; above-mentioned two kinds of methods can both avoid using dry etching; reduce the etching injury to grid 111, fin structure 103 and welding pad structure 107; the good interface profile of protection grid 111, fin structure 103 and welding pad structure 107, and then the performance of raising multiple gate field effect transistor.The final structure that forms as shown in figure 15.
In sum; multiple gate field effect transistor of the present invention is by utilizing first sacrifice layer and second sacrifice layer definition welding pad structure and grid; reduced the requirement of window size; simultaneously; when forming welding pad structure; first sacrifice layer blocks fin structure; protected fin structure; when forming grid; second sacrifice layer has blocked two end regions of fin structure, has avoided the etching injury of the top corner regions in source area and the drain region, thereby can form the good fin structure of interface profile and grid; reduce the generation of punchthrough effect, improved the performance of multiple gate field effect transistor.
In addition, because the material of first sacrifice layer and second sacrifice layer is selected high silicon content polymer or amorphous carbon material, can the using plasma ashing method in the removal process or wet etching remove, avoid adopting dry etching, reduced the damage to fin structure, welding pad structure and grid, thereby make said structure can form good interface profile and regular size, improved the performance of multiple gate field effect transistor.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (16)
1. the manufacture method of a multiple gate field effect transistor is characterized in that, comprising:
Substrate is provided, forms fin structure in described substrate;
Form first sacrifice layer at described fin structure and described substrate;
In the first other sacrifice layer of described fin structure, form welding pad structure;
Remove first sacrifice layer, and cover second sacrifice layer in described fin structure, welding pad structure and substrate;
In described second sacrifice layer, form to stride and be located at grid on fin structure end face and the sidewall and that link to each other with described welding pad structure;
Remove second sacrifice layer.
2. the manufacture method of multiple gate field effect transistor as claimed in claim 1 is characterized in that, forms in the step of welding pad structure in the first other sacrifice layer of described fin structure, comprising:
Utilize photoetching and etching technics, in described first sacrifice layer, form first groove;
The deposition bonding pad materials is filled described first groove;
Carry out cmp, until exposing described fin structure, in first groove, to form welding pad structure.
3. the manufacture method of multiple gate field effect transistor as claimed in claim 1 is characterized in that, forms to stride in the step of being located at grid on fin structure end face and the sidewall and that link to each other with described welding pad structure in described second sacrifice layer, comprising:
Utilize photoetching and etching technics, form second groove in described second sacrifice layer, described second groove exposes the zone line of described fin structure, and the described welding pad structure of expose portion;
Deposition of gate material is filled described second groove;
Carry out cmp, until exposing described second sacrifice layer, stride with formation and to be located at grid on fin structure end face and the sidewall and that link to each other with described welding pad structure.
4. as the manufacture method of any described multiple gate field effect transistor in the claim 1 to 3, it is characterized in that, the material of described first sacrifice layer is the high silicon content polymer, and described first sacrifice layer adopts the method that applies to form, and described first sacrifice layer adopts wet etching to remove.
5. the manufacture method of multiple gate field effect transistor as claimed in claim 4 is characterized in that, the molar content of silicon is greater than 35% in the described high silicon content polymer.
6. as the manufacture method of any described multiple gate field effect transistor in the claim 1 to 3, it is characterized in that, the material of described first sacrifice layer is amorphous carbon, and described first sacrifice layer adopts chemical vapour deposition technique to form, and described first sacrifice layer adopts the plasma ashing method to remove.
7. as the manufacture method of any described multiple gate field effect transistor in the claim 1 to 3, it is characterized in that the thickness of described first sacrifice layer is greater than the thickness of described fin structure, thickness difference is 10～20nm.
8. as the manufacture method of any described multiple gate field effect transistor in the claim 1 to 3, it is characterized in that, the material of described second sacrifice layer is the high silicon content polymer, and described second sacrifice layer adopts the method that applies to form, and described second sacrifice layer adopts wet etching to remove.
9. the manufacture method of multiple gate field effect transistor as claimed in claim 8 is characterized in that, the molar content of silicon is greater than 35% in the described high silicon content polymer.
10. as the manufacture method of any described multiple gate field effect transistor in the claim 1 to 3, it is characterized in that, the material of described second sacrifice layer is amorphous carbon, and described second sacrifice layer adopts chemical vapour deposition technique to form, and described second sacrifice layer adopts the plasma ashing method to remove.
11. the manufacture method as any described multiple gate field effect transistor in the claim 1 to 3 is characterized in that, the thickness of described second sacrifice layer is greater than the thickness of described fin structure, and thickness difference is 10～20nm.
12. the manufacture method as any described multiple gate field effect transistor in the claim 1 to 3 is characterized in that, the material of described fin structure is monocrystalline silicon, germanium or silicon Germanium compound.
13. the manufacture method as any described multiple gate field effect transistor in the claim 1 to 3 is characterized in that, the height of described fin structure is 30nm～100nm, and the width of described fin structure is 10nm～30nm.
14. the manufacture method as any described multiple gate field effect transistor in the claim 1 to 3 is characterized in that, described grid is polysilicon gate or metal gates.
15. the manufacture method as any described multiple gate field effect transistor in the claim 1 to 3 is characterized in that the thickness of described grid is greater than the thickness of described welding pad structure.
16. the manufacture method as any described multiple gate field effect transistor in the claim 1 to 3 is characterized in that, described substrate comprises silicon substrate and is positioned at buries the oxygen insulating barrier on the silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110458039.4A CN103187289B (en) | 2011-12-31 | 2011-12-31 | The manufacture method of multiple gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110458039.4A CN103187289B (en) | 2011-12-31 | 2011-12-31 | The manufacture method of multiple gate field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103187289A true CN103187289A (en) | 2013-07-03 |
| CN103187289B CN103187289B (en) | 2015-08-19 |
Family
ID=48678395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110458039.4A Active CN103187289B (en) | 2011-12-31 | 2011-12-31 | The manufacture method of multiple gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103187289B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576392A (en) * | 2013-10-18 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing finned field-effect transistor |
| CN104979202A (en) * | 2014-04-04 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Formation method of transistor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
| US7795669B2 (en) * | 2007-05-30 | 2010-09-14 | Infineon Technologies Ag | Contact structure for FinFET device |
| CN101939830A (en) * | 2008-02-11 | 2011-01-05 | Nxp股份有限公司 | Finfet with separate gates and method for fabricating a FinFET with separate gates |
| CN102074506A (en) * | 2009-11-19 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Method for fabricating fin-like field effect transistor |
| CN102129982A (en) * | 2010-12-29 | 2011-07-20 | 北京大学深圳研究生院 | Manufacturing method of fine pattern of semiconductor and FIN body of fin type field effect transistor |
-
2011
- 2011-12-31 CN CN201110458039.4A patent/CN103187289B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
| US7795669B2 (en) * | 2007-05-30 | 2010-09-14 | Infineon Technologies Ag | Contact structure for FinFET device |
| CN101939830A (en) * | 2008-02-11 | 2011-01-05 | Nxp股份有限公司 | Finfet with separate gates and method for fabricating a FinFET with separate gates |
| CN102074506A (en) * | 2009-11-19 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Method for fabricating fin-like field effect transistor |
| CN102129982A (en) * | 2010-12-29 | 2011-07-20 | 北京大学深圳研究生院 | Manufacturing method of fine pattern of semiconductor and FIN body of fin type field effect transistor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576392A (en) * | 2013-10-18 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing finned field-effect transistor |
| CN104979202A (en) * | 2014-04-04 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Formation method of transistor |
| CN104979202B (en) * | 2014-04-04 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103187289B (en) | 2015-08-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101633225B1 (en) | FIN STRUCTURE FOR A FinFET DEVICE | |
| US11251183B2 (en) | Semiconductor arrangement having continuous spacers and method of manufacturing the same | |
| US7285456B2 (en) | Method of fabricating a fin field effect transistor having a plurality of protruding channels | |
| US9461150B2 (en) | Method for fabricating semiconductor device with fin-shaped structure | |
| CN105470295B (en) | Fin structure and manufacturing method thereof | |
| US9263287B2 (en) | Method of forming fin-shaped structure | |
| US20170005102A1 (en) | Semiconductor device and method for fabricating the same | |
| US9076870B2 (en) | Method for forming fin-shaped structure | |
| US10832972B2 (en) | Semiconductor arrangement having continuous spacers and method of manufacturing the same | |
| US9378973B1 (en) | Method of using sidewall image transfer process to form fin-shaped structures | |
| US10043675B2 (en) | Semiconductor device and method for fabricating the same | |
| CN106409748B (en) | Semiconductor element and manufacturing method thereof | |
| CN108807179B (en) | Semiconductor structure and forming method thereof | |
| CN103187289B (en) | The manufacture method of multiple gate field effect transistor | |
| CN103378005A (en) | Method for manufacturing fin-shaped structures of multi-gate field effect transistor | |
| CN107546127B (en) | Semiconductor element and manufacturing method thereof | |
| CN111370488A (en) | Semiconductor structure and forming method thereof | |
| CN103632978A (en) | Formation method for semiconductor structure | |
| CN108630752B (en) | Semiconductor structure and forming method thereof | |
| CN113838934A (en) | Semiconductor structure and forming method thereof | |
| CN105448968B (en) | Method for manufacturing fin field effect transistor | |
| CN103021857B (en) | The manufacture method of multiple gate field effect transistor | |
| CN111383994A (en) | Semiconductor structure and forming method thereof | |
| CN115084240A (en) | Semiconductor structure and forming method thereof | |
| CN103137671B (en) | Multi-grid field effect transistor and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |