CN103295509B - Shift registor and display device - Google Patents
Shift registor and display device Download PDFInfo
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- CN103295509B CN103295509B CN201210043408.8A CN201210043408A CN103295509B CN 103295509 B CN103295509 B CN 103295509B CN 201210043408 A CN201210043408 A CN 201210043408A CN 103295509 B CN103295509 B CN 103295509B
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Abstract
One of a kind of wherein one-level shift register module of shift registor is drawn high unit and and is drawn high gate node and an output node is electrically connected, and the start according to one first clock signal and the voltage drawing high gate node.Draw high control module and draw high gate node and be electrically connected with output node, and the start according to a reset signal and a coupled signal, the one first limit voltage compensating unit drawing high control module connects reset signal and coupled signal, and with draw high gate node and be electrically connected.Drag down control module and draw high control module and be electrically connected, and the start according to reset signal, coupled signal and a second clock signal.Drag down unit and draw high unit and be electrically connected, and drag down gate node via one and drag down control module and be electrically connected.
Description
Technical field
The invention relates to a kind of shift registor and display device.
Background technology
Flat display apparatus, due to advantages such as it is frivolous, low power consumptions, has been widely used on the products such as communication, information and consumer electronics.Generally speaking, flat display apparatus comprises a display panel, scan driving circuit and a data drive circuit.Wherein scan drive circuit has a shift registor, and it transmits scanning drive signal, sequentially to drive the multi-strip scanning line be electrically connected with shift register module.
Figure 1A and Figure 1B is the circuit of shift registor and the schematic diagram of signal thereof of existing single kenel (for N-type) thin film transistor (TFT) respectively.Can find that grid (nodes X ') voltage of transistor T5 ' is respectively VGH-Vt_ in operational phase I and II from Figure 1A
t1and 2*VGH-VGL-Vt_
t1.Wherein, Vt_
t1for the critical voltage value (thresholdvoltage) of transistor T1 ', that is the grid voltage of transistor T5 ' is relevant to the Vt value of transistor T1 '.Therefore, long-time operation causes transistor threshold voltage value Vt rising that the transistor switch remarkable action of available circuit may be caused to cause circuit malfunction.
In addition, the drain current path that the grid (nodes X ') of the transistor T5 ' of available circuit is possible (is present in transistor T4 ' and transistor T1 ') as shown in Figure 1A, and the large young pathbreaker of the leakage current of transistor unit affects nodes X voltage.Fig. 2 is transistor unit (for N-type) (V under different Drain-Source bias voltage
dS=0.5, V
dS=10) drain-source current flow (I
dS) and gate-source bias (V
gS) curve map.Can find, identical V
gSin situation, V
dSthe leakage current of larger then transistor unit is also larger.And operational phase II can be found in by the signal graph of Figure 1B, the V of transistor T1 ' and T4 '
dSbe 2* (VGH-VGL)-Vt_
t1.If with VGH=15V, VGL=-5V, Vt_
t1=5V substitutes into calculating, this V
dSbe equivalent to 35V, real symbolic animal of the birth year is when high value.Its leakage current may cause under this operating conditions the nodes X of available circuit ' current potential cannot keep and make transistor T5 ' cannot normally export a high levle in operational phase II.
Summary of the invention
Because above-mentioned problem, object of the present invention can solve existing issue for providing a kind of and promotes shift registor and the display device of usefulness.
For reaching above-mentioned purpose, according to a kind of shift registor of the present invention, there is stages shift temporary storage module and being connected in series.One of them grade of shift register module comprises to be drawn high unit, and draws high control module, and drag down control module and and drag down unit.Draw high unit and and draw high gate node and an output node is electrically connected, and the start according to one first clock signal (clocksignal) and the voltage drawing high gate node.Draw high control module and draw high gate node and be electrically connected with output node, and the start according to a reset signal and a coupled signal, the one first limit voltage compensating unit drawing high control module connects reset signal and coupled signal, and with draw high gate node and be electrically connected.Drag down control module and draw high control module and be electrically connected, and the start according to reset signal, coupled signal and a second clock signal.Drag down unit and draw high unit and be electrically connected, and drag down gate node via one and drag down control module and be electrically connected.
In one embodiment, the first limit voltage compensating unit comprises one first compensation transistor, a first transistor and one first building-out capacitor.One first end of one first end of the first compensation transistor, a first end of the first building-out capacitor and the first transistor and a gate terminal are via one first common node electrical connection.One gate terminal of the first compensation transistor connects reset signal, one second end butt coupling signal of the first building-out capacitor.One second end of the first transistor with draw high gate node and be electrically connected.
In one embodiment, the second end of the first transistor is electrically connected with one the 4th transistor via drawing high gate node.One gate terminal of the 4th transistor with drag down gate node and be electrically connected.One first end of the 4th transistor with draw high gate node and be electrically connected.
In one embodiment, draw high control module and more comprise bias voltage reduction unit (biasreducingunit), it is electrically connected with output node and the first common node, and is electrically connected with one second end of the 4th transistor via a node.
In one embodiment, draw high unit and comprise one the 5th transistor, a gate terminal of the 5th transistor with draw high gate node and be electrically connected, a first end of the 5th transistor connects this first clock signal, and one second end of the 5th transistor is electrically connected with output node.
In one embodiment, the high levle of reset signal shifts to an earlier date high levle one phase differential of coupled signal.
In one embodiment, drag down control module and have one second limit voltage compensating unit, the second limit voltage compensating unit connects reset signal and second clock signal, and via dragging down gate node and dragging down unit and be electrically connected.
In one embodiment, the second limit voltage compensating unit comprises one second compensation transistor, a third transistor and one second building-out capacitor.One first end of one first end of the second compensation transistor, a first end of the second building-out capacitor and third transistor and a gate terminal are via one second common node electrical connection.One gate terminal of the second compensation transistor connects reset signal, and one second end of the second building-out capacitor connects second clock signal.One second end of third transistor with drag down gate node and be electrically connected.
In one embodiment, drag down unit and comprise one the 6th transistor, a gate terminal of the 6th transistor with drag down gate node and be electrically connected, a first end of the 6th transistor is electrically connected with output node.
In one embodiment, shift register module one before secondary move that temporary storage module exports one draw high the voltage of gate node as reset signal.
In one embodiment, coupled signal moves an output node of temporary storage module from previous stage.
For reaching above-mentioned purpose, comprise a display panel, data scanning driving circuit and a scan driving circuit according to a kind of display device of the present invention.Wherein, scan drive circuit has above-mentioned shift registor.
From the above, in shift registor of the present invention, the control module of drawing high of one of them grade of shift register module comprises one first limit voltage compensating unit, its can for the compensation of drawing high transistor that unit is connected and do a limit voltage, make it during a certain specific operation, transmit high levle (VGH) voltage do not affected by limit voltage to drawing high unit.By this, the present invention can avoid long-time operation to cause transistor threshold voltage value raise and cause transistor switch remarkable action and circuit malfunction, and then promotes and overall efficiency.
Accompanying drawing explanation
Figure 1A and Figure 1B is the circuit of existing shift registor and the schematic diagram of signal thereof respectively;
Fig. 2 is the drain-source current flow of transistor unit under different Drain-Source bias voltage and the curve map of gate-source bias;
Fig. 3 A is the block schematic diagram of the wherein one-level shift register module of a shift registor of present pre-ferred embodiments;
Fig. 3 B is the circuit diagram that one of the shift register module of Fig. 3 A implements aspect;
Fig. 4 is the signal schematic representation of the shift register module of Fig. 3 B;
Fig. 5 shows level and the relation of each signal in Fig. 4;
Fig. 6 is the switch list of each transistor in the shift register module shown in Fig. 3 B is during each operation;
Fig. 7 is the current potential table of each node in the shift register module shown in Fig. 3 B is during each operation;
Fig. 8 shows shift register module shown in Fig. 3 B possible drain current path A, B;
Fig. 9 is the configuration diagram of a kind of shift registor of present pre-ferred embodiments;
Figure 10 is the signal schematic representation of the shift registor shown in Fig. 9;
Figure 11 is the configuration diagram of the shift registor of another change aspect of the present invention;
Figure 12 is the signal schematic representation of the shift registor shown in Figure 11;
Figure 13 is the configuration diagram of the shift registor of another change aspect of the present invention;
Figure 14 is the signal schematic representation of the shift registor shown in Figure 13;
Figure 15 A is the block schematic diagram of the wherein one-level shift register module of a shift registor of another change aspect of the present invention;
The circuit diagram of the enforcement aspect that Figure 15 B is the shift register module shown in Figure 15 A; And
Shift register module shown in Figure 16 A and the shift register module shown in Figure 16 B are respectively a change aspect of Fig. 3 A and the shift register module shown in Figure 15 A.
Drawing reference numeral:
1,1a, 1b, 1c: shift register module
11: draw high unit
12: draw high control module
121: the first limit voltage compensating units
122: bias voltage reduces unit
13: drag down control module
131: the second limit voltage compensating units
14: drag down unit
A: the first common node
B: the second common node
C, X ', Y ': node
CK2: the first clock signal
CK3: second clock signal
C1, C2, Cvt1, Cvt2: electric capacity
INI: initialize signal
RST, RST-1, RST-2: reset signal
T0: phase differential
T1 ' ~ T6 ', T1 ~ T8, Tc1, Tc2, Tr1 ~ Tr3, T_ini: transistor
S (n): coupled signal
S (n+1): output node
SR1, SR2, SR3: shift registor
VGH: high levle
VGL: low level
VREF, VREF2: with reference to level
VST: signal is initiated in scanning
X: draw high gate node
Y: drag down gate node
Embodiment
Hereinafter with reference to correlative type, a kind of shift registor according to present pre-ferred embodiments and display device are described, wherein identical element is illustrated with identical reference marks.
Fig. 3 A is the block schematic diagram of the wherein one-level shift register module 1 of a shift registor of present pre-ferred embodiments, and Fig. 3 B is the circuit diagram that one of this shift register module 1 implements aspect.
Shift register module 1 comprises to be drawn high unit 11, and draws high control module 12, and drag down control module 13 and and drag down unit 14.
Draw high unit 11 and and draw high gate node X and an output node S (n+1) (n is the integer of >=0) is electrically connected, and the start according to one first clock signal C K2 and the voltage drawing high gate node X.
Draw high control module 12 and draw high gate node X and be electrically connected with output node S (n+1), and the start according to a reset signal RST and coupled signal S (n).In this, coupled signal S (n) is output node S (n) moving temporary storage module from previous stage; In other embodiments, coupled signal also can copy from system the signal exported by output node S (n).Draw high control module 12 there is one first limit voltage compensating unit 121, first limit voltage compensating unit 121 to connect reset signal RST and coupled signal, and with draw high gate node X and be electrically connected.
Drag down control module 13 and draw high control module 11 and be electrically connected, and the start according to reset signal RST, coupled signal and a second clock signal CK3.
Drag down unit 14 and draw high unit 11 and be electrically connected, and drag down gate node Y via one and drag down control module 13 and be electrically connected.
Below describe in detail and draw high unit 11, draw high control module 12, drag down control module 13 and drag down unit 14.
Draw high unit 11 and comprise one the 5th transistor T5, one gate terminal of the 5th transistor T5 with draw high gate node X and be electrically connected, one first end of the 5th transistor T5 connects the first clock signal C K2, one second end of the 5th transistor T5 is electrically connected to export a drive singal with output node S (n+1), and drive singal can such as the sweep signal of display panel.
First limit voltage compensating unit 121 comprises one first compensation transistor Tc1, a first transistor T1 and one first building-out capacitor Cvt1.One first end of the first compensation transistor Tc1, a first end of the first building-out capacitor Cvt1 and a first end of the first transistor T1 and one gate terminal are electrically connected via one first common node a.One gate terminal of the first compensation transistor Tc1 connects reset signal RST, and one second end of the first compensation transistor Tc1 connects one with reference to level VREF.One second end butt coupling signal S (n) of the first building-out capacitor Cvt1.In this, the first building-out capacitor Cvt1 is as the use of coupling capacitance.One second end of the first transistor T1 with draw high gate node X and be electrically connected, and control the grid drawing high unit 11.
In addition, second end of the first transistor T1 is electrically connected with one the 4th transistor T4 via drawing high gate node X.One gate terminal of the 4th transistor T4 with drag down gate node Y and be electrically connected, a first end of the 4th transistor with draw high gate node X and be electrically connected, one second end of the 4th transistor is connected with a node c.
In addition, draw high control module 12 and more comprise bias voltage reduction unit (biasreducingunit) 122, it is electrically connected with output node S (n+1) and the first common node a, and is electrically connected with one second end of the 4th transistor T4 via node c.Bias voltage reduces unit 122 and comprises transistor Tr1, Tr2, Tr3.Wherein, transistor Tr1, Tr3 grid separately, drain electrode mutual connection form a diodeconnection, and are connected to output node S (n+1).The source electrode of transistor Tr1 and the drain electrode of transistor Tr2 are connected to node c.The source electrode of transistor Tr2 is connected to a low level VGL, and its grid is connected to and drags down gate node Y.The source electrode of transistor Tr3 is connected to the first common node a.Bias voltage reduces unit 122 can during output node S (n+1) exports the operation of high levle signal in (operationperiod), reduce the node voltage drawn high on the drain current path of gate node X poor and suppress leakage current, and then promoting the usefulness of displacement working storage; Can further illustrate below this advantage.
Drag down control module 13 and there is one second limit voltage compensating unit 131.Second limit voltage compensating unit 131 connects reset signal RST and second clock signal CK3, and via dragging down gate node Y and dragging down unit 14 and be electrically connected.Second limit voltage compensating unit 131 comprises one second compensation transistor Tc2, a third transistor T3 and one second building-out capacitor Cvt2.One first end (drain electrode) and the one gate terminal of one first end (drain electrode) of the second compensation transistor Tc2, a first end of the second building-out capacitor Cvt2 and third transistor T3 are electrically connected via one second common node b.In this, the second building-out capacitor Cvt2 is the use as coupling capacitance.One gate terminal of the second compensation transistor Tc2 connects reset signal RST, and one second end (source electrode) connects one with reference to level VREF.One second end of the second building-out capacitor Cvt2 connects second clock signal CK3.One second end (source electrode) of third transistor T3 with drag down gate node Y and be electrically connected, and control grid and transistor T4, Tr2 of dragging down unit 14.
Drag down unit 14 and comprise one the 6th transistor T6.One gate terminal of the 6th transistor T6 with drag down gate node Y and be electrically connected, a first end (drain electrode) of the 6th transistor T6 is electrically connected with output node S (n+1), and one second end (source electrode) connects a low level VGL.
In addition, the grid of transistor T2, T7 controls by coupled signal S (n) and output node signal S (n+1) respectively.The grid of transistor T8 is connected to the second common node b, and the connection of one first end drags down gate node Y, and one second end connects one with reference to level VREF.In other embodiments, transistor T8 can omit, and its function can be replaced by transistor T3.One first end of electric capacity C1 is connected to draws high gate node X, and one second end is connected to output node S (n+1).One first end of electric capacity C2 is connected to and drags down gate node Y, and one second end is connected to a low level VGL.Electric capacity C1, C2 are storage unit, except suppressing effect of leakage, also can reduce noise.In other embodiments, electric capacity C1 can omit, and second end of electric capacity C2 can be connected to other an any direct current (DC) voltage.
More than illustrate it is for N-type transistor, as long as but level appropriately adjust and be also applicable to P-type transistor.
Fig. 4 is the signal schematic representation of the shift register module 1 of Fig. 3 B, wherein, ts represents the sweep trace opening time, and ta >=0 represents the interval that clock signal C K2 and CK3 is adjacent, and t0 represents an interval of the high levle of reset signal RST and the high levle of coupled signal S (n).In this, the high levle of reset signal RST shifts to an earlier date the high levle one phase differential t0 of coupled signal S (n), and preferably is phase differential t0 >=ts.Fig. 5 shows level and the relation of each signal of Fig. 4.Wherein, the high levle for making the first limit voltage compensating unit 121 can reset reference level VREF, a reset signal RST need be greater than VREF level.Fig. 6 is the switch list of each transistor in the shift register module 1 shown in Fig. 3 B is during each operation.Fig. 7 is the current potential table of each node in the shift register module 1 shown in Fig. 3 B is during each operation.Below please refer to Fig. 3 B to Fig. 7 so that the start situation of shift register module 1 during each operation to be described.
Operation period Rst
Reset signal RST is a high levle and is greater than the high levle with reference to level VREF, so transistor Tc1, Tc2, T1, T3, T8 are for opening (ON).First common node a and the second common node b will be reset to a high levle VREF.The level dragging down gate node Y is reset to a level VREF-Vt_
t8(Vt_
t8critical voltage value for transistor T8), its value is greater than VGL+Vt_
t6(Vt_
t6critical voltage value for transistor T6), so transistor T6 is ON and exports a low level VGL to output node S (n+1).Transistor Tr2, T4 are also ON.Draw high gate node X voltage to be now reset to a level between VGL ~ VREF-Vt_
t1.In design, the level that usually can make to draw high gate node X is VGL as far as possible during this, and makes transistor T5 be OFF (transistor Tr2, T4, T1 can be made to have a suitable transistor breadth length ratio reach).If but the level of nodes X during this makes transistor T5 be ON, then the signal of clock signal C K2 is VGL, therefore can't causes with the output of transistor T6 and conflict.
Operation period A
Reset signal RST is low level VGL, and therefore transistor Tc1, Tc2 is OFF.Second common node b is still high levle VREF, so transistor T8 is ON, and makes the level dragging down gate node Y be still VREF-Vt_
t8, so transistor T6 is ON, and export a low level VGL to output node S (n+1).Transistor Tr2, T4 are also ON, and drawing high gate node X voltage is now a low level VGL, so transistor T5 is OFF.And the current potential of the first common node a will be discharged to level through transistor T1 is VGL+Vth_
t1(Vt_
t1critical voltage value for transistor T1), and now transistor T1 is OFF.
Operation period B
Coupled signal S (n) is a high levle VGH, makes transistor T2 be ON and transmits a low level VGL to node Y, so transistor Tr2, T4, T6 are OFF.Node a will be coupled (coupling) to VGH+Vth_ by electric capacity Cvt1
t1, and be sent to nodes X through transistor T1 and make its level be VGH, make transistor T5 be ON and the low level VGL to output node S (n+1) of transmission clock signal CK2.And the current potential of node b is discharged to level through transistor T3 is VGL+Vth_
t3(Vt_
t3critical voltage value for transistor T3), and transistor T3 is now OFF.Therefore transistor T8 is OFF.
Operation period C
First clock signal C K2 is a high levle VGH, and nodes X will be coupled to VGH*2-VGL, so transistor T5 is ON and transmits high levle VGH to output node S (n+1).So transistor T7 is ON and is sent to level VGL to node Y, so that transistor T6, Tr2, T4 are OFF.And transistor Tr3, Tr1 are ON and transmit VGH-Vt_ respectively
tr3(Vt_
tr3critical voltage value for transistor Tr3) and VGH-Vt_
tr1(Vt_
tr1critical voltage value for transistor Tr1) to node a and c.Node b is still VGL+Vth_
t3, and make transistor T8OFF.
Operation period D
Second clock signal CK3 is that the level of a high levle VGH, node b will be coupled to VGH+Vth_
t3.So transistor T8 is ON, the level of node Y is VGH+Vth_
t3-Vth_
t8, suppose Vth_
t3=Vth_
t8, then the level of node Y is VGH.So transistor T6 is ON and exports a low level VGL to output node S (n+1).And transistor Tr2, T4 are also ON, nodes X voltage is now a low level VGL, makes transistor T5 be OFF.Now node a will be discharged to VGL+Vt_
t1.
Operation period E
Second clock signal CK3 is that the level of a low level VGL, node b will be coupled to VGL+Vth_
t3, make transistor T8 be OFF, but the level of node Y is still held in high levle VGH by electric capacity C2, so transistor T6 is ON and exports a low level VGL to node S (n+1).Due to the high levle VGH of node Y, transistor Tr2, T4 are also ON, and nodes X voltage is now a low level VGL, make transistor T5 be OFF.Now node a is still VGL+Vt_
t1.
Because transistor T1, T3 need conducting one high levle (High) during operation, therefore the present embodiment can do a limit voltage for this transistor T1, T3 by the first limit voltage compensating unit 121 and the second limit voltage compensating unit 131 compensates, can respectively during operation B and D transmit a high levle (VGH) to draw high unit 11 and drag down unit 14 gate terminal and by the impact that limit voltage own drifts about.In other embodiments, compensating unit 121,131 also can only for transistor T1 and T3 one of them or in drawing high control module 12, drag down in control module 13 select more transistor and arrange in pairs or groups one suitable time ordered pair its compensate, this looks closely the situation of transistor limit voltage drift in control module.The circuit of the present embodiment is compensated for as a preferred embodiment to do limit voltage to transistor T1 and T3.
In addition, the bias voltage reduction unit 122 of the present embodiment is arranged to be drawn high on gate node X possible drain current path A, B, as shown in Figure 8.Utilizing bias voltage to reduce unit 122 can in time operating period C, and reducing nodes X node voltage difference on leakage path A, B (as nodes X and the voltage difference of node c and the voltage difference of nodes X and node a) may suppress leakage current.In other embodiments, bias voltage reduce unit 122 can only selecting paths A or B one of them do drain current suppressing, the circuit of the present embodiment is to carry out bias voltage reduction to path A and B.
Fig. 9 is the configuration diagram of a kind of shift registor SR1 of present pre-ferred embodiments, and it such as can be applied to scan driving circuit.Figure 10 is the signal schematic representation of shift registor SR1.Shift registor SR1 comprises stages shift temporary storage module and is connected in series, and one of them grade of shift register module has the technical characteristic as shift register module 1.In addition, wherein one-level shift register module one before secondary move the reset signal RST of voltage as this grade of shift register module that one of temporary storage module draws high gate node X.In this, the voltage drawing high gate node X of first order shift register module is as the reset signal RST of third level shift register module, the voltage drawing high gate node X of second level shift register module as the reset signal RST of fourth stage shift register module, and all the other by that analogy.In addition, first order shift register model calling one reset signal RST-1 is using as its reset signal RST, and second level shift register model calling one reset signal RST-2 is using as its reset signal RST.In addition, the signal of the output node of first order shift register module is as the coupled signal of second level shift register module, and all the other by that analogy.First order shift register model calling one scan initiates signal VST as its coupled signal.
The shift registor of the present embodiment can have multiple change aspect, below illustrates it.
Figure 11 is the configuration diagram of the shift registor SR2 of another change aspect of the present invention, and Figure 12 is the signal schematic representation of shift registor SR2.In this, the first order and the same reset signal RST of second level shift register model calling.
Figure 13 is the configuration diagram of the shift registor SR3 of another change aspect of the present invention, and Figure 14 is the signal schematic representation of shift registor SR3.In this, the same reset signal RST of all shift register model calling.
Figure 15 A is the block schematic diagram of the wherein one-level shift register module 1a of a shift registor of another change aspect of the present invention, and Figure 15 B is the circuit diagram that one of this shift register module 1a implements aspect.Be with shift register module 1 main difference shown in Fig. 3 A and Fig. 3 B, the control module 13 that drags down of shift register module 1a does not have the second limit voltage compensating unit, and only draws high control module 12 and have the first limit voltage compensating unit 121.The signal of shift register module 1a can refer to Fig. 4, repeats no more in this.
Shift register module 1b shown in Figure 16 A and the shift register module 1c shown in Figure 16 B is respectively a change aspect of Fig. 3 A and the shift register module shown in Figure 15 A.Be with the shift register module main difference shown in Fig. 3 A and Figure 15 A, shift register module 1b, 1c connect an initial transistor T_ini, its grid connects an initialize signal INI, and the connection of one first end drags down gate node Y, and one second end connects one with reference to level VREF2.Initialize signal INI initiates and transmits a reference level VREF2 to node Y when panel starts and before other control signals are as VST, RST, CK1 ~ CK4.Arbitrary direct voltage source or an alternating-current voltage source can be used, as long as the level transmitted during being identified in this is a high levle VGH with reference to level VREF2.Its object makes the current potential of node Y be a high levle and is exporting a low level to node S (n+1).
The shift registor of arbitrary aspect as above can be applicable to a display device, and this display device comprises a display panel, data scanning driving circuit and a scan driving circuit.Wherein, scan drive circuit has above-mentioned shift registor.
In sum, in shift registor of the present invention, the control module of drawing high of one of them grade of shift register module comprises one first limit voltage compensating unit, its can for the compensation of drawing high transistor that unit is connected and do a limit voltage, make it during a certain specific operation, transmit high levle (VGH) voltage do not affected by limit voltage to drawing high unit.By this, the present invention can avoid long-time operation to cause transistor threshold voltage value to raise so that transistor switch remarkable action and circuit malfunction, and then promotes and overall efficiency.
The foregoing is only illustrative, but not be restricted.Anyly do not depart from spirit of the present invention and category, and to its equivalent modifications of carrying out or change, all should be contained in claim.
Claims (16)
1. a shift registor, has stages shift temporary storage module and is connected in series, it is characterized in that, one of them grade of described shift register module comprises:
One draws high unit, draws high gate node and an output node is electrically connected with one, and according to one first clock signal and described in draw high the voltage of gate node and start;
One draws high control module, be electrically connected with described output node with described gate node of drawing high, and the start according to a reset signal and a coupled signal, described control module of drawing high has one first limit voltage compensating unit, described first limit voltage compensating unit connects described reset signal and described coupled signal, and is electrically connected with described gate node of drawing high;
One drags down control module, is electrically connected with described control module of drawing high, and the start according to described reset signal, described coupled signal and a second clock signal; And
One drags down unit, is electrically connected with described unit of drawing high, and drags down gate node via one and be electrically connected with the described control module that drags down;
Wherein, described first limit voltage compensating unit comprises one first compensation transistor, one the first transistor and one first building-out capacitor, one first end of described first compensation transistor, one first end of described first building-out capacitor and a first end of described the first transistor and a gate terminal are via one first common node electrical connection, one gate terminal of described first compensation transistor connects described reset signal, one second end of described first building-out capacitor connects described coupled signal, one second end of described the first transistor is electrically connected with described gate node of drawing high, one second end of described first compensation transistor connects one with reference to level.
2. shift registor as claimed in claim 1, it is characterized in that, described second end of described the first transistor is electrically connected with one the 4th transistor via described gate node of drawing high, one gate terminal of described 4th transistor is electrically connected with the described gate node that drags down, one first end of described 4th transistor is electrically connected with described gate node of drawing high
Wherein, described in draw high control module more comprise one bias voltage reduce unit, it is electrically connected with described output node and described first common node, and is electrically connected via one second end of a node with described 4th transistor.
3. shift registor as claimed in claim 1, it is characterized in that, described unit of drawing high comprises one the 5th transistor, one gate terminal of described 5th transistor is electrically connected with described gate node of drawing high, one first end of described 5th transistor connects described first clock signal, and one second end of described 5th transistor is electrically connected with described output node.
4. shift registor as claimed in claim 1, it is characterized in that, the described control module that drags down has one second limit voltage compensating unit, described second limit voltage compensating unit connects described reset signal and described second clock signal, and is electrically connected with the described unit that drags down via the described gate node that drags down.
5. shift registor as claimed in claim 4, it is characterized in that, described second limit voltage compensating unit comprises one second compensation transistor, one third transistor and one second building-out capacitor, one first end of described second compensation transistor, one first end of described second building-out capacitor and a first end of described third transistor and a gate terminal are via one second common node electrical connection, one gate terminal of described second compensation transistor connects described reset signal, one second end of described second building-out capacitor connects described second clock signal, one second end of described third transistor is electrically connected with the described gate node that drags down, one second end of described second compensation transistor connects described with reference to level.
6. shift registor as claimed in claim 1, it is characterized in that, the described unit that drags down comprises one the 6th transistor, one gate terminal of described 6th transistor is electrically connected with the described gate node that drags down, one first end of described 6th transistor is electrically connected with described output node, and one second end of described 6th transistor connects a low level.
7. shift registor as claimed in claim 1, is characterized in that, the high levle of described reset signal shifts to an earlier date high levle one phase differential of described coupled signal.
8. shift registor as claimed in claim 1, is characterized in that, described shift register module one before secondary shift register module one draw high the voltage of gate node as described reset signal.
9. shift registor as claimed in claim 1, it is characterized in that, described coupled signal is from an output node of shift register module described in previous stage.
10. a display device, is characterized in that, described display device comprises:
One display panel;
One data scanning driving circuit; And
Scan driving circuit has at least one shift registor, and wherein said shift registor has stages shift temporary storage module and is connected in series, and one of them grade of shift register module comprises:
One draws high unit, draws high gate node and an output node is electrically connected with one, and according to one first clock signal and described in draw high the voltage of gate node and start;
One draws high control module, be electrically connected with described output node with described gate node of drawing high, and the start according to a reset signal and a coupled signal, described control module of drawing high has one first limit voltage compensating unit, described first limit voltage compensating unit connects described reset signal and described coupled signal, and is electrically connected with described gate node of drawing high;
One drags down control module, is electrically connected with described control module of drawing high, and the start according to described reset signal, described coupled signal and a second clock signal; And
One drags down unit, is electrically connected with described unit of drawing high, and drags down gate node via one and be electrically connected with the described control module that drags down;
Wherein, the described first limit voltage compensating unit of described shift registor comprises one first compensation transistor, one the first transistor and one first building-out capacitor, one first end of described first compensation transistor, one first end of described first building-out capacitor and a first end of described the first transistor and a gate terminal are via one first common node electrical connection, one gate terminal of described first compensation transistor connects described reset signal, one second end of described first building-out capacitor connects described coupled signal, one second end of described the first transistor is electrically connected with described gate node of drawing high, one second end of described first compensation transistor connects one with reference to level.
11. display device as claimed in claim 10, it is characterized in that, described second end of the described the first transistor of described shift registor is electrically connected with one the 4th transistor via described gate node of drawing high, one gate terminal of described 4th transistor is electrically connected with the described gate node that drags down, one first end of described 4th transistor is electrically connected with described gate node of drawing high
Wherein, draw high control module described in described shift registor and more comprise a bias voltage reduction unit, it is electrically connected with described output node and described first common node, and is electrically connected via one second end of a node with described 4th transistor.
12. display device as claimed in claim 10, it is characterized in that, draw high unit described in described shift registor and comprise one the 5th transistor, one gate terminal of described 5th transistor is electrically connected with described gate node of drawing high, one first end of described 5th transistor connects described first clock signal, and one second end of described 5th transistor is electrically connected with described output node.
13. display device as claimed in claim 10, it is characterized in that, drag down control module described in described shift registor and there is one second limit voltage compensating unit, described second limit voltage compensating unit connects described reset signal and described second clock signal, and is electrically connected with the described unit that drags down via the described gate node that drags down.
14. display device as claimed in claim 13, it is characterized in that, the described second limit voltage compensating unit of described shift registor comprises one second compensation transistor, one third transistor and one second building-out capacitor, one first end of described second compensation transistor, one first end of described second building-out capacitor and a first end of described third transistor and a gate terminal are via one second common node electrical connection, one gate terminal of described second compensation transistor connects described reset signal, one second end of described second building-out capacitor connects described second clock signal, one second end of described third transistor is electrically connected with the described gate node that drags down, one second end of described second compensation transistor connects described with reference to level.
15. display device as claimed in claim 10, it is characterized in that, drag down unit described in described shift registor and comprise one the 6th transistor, one gate terminal of described 6th transistor is electrically connected with the described gate node that drags down, one first end of described 6th transistor is electrically connected with described output node, and one second end of described 6th transistor connects a low level.
16. display device as claimed in claim 10, is characterized in that, the described shift register module of described shift registor one before secondary shift register module one draw high the voltage of gate node as described reset signal.
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| CN201210043408.8A CN103295509B (en) | 2012-02-24 | 2012-02-24 | Shift registor and display device |
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| CN201210043408.8A CN103295509B (en) | 2012-02-24 | 2012-02-24 | Shift registor and display device |
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| CN103295509A CN103295509A (en) | 2013-09-11 |
| CN103295509B true CN103295509B (en) | 2016-04-06 |
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| US20180277232A1 (en) * | 2017-03-27 | 2018-09-27 | Int Tech Co., Ltd. | Shift register |
| TWI627622B (en) * | 2017-08-30 | 2018-06-21 | 友達光電股份有限公司 | Voltage compensation circuit and voltage compensation method |
| CN108831395B (en) * | 2018-07-17 | 2020-09-04 | 惠科股份有限公司 | Display device and shift register circuit |
| CN112331142B (en) * | 2020-11-25 | 2022-06-17 | 厦门天马微电子有限公司 | Scanning driving circuit, display panel and display device |
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| JP5073547B2 (en) * | 2008-03-27 | 2012-11-14 | ラピスセミコンダクタ株式会社 | Display drive circuit and display drive method |
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Address after: 518109 Longhua, Shenzhen, town, Foxconn science and Technology Industrial Park E District, building 4, building 1, building Applicant after: Qunkang Technology (Shenzhen) Co., Ltd. Applicant after: Innolux Display Group Address before: 518109 Longhua, Shenzhen, town, Foxconn science and Technology Industrial Park E District, building 4, building 1, building Applicant before: Qunkang Technology (Shenzhen) Co., Ltd. Applicant before: Chimei Optoelectronics Co., Ltd. |
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