CN103312162B - Voltage-multiplying circuit and comprise its radio frequency identification label chip - Google Patents
Voltage-multiplying circuit and comprise its radio frequency identification label chip Download PDFInfo
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- CN103312162B CN103312162B CN201210060641.7A CN201210060641A CN103312162B CN 103312162 B CN103312162 B CN 103312162B CN 201210060641 A CN201210060641 A CN 201210060641A CN 103312162 B CN103312162 B CN 103312162B
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Abstract
The invention provides a kind of voltage-multiplying circuit and comprise its radio frequency identification label chip, belong to integrated circuit (IC) design field.In this voltage-multiplying circuit, the nmos pass transistor in two transmission channels is replaced by PMOS transistor, and two PMOS transistor are connected in series formation first transmission channel, and two other PMOS transistor is connected in series formation second transmission channel.This voltage-multiplying circuit operating efficiency is high, by preparation process technology limit, be particluarly suitable for applying in RFID label chip.
Description
Technical field
The invention belongs to integrated circuit (IC) design field, relate to voltage-multiplying circuit, particularly relate in transmission channel and all use the voltage-multiplying circuit of PMOS transistor and comprise radio-frequency (RF) identification (RFID) label chip of this voltage-multiplying circuit.
Background technology
In IC chip design, often need to apply the normal power voltage (V being greater than IC itself and providing
dD) voltage source, therefore, usually can arrange charge pump circuit module with booster tension in IC chip, wherein voltage-multiplying circuit is exactly one of common charge pump circuit.
Figure 1 shows that the voltage-multiplying circuit structural representation of prior art.As shown in Figure 1, in this example, voltage-multiplying circuit 10 comprises four transmission mos transistors, 110,120,210,220 and two electric capacity 130,230.Wherein, MOS transistor 110 and 210 is nmos pass transistor, and MOS transistor 120 and 220 is PMOS transistor; Nmos pass transistor 110 and PMOS transistor 120 are connected in series, to form the first transmission channel basically; The level that B point place between the source/drain terminal and the drain terminal/source of PMOS transistor 120 of nmos pass transistor 110 arranges electric capacity 130, B point can control conducting or the closedown of nmos pass transistor 210 and PMOS transistor 220; Further, when PMOS transistor 120 conducting, the current potential of electric capacity 130 can export output end vo ut to.Equally, nmos pass transistor 210 and PMOS transistor 220 are connected in series, to form the second transmission channel basically; The level that A point place between the source/drain terminal and the drain terminal/source of PMOS transistor 220 of nmos pass transistor 210 arranges electric capacity 230, A point can control conducting or the shutoff of nmos pass transistor 110 and PMOS transistor 120; Further, when PMOS transistor 220 conducting, the current potential of electric capacity 230 can export output end vo ut to.
The basic functional principle of voltage-multiplying circuit shown in following key diagram 1.
(when supposing high level, normal power voltage V is equaled when being offset to the clock signal clk A on electric capacity 230 and becoming high level from low level
dD), the clock signal clk B be offset on electric capacity 130 side by side becomes low level from high level; After electric capacity, A point becomes high level, and B point is dragged down as low level;
When B point becomes low level, the grid end of nmos pass transistor 210 and PMOS transistor 220 is biased low level, and nmos pass transistor 210 turns off, and (such as it equals V to incoming level Vin
dD) cut-off, PMOS transistor 220 conducting, level signal (such as, the 2V of A point
dD) output end vo ut can be transferred to; Meanwhile, now A point becomes high level, and the grid end of nmos pass transistor 110 and PMOS transistor 120 is biased high level, nmos pass transistor 110 conducting, incoming level Vin can charge to electric capacity 130, and PMOS transistor 120 turns off simultaneously, and the level signal of B point can not be transmitted output by PMOS transistor 120;
Therefore, keep in the process of high level at the low level of B point maintenance thereafter, A point, the B point that electric capacity 130 connects is connected to incoming level Vin because of nmos pass transistor 110 conducting, thus keeps incoming level (V
dD).
On the contrary, when being offset to the clock signal clk A on electric capacity 230 and becoming low level from high level, the clock signal clk B be offset on electric capacity 130 side by side becomes high level from low level; After electric capacity, B point becomes high level (2V
dD), A point is dragged down as low level;
When B point becomes high level, the grid end of nmos pass transistor 210 and PMOS transistor 220 is biased high level, nmos pass transistor 210 conducting, and incoming level Vin transfers to A point and charges to electric capacity 230, PMOS transistor 220 turns off, and the level signal of A point can not be transmitted output by PMOS transistor 220; Meanwhile, now A point becomes low level, and the grid end of nmos pass transistor 110 and PMOS transistor 120 is biased high level, and nmos pass transistor 110 turns off, PMOS transistor 120 conducting, level signal (such as, the 2V of B point
dD) output end vo ut can be transferred to.
Therefore, keep in the process of high level at the low level of A point maintenance thereafter, B point, equally, due to nmos pass transistor 210 conducting, A point is connected with incoming level Vin, thus remains incoming level (V
dD).
Circulate and so forth, output end vo ut just can be made substantially to equal 2V
dD.
But the threshold voltage vt h of nmos pass transistor 110 and 210 is greater than 0, at normal power voltage V
dDoccur fluctuation and when being in lower, the normal power voltage V of input
dDbe difficult to be efficiently transmitted over a channel, thus make the current potential of A point and B point be difficult to be charged draw high promote V
dD, generally lower than V
dD, next time fill high in can not reach 2V
dD, therefore, make output end vo ut be less than 2V
dD, energy is underutilized, and the operating efficiency of voltage-multiplying circuit 10 reduces greatly.
For this reason, industry is improved the voltage-multiplying circuit 10 shown in Fig. 1, is used by nmos pass transistor 110 and 210 threshold voltage close to the particular device of NMOS tube (or being called " NativeNMOS ", depletion type NMOS) of zero, thus to raise the efficiency.But due to the existence of the substrate transformation effect (BodyEffect) of NativeNMOS, its threshold value can only be close to zero, is generally greater than zero, therefore, still can there is the energy loss of transmission, and the operating efficiency of voltage-multiplying circuit is difficult to effective raising.
Summary of the invention
The object of the invention is to, improve the operating efficiency of voltage-multiplying circuit.
For realizing above object or other objects, the invention provides following technical scheme.
According to an aspect of of the present present invention, provide a kind of voltage-multiplying circuit (30), it comprises:
First PMOS transistor (310);
Second MOS transistor (320) of formation first transmission channel is connected in series with described first PMOS transistor (310);
3rd PMOS transistor (410);
The 4th MOS transistor (420) of formation second transmission channel is connected in series with described 3rd PMOS transistor (410).
According to the voltage-multiplying circuit (30) of one embodiment of the invention, wherein, voltage-multiplying circuit (30) also comprises:
Be respectively used to control described first PMOS transistor (310), the second MOS transistor (320), first logical circuit (311) of turn-on and turn-off of the 3rd PMOS transistor (410) and the 4th MOS transistor (420), the second logical circuit (321), the 3rd logical circuit (411) and the 4th logical circuit (421);
First electric capacity (330), its first end is connected to the Section Point (D) between the first PMOS transistor (310) on the first transmission channel and the second MOS transistor (320), and its second termination enters the 4th clock signal (CLKB); And
Second electric capacity (430), its first end is connected to the first node (C) between the 3rd PMOS transistor (410) on the second transmission channel and the 4th MOS transistor (420), and its second termination enters the 3rd clock signal (CLKA);
Wherein, the level signal of described Section Point (D) is fed and inputs to described first logical circuit (311) and the 4th logical circuit (421), meanwhile, second clock signal (CLKBM) inputs to described first logical circuit (311) and the 4th logical circuit (421);
The level signal of described first node (C) is fed and inputs to described second logical circuit (321) and the 3rd logical circuit (411), meanwhile, the first clock signal (CLKAM) inputs to described second logical circuit (321) and the 3rd logical circuit (411);
The input (Vin) of described voltage-multiplying circuit (30) connects the source/drain terminal of described first PMOS transistor (310) and the 3rd PMOS transistor (410) simultaneously, and the output (Vout) of described voltage-multiplying circuit (30) connects the drain terminal/source of described second PMOS transistor (320) and the 4th PMOS transistor (420) simultaneously.
According to the voltage-multiplying circuit (30) of further embodiment of this invention, wherein, described first logical circuit (311), the second logical circuit (321), the 3rd logical circuit (411) and/or the 4th logical circuit (421) for the current potential of output low level be 0 substantially, the current potential of high level be substantially 2 times to normal power voltage (V
dD) signal, with control respectively the first PMOS transistor (310), the second MOS transistor (320), the 3rd PMOS transistor (410) and the 4th MOS transistor (420) the conducting when this low level is biased of grid end, when this high level is biased turn off.
In the voltage-multiplying circuit (30) of described any embodiment before, described first PMOS transistor (310), the second MOS transistor (320), the 3rd PMOS transistor (410) and the 4th MOS transistor (420) can be depletion type PMOS transistor or enhancement mode PMOS transistor.
In the voltage-multiplying circuit (30) of described any embodiment before, preferably, described first electric capacity (330) and the second electric capacity (430) are mos capacitance.
In the voltage-multiplying circuit (30) of described any embodiment before, arrange described first clock signal (CLKAM), second clock signal (CLKBM), the 3rd clock signal (CLKA) and the 4th clock signal (CLKB) phase relation substantially equal to double normal power voltage (V with the output voltage of the output making described voltage-multiplying circuit (30)
dD).
In the voltage-multiplying circuit (30) of described any embodiment before, preferably, the low level of described first clock signal (CLKAM), second clock signal (CLKBM), the 3rd clock signal (CLKA) and the 4th clock signal (CLKB) and high level are respectively 0 current potential and normal power voltage (V
dD).
In the voltage-multiplying circuit (30) of described any embodiment before, preferably, low level and the high potential of described first node (C) and Section Point (D) are respectively normal power voltage (V
dD), 2 times to normal power voltage (2V
dD).
According to another aspect of the present invention, provide a kind of RFID label chip, it comprise the above and any one voltage-multiplying circuit (30).
According to the RFID label chip of one embodiment of the invention, it also comprises: four phase clocks for generation of the signal of described first clock signal (CLKAM), second clock signal (CLKBM), the 3rd clock signal (CLKA) and the 4th clock signal (CLKB) produce circuit (50).
Technique effect of the present invention is, by the nmos pass transistor in transmission channel is replaced with PMOS transistor, and, four PMOS transistor in voltage-multiplying circuit can control its turn-on and turn-off respectively by four logical circuits, make the efficiency of transmission of the PMOS transistor of this replacement when conducting high, therefore, the energy conversion loss of this voltage-multiplying circuit is little, and operating efficiency is greatly enhanced.Further, it is realized by circuit design, and the raising of operating efficiency is little by preparation process technology limit, is especially used in the large RFID label chip of working power voltage fluctuation range and applies.
Accompanying drawing explanation
From following detailed description by reference to the accompanying drawings, will make above and other object of the present invention and advantage more completely clear, wherein, same or analogous key element adopts identical label to represent.
Fig. 1 is the voltage-multiplying circuit structural representation of prior art;
Fig. 2 is the basic structure schematic diagram of the multiplication of voltage operating circuit according to one embodiment of the invention;
Fig. 3 is voltage-multiplying circuit time diagram operationally embodiment illustrated in fig. 2;
Fig. 4 is circuit modular structure schematic diagram relevant to voltage-multiplying circuit in the RFID label chip according to one embodiment of the invention.
Embodiment
Introduce below be of the present invention multiple may some in embodiment, aim to provide basic understanding of the present invention, be not intended to confirm key of the present invention or conclusive key element or limit claimed scope.Easy understand, according to technical scheme of the present invention, do not changing under connotation of the present invention, one of ordinary skill in the art can propose other implementations that can mutually replace.Therefore, following embodiment and accompanying drawing are only the exemplary illustrations to technical scheme of the present invention, and should not be considered as of the present invention all or the restriction be considered as technical solution of the present invention or restriction.
For improving the operating efficiency of voltage-multiplying circuit, those skilled in the art set about from the device architecture and performance that improve nmos pass transistor, to promote the efficiency of transmission of nmos pass transistor 110 and 210 as shown in Figure 1 more.And in the present invention, trigger from the circuit structure of voltage-multiplying circuit the operating efficiency improving the circuit of multiplication of voltage emphatically.
Figure 2 shows that the basic structure schematic diagram of the multiplication of voltage operating circuit according to one embodiment of the invention.As shown in Figure 2, there are two transmission channels between the input Vin of voltage-multiplying circuit 30 and output end vo ut, input Vin can input normal power voltage V
dD.Wherein, Article 1, transmission channel is formed by two PMOS transistor be connected in series 310 and PMOS transistor 320 substantially, drain terminal/the source of PMOS transistor 310 is connected with input Vin, source/the drain terminal of PMOS transistor 310 is connected with the drain terminal/source of PMOS transistor 320, and the source/drain terminal of PMOS transistor 320 exports output end vo ut to; Article 2 transmission channel is formed by two PMOS transistor be connected in series 410 and PMOS transistor 420 substantially, drain terminal/the source of PMOS transistor 410 is connected with input Vin, source/the drain terminal of PMOS transistor 410 is connected with the drain terminal/source of PMOS transistor 420, and the source/drain terminal of PMOS transistor 420 exports output end vo ut to.
Node D place between the source/drain terminal of PMOS transistor 310 and the drain terminal/source of PMOS transistor 320 arranges electric capacity 330, one end incoming clock signal CLKB of electric capacity 330, and the other end is connected with node D; Equally, the node C place between the source/drain terminal of PMOS transistor 410 and the drain terminal/source of PMOS transistor 420 arranges electric capacity 430, and one end incoming clock signal CLKA of electric capacity 430, the other end is connected with node C.Therefore, the normal power voltage V that transmits by the current potential of electric capacity 330 and PMOS transistor 310 of the current potential of node D
dD(Vin input) affects, the normal power voltage V that the current potential of node C transmits by current potential and the PMOS transistor 410 of electric capacity 430
dD(Vin input) affects.
In this article, the high level of four that provide different clock signal clk A, CLKB, CLKAM, CLKBM is V
dD, low level is V
sS(V
sS=0V), the concrete sequential of clock signal clk A, CLKB, CLKAM, CLKBM in figure 3 example provides.
Continue as shown in Figure 2, for controlling conducting and/or the shutoff of PMOS transistor, this voltage-multiplying circuit 30 also comprises four logical circuits 311,321,411,421.Wherein, logical circuit 311 and logical circuit 421 incoming clock signal CLKBM, simultaneously, the level signal feed back input logical circuit 311 of node D and logical circuit 421, the level signal of logical circuit 311,421 couples of clock signal clk BM and node D processes to output signal bm2 and bm1 respectively, bm2 and bm1 can be used for controlling the turn-on and turn-off of PMOS transistor 310 and PMOS transistor 420 respectively.When PMOS transistor 310 conducting, V
dDbe transferred to node D; Meanwhile, PMOS transistor 420 conducting, the level signal of node C is transmitted and exports Vout to.
Simultaneously, logical circuit 321 and logical circuit 411 incoming clock signal CLKAM, simultaneously, the level signal feed back input logical circuit 321 of node C and logical circuit 411, the level signal of logical circuit 321,411 couples of clock signal clk AM and node C processes to output signal am2 and am1 respectively, am2 and am1 can be used for controlling the turn-on and turn-off of PMOS transistor 320 and PMOS transistor 410 respectively.When PMOS transistor 410 conducting, V
dDbe transferred to node C; Meanwhile, PMOS transistor 320 conducting, the level signal of node D is transmitted and exports Vout to.
By controlling the phase relation of clock signal clk A, CLKB, CLKAM, CLKBM, when making PMOS transistor 310 and 420 conducting, PMOS transistor 410 and 320 turns off, and the level of node C exports, and the level of node D equals V substantially
dD; When making PMOS transistor 410 and 320 conducting, PMOS transistor 310 and 420 turns off, and the level of node D exports, and the level of node C equals V substantially
dD; Meanwhile, the level of node C, before output, is biased high level signal by CLKA and makes the level of node C be pulled up to 2V by electric capacity 430
dD, and when the level that PMOS transistor 420 conducting maintains node C exports, the level of node C maintains 2V
dD, therefore, Vout can export 2V
dD; Equally, the level of node D, before output, is biased high level signal by CLKB and makes the level of node D be pulled up to 2V by electric capacity 330
dD, and when the level that PMOS transistor 320 conducting maintains node D exports, the level of node D maintains 2V
dD, therefore, Vout can export 2V
dD.
Figure 3 shows that voltage-multiplying circuit embodiment illustrated in fig. 2 time diagram operationally, wherein, " Low " represents its low level, and " high " represents its high level.Composition graphs 3 and Fig. 2, illustrate the basic functional principle of the voltage-multiplying circuit of this embodiment.
At CLKAM from high level (high level high=V
dD) become low level (low level Low=V
sS) time (CLKA is low level, CLKB is high level, CLKBM be low level), node C is relatively low level V
dD(low level Low=V
dD), process through logical circuit 321 and 411, am1 and am2 is raised to V
dD;
When CLKA uprises level from low level (CLKAM is low level, CLKB is high level, CLKBM be low level), electric capacity 430 charges, by node C from V
dDbe raised to 2 times of V
dD(high level of node C), process through logical circuit 321 and 411, am1 and am2 follows node C and is raised to 2 times of V
dD, the PMOS transistor 410 that am1 controls turns off completely, cuts off node C and Vin, and the PMOS transistor 320 that am2 controls turns off completely, cuts off node D and Vout;
When CLKB becomes low level from high level (CLKA is high level, CLKAM is low level, CLKBM be low level), by node D from 2 times of V
dD(high level) is pulled low to V
dD(low level), process through logical circuit 311 and 421, bm1 and bm2 follows node D from high level 2V
dDbe pulled low to V
dD(bm1 is V
dD, because node C is 2V
dD, PMOS transistor 420 is in conducting state, and Vout exports 2V
dD, further subsequently when CLKBM is raised to V
dD, bm1 is dragged down as V
sStime, PMOS transistor 420 more fully conducting, Vout is maintained 2VDD);
When CLKBM becomes high level from low level (CLKA is high level, CLKAM is low level, CLKB be high level), process through logical circuit 311 and 421, bm1 and bm2 is further from V
dDbe pulled low to low level V
sS(0 current potential), the PMOS transistor 420 that bm1 controls conducting completely, the level signal (2V of node C
dD) be connected with Vout through PMOS transistor 420, Vout is 2 times of V
dD; The PMOS transistor 310 that bm2 controls conducting completely, node D is connected with Vin through PMOS transistor 310, and node D remains input voltage V
dD(because bm2 is 0, PMOS transistor 310 transmits V
dDnot loss, the level of node D completely can reach V
dD);
Then, based on the principle that above process is substantially identical, above inverse process is performed, CLKBM becomes high level from low level, and then, CLKB becomes high level from low level, CLKA becomes low level from high level, and CLKAM becomes high level from low level, and node D can become 2 times of V
dD, and passing through the complete conducting of PMOS transistor 320, Vout exports 2V
dD, PMOS transistor 410 conducting completely under 0 electric potential signal of am1 controls, node C and Vin is communicated with, and becomes V
dD(because am1 is 0, PMOS transistor 410 transmits V
dDnot loss, the level of node C completely can reach V
dD).
Therefore, in voltage-multiplying circuit 30, the conducting of four PMOS transistor 310,320,410,420 all realizes by 0 control of Electric potentials of grid end, and it turns off also by the 2V of grid end
dDcontrol of Electric potentials realizes, therefore, all can realize complete conducting (when needs conducting) and turn off (when needs turn off) completely, PMOS transistor 310,320,410,420 (particularly PMOS transistor 310,410) efficiency of transmission as transfer tube is high, and the operating efficiency of voltage-multiplying circuit effectively improves.
When voltage-multiplying circuit 30 is applied to RFID (radio-frequency (RF) identification) label chip, the normal power voltage V in RFID label chip
dDfluctuation range large, such as, normal power voltage V
dDnormal voltage when being 1.8V, it can fluctuate in scope from 1.0V to 2.2V.At normal power voltage V
dDfluctuation range large time, the nmos pass transistor (as shown in Figure 1) in the transmission channel in traditional voltage-multiplying circuit is difficult to realize complete conducting or shutoff more, and therefore, efficiency of transmission is lower.If for improving efficiency of transmission, the operating voltage of nmos pass transistor reduced, this may cause again nmos pass transistor by 2 times of V
dD(V
dDduring for higher value) punch through damage.Therefore, the voltage-multiplying circuit 30 of example shown in Fig. 2 is especially suitable for and is applied in RFID label chip.
Such as, when voltage-multiplying circuit 10 embodiment illustrated in fig. 1 is applied to RFID label chip, if V
dDfluctuation is to 1.0V (smaller value), and the operating efficiency of voltage-multiplying circuit 10 only has about 20%; And if V when being applied to RFID label chip for voltage-multiplying circuit 30 embodiment illustrated in fig. 2
dDfluctuation is to 1.0V (smaller value), and voltage-multiplying circuit 30 still can export the multiplication of voltage close to 2V, and operating efficiency still can reach 50% to 65%.
Figure 4 shows that circuit modular structure schematic diagram relevant to voltage-multiplying circuit in the RFID label chip according to one embodiment of the invention.This RFID label chip comprises voltage-multiplying circuit 30, four phase clock and produces circuit 50 and normal power voltage module 70, and normal power voltage module 70 is that the input (Vin) of voltage-multiplying circuit 20 provides normal power voltage V
dD, four phase clocks produce circuit 50 for generation of four different clock signals (CLKA, CLKB, CLKAM, CLKBM), export and substantially equal 2V after the process of voltage-multiplying circuit 30 multiplication of voltage
dDvoltage signal.
It will be appreciated that, the multiplication of voltage of the voltage-multiplying circuit 30 in Fig. 2 and Fig. 4 exports size and not only depends on its operating efficiency (operating efficiency is higher, represent that energy conversion efficiency is high, the output voltage of output is more close to twice input voltage), also depend on the size of the output loading of voltage-multiplying circuit 30; In description above about the operation principle of voltage-multiplying circuit 30, multiplication of voltage exports as 2V
dDthere is no the situation gained of output loading.Although it is also to be appreciated that greatly can improve the efficiency of transmission of PMOS transistor, other working loss is not considered in the output of voltage-multiplying circuit.
In the embodiment depicted in figure 2, electric capacity 330 and/or 430 can be chosen as mos capacitance, and such opposed configuration is simple, easily prepares under MOS technique.
It is to be appreciated that PMOS transistor 310,320,410,420 can be depletion type PMOS transistor, its cut-in voltage V
tscope be preferably and be more than or equal to 0 to being less than or equal between VDD; PMOS transistor 310,320,410,420 also can be enhancement mode PMOS transistor, its cut-in voltage V
tscope be preferably and be more than or equal to-VDD to being less than or equal to 0, those skilled in the art specifically can arrange the concrete threshold voltage of PMOS transistor according to the announcement of the above operation principle.
Above example mainly describes voltage-multiplying circuit of the present invention and uses the RFID label chip of this voltage-multiplying circuit.Although be only described some of them embodiments of the present invention, those of ordinary skill in the art should understand, and the present invention can implement with other forms many not departing from its purport and scope.Therefore, the example shown and execution mode are regarded as illustrative and not restrictive, when do not depart from as appended each claim define the present invention spirit and scope, the present invention may contain various amendments and replacement.
Claims (8)
1. a voltage-multiplying circuit (30), is characterized in that, comprising:
First PMOS transistor (310);
Second MOS transistor (320) of formation first transmission channel is connected in series with described first PMOS transistor (310);
3rd PMOS transistor (410);
The 4th MOS transistor (420) of formation second transmission channel is connected in series with described 3rd PMOS transistor (410);
Be respectively used to control described first PMOS transistor (310), the second MOS transistor (320), first logical circuit (311) of turn-on and turn-off of the 3rd PMOS transistor (410) and the 4th MOS transistor (420), the second logical circuit (321), the 3rd logical circuit (411) and the 4th logical circuit (421);
First electric capacity (330), its first end is connected to the Section Point (D) between the first PMOS transistor (310) on the first transmission channel and the second MOS transistor (320), and its second termination enters the 4th clock signal (CLKB); And
Second electric capacity (430), its first end is connected to the first node (C) between the 3rd PMOS transistor (410) on the second transmission channel and the 4th MOS transistor (420), and its second termination enters the 3rd clock signal (CLKA);
Wherein, the level signal of described Section Point (D) is fed and inputs to described first logical circuit (311) and the 4th logical circuit (421), meanwhile, second clock signal (CLKBM) inputs to described first logical circuit (311) and the 4th logical circuit (421);
The level signal of described first node (C) is fed and inputs to described second logical circuit (321) and the 3rd logical circuit (411), meanwhile, the first clock signal (CLKAM) inputs to described second logical circuit (321) and the 3rd logical circuit (411);
The input (Vin) of described voltage-multiplying circuit (30) connects the source/drain terminal of described first PMOS transistor (310) and the 3rd PMOS transistor (410) simultaneously, and the output (Vout) of described voltage-multiplying circuit (30) connects the drain terminal/source of described second MOS transistor (320) and the 4th MOS transistor (420) simultaneously;
Arrange described first clock signal (CLKAM), second clock signal (CLKBM), the 3rd clock signal (CLKA) and the 4th clock signal (CLKB) phase relation substantially equal to double normal power voltage (V with the output voltage of the output making described voltage-multiplying circuit (30)
dD).
2. voltage-multiplying circuit (30) as claimed in claim 1, it is characterized in that, described first logical circuit (311), the second logical circuit (321), the 3rd logical circuit (411) and the 4th logical circuit (421) for the current potential of output low level be 0 substantially, the current potential of high level be substantially 2 times to normal power voltage (V
dD) signal, with control respectively the first PMOS transistor (310), the second MOS transistor (320), the 3rd PMOS transistor (410) and the 4th MOS transistor (420) the conducting when this low level is biased of grid end, when this high level is biased turn off.
3. voltage-multiplying circuit (30) as claimed in claim 1, it is characterized in that, described first PMOS transistor (310), the second MOS transistor (320), the 3rd PMOS transistor (410) and the 4th MOS transistor (420) are depletion type PMOS transistor or enhancement mode PMOS transistor.
4. voltage-multiplying circuit (30) as claimed in claim 1 or 2, it is characterized in that, described first electric capacity (330) and the second electric capacity (430) are mos capacitance.
5. voltage-multiplying circuit (30) as claimed in claim 1, it is characterized in that, low level and the high level of described first clock signal (CLKAM), second clock signal (CLKBM), the 3rd clock signal (CLKA) and the 4th clock signal (CLKB) are respectively 0 current potential and normal power voltage (V
dD).
6. voltage-multiplying circuit (30) as claimed in claim 1 or 2, it is characterized in that, low level and the high potential of described first node (C) and Section Point (D) are respectively normal power voltage (V
dD), 2 times to normal power voltage (2V
dD).
7. a radio frequency identification label chip, is characterized in that, comprises the voltage-multiplying circuit (30) according to any one of claim 1 to 6.
8. radio frequency identification label chip as claimed in claim 7, it is characterized in that, also comprise: four phase clocks for generation of the signal of described first clock signal (CLKAM), second clock signal (CLKBM), the 3rd clock signal (CLKA) and the 4th clock signal (CLKB) produce circuit (50).
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| CN201210060641.7A CN103312162B (en) | 2012-03-08 | 2012-03-08 | Voltage-multiplying circuit and comprise its radio frequency identification label chip |
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|---|---|---|---|
| CN201210060641.7A CN103312162B (en) | 2012-03-08 | 2012-03-08 | Voltage-multiplying circuit and comprise its radio frequency identification label chip |
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| CN101888181A (en) * | 2010-08-02 | 2010-11-17 | 中国电子科技集团公司第二十四研究所 | Charge pump circuit based on feedback |
| CN102104328A (en) * | 2009-12-18 | 2011-06-22 | 上海华虹Nec电子有限公司 | Charge pump circut |
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| CN1256554A (en) * | 1999-09-03 | 2000-06-14 | 北京大学 | New-type CMOS charge pump and its cascade method |
| US6661682B2 (en) * | 2001-02-16 | 2003-12-09 | Imec (Interuniversitair Microelectronica Centrum) | High voltage generating charge pump circuit |
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| CN101674011A (en) * | 2008-12-16 | 2010-03-17 | 昆山锐芯微电子有限公司 | Charge pump |
| CN101510728A (en) * | 2008-12-18 | 2009-08-19 | 昆山锐芯微电子有限公司 | Charge pump and CMOS image sensor |
| CN102104328A (en) * | 2009-12-18 | 2011-06-22 | 上海华虹Nec电子有限公司 | Charge pump circut |
| CN101888181A (en) * | 2010-08-02 | 2010-11-17 | 中国电子科技集团公司第二十四研究所 | Charge pump circuit based on feedback |
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