CN103377954A - Forming method for grid bonding pad and source bonding pad - Google Patents
Forming method for grid bonding pad and source bonding pad Download PDFInfo
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- CN103377954A CN103377954A CN201210132712XA CN201210132712A CN103377954A CN 103377954 A CN103377954 A CN 103377954A CN 201210132712X A CN201210132712X A CN 201210132712XA CN 201210132712 A CN201210132712 A CN 201210132712A CN 103377954 A CN103377954 A CN 103377954A
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Abstract
The invention relates to a forming method for a grid bonding pad and a source bonding pad. The forming method comprises the step that copper alloy layers of the grid bonding pad and the source bonding pad are formed on a wafer through physical vapor deposition, wherein the deposition temperature of the deposition step is 250+/-10 DEG C. Color difference between the grid bonding pad and the source bonding pad formed by the forming method for the grid bonding pad and the source bonding pad is large, so that the forming method for the grid bonding pad and the source bonding pad meets the recognition requirements of a bonding machine, can reduce rework rate, is easy to operate, can be implemented with the adoption of an original production device, has no need to enable a new device to be added, and cannot increase the cost for purchasing the new device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to the formation method of a kind of gate pads and source pad.
Background technology
Double-diffusion metal-oxide-semiconductor field effect transistor (DMOSFET) product need to carry out bonding (bonding) with the pad on grid and the source electrode (pad) and gold thread in packaging technology.Generally speaking, bonding machine platform can carry out bonding automatically according to the difference of pad on color of grid and source electrode, but sometimes can can't distinguish the two because of the very little bonding machine platform that causes of difference between gate pads and source pad, as shown in Figure 1.The left side is the product that bonding machine platform can be identified among Fig. 1, and the right is the impalpable product of bonding machine platform.This series products on Fig. 1 the right can only be by manually manually connecting gold thread, thereby cause production efficiency low.
Summary of the invention
Based on this, be necessary can cause the too small problem of pad color distortion for the formation method of traditional gate pads and source pad, provide a kind of and can obtain the gate pads of larger color distortion and the formation method of source pad.
The formation method of a kind of gate pads and source pad comprises physical vapor deposition in the step of the albronze layer of wafer formation gate pads and source pad, and the deposition temperature of described depositing step maintains 250 ± 10 degrees centigrade.
Therein among embodiment, described physical vapor deposition forms the step of the albronze layer of gate pads and source pad at wafer, specifically in the second cavity, carry out, and whether the temperature that also comprises the following steps: after this step to monitor in described the second cavity surpasses the first temperature threshold, until the deposit of described albronze layer is complete; In case surpass the first temperature threshold then interrupt the deposit of described albronze layer, and described wafer is shifted out described the second cavity lower the temperature, simultaneously described the second cavity is carried out cooling processing; Whether the temperature of monitoring in described the second cavity is lower than the second temperature threshold, in case be lower than the second temperature threshold then described wafer retracted described the second cavity proceed deposit.
Among embodiment, described the first temperature threshold is 255 degrees centigrade therein.
Therein among embodiment, the step that described physical vapor deposition forms the albronze layer of gate pads and source pad at wafer is included in the albronze layer of deposit the first thickness in the second cavity and two steps of the albronze layer of deposit the second thickness in the second cavity, and comprise also between described two steps that wafer is shifted out described the second cavity lowers the temperature, simultaneously described the second cavity is carried out cooling processing, until the temperature in described the second cavity is lower than the step of the second temperature threshold.
Among embodiment, described the first thickness is that 22,000 dusts and the second thickness are 22,000 dusts therein.
Among embodiment, described the second temperature threshold is 245 degrees centigrade therein.
Therein among embodiment, described physical vapor deposition forms at wafer before the step of albronze layer of gate pads and source pad, also is included in the first cavity the step by physical vapor deposition process deposit titanium coating and titanium nitride layer on described wafer.
Therein among embodiment, describedly in the first cavity, before the step by physical vapor deposition process deposit titanium coating and titanium nitride layer, also be included in the step of the described wafer of baking in the degassed cavity.
Therein among embodiment, described in degassed cavity in the step of the described wafer of baking baking temperature be 150 ± 10 degrees centigrade.
Among embodiment, the step of described deposit titanium coating and titanium nitride layer is to carry out at normal temperatures deposit therein.
Color distortion is larger between the grid that the formation method of above-mentioned gate pads and source pad forms and the source pad, therefore the identification requirement that meets bonding machine platform, can reduce rework rate, and simple to operate, the original production equipment of employing just can be implemented, need not to acquire new equipment, can not increase the cost of purchasing new equipment.
Description of drawings
Fig. 1 is that bonding machine platform can be identified and impalpable grid and source pad photo;
Fig. 2 is to be respectively the photo of 300 degrees centigrade and 250 degrees centigrade of lower grids and source pad;
Fig. 3 is the deposition temperature data when adopting a kind of Endura board to carry out the deposit of albronze layer;
Fig. 4 is the flow chart of the formation method of gate pads and source pad among the embodiment;
Fig. 5 is the structural representation of titanium coating, titanium nitride layer and albronze layer;
Fig. 6 is the flow chart of the formation method of gate pads and source pad among another embodiment;
Fig. 7 is the deposition temperature data when adopting method embodiment illustrated in fig. 6 to carry out the deposit of albronze layer;
Fig. 8 is the Comparative Examples that adopts the described embodiment of Fig. 6, temperature data shown in Figure 3, the grid that reaches 300 degrees centigrade of traditional technology formation and the photo of source pad.
Embodiment
For purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
The color distortion of gate pads and source pad is because this metal level (material is the albronze alloy) of grid is covered on the more smooth surface, and this metal level (material is similarly albronze) of source electrode is covered on the more coarse surface, so source pad in theory should be darker than gate pads.
But the inventor finds according to research and experiment, if the metal level of above-mentioned source electrode temperature when deposit is higher, then the crystallite dimension of metal level (grain size) will be larger, even the comparatively coarse surface curve below the metal level all covered, cause the layer on surface of metal difference of the layer on surface of metal of source electrode and grid very little, final performance is exactly that the color distortion of source pad and gate pads is very little, causes bonding (bonding) board can't automatically identify source pad and the gate pads of DMOS device.
Therefore the inventor infers if the temperature of metal level in deposition process of pad also controlled in reduction effectively, just can obtain the larger grid of color distortion and source pad.Experimental result as shown in Figure 2.Fig. 2 shows respectively at 300 degrees centigrade of local photos of two wafer (wafer) lower and carry out the metal level deposit of gate pads and source pad under 250 degrees centigrade, we can see respectively the color distortion contrast of the chip of the chip (die) that is positioned at crystal circle center under two kinds of temperature and crystal round fringes from figure, and the color distortion between 250 degrees centigrade of lower grids and the source pad is significantly greater than the color distortion under 300 degrees centigrade.Physical vapor deposition process is adopted in the deposit of this metal level, deposit form for the metal level material be albronze.In actual production, physical vapor deposition deposition temperature in the albronze layer process of wafer formation gate pads and source pad can be controlled at 250 ± 10 degrees centigrade, be preferably 250 degrees centigrade.
But in actual production, the temperature of cement copper aluminium alloy layer is generally 270 and 300 degrees centigrade two kinds in the industry.If use 250 degrees centigrade technique, then the conversion meeting more complicated between the various temperature process is difficult to control.Take a kind of Endura board as example, its purpose of design is for the deposit of carrying out the albronze film under the environment about 300 degrees centigrade, therefore if under 250 degrees centigrade of techniques, carry out deposit, and carrying out continuously along with depositing technics then, temperature will be unstable, as shown in Figure 3.Specifically in Fig. 3, show the trend that temperature rises gradually.
For this problem, the inventor proposes again the formation method of a kind of gate pads and source pad, and Fig. 4 is the flow chart of the formation method of gate pads and source pad among the embodiment, comprises the following steps:
S110 places degassed cavity to toast wafer.
Noticing that the front road of the DMOS technique of the wafer in this step finishes, is conventional process so locate to repeat no more because of what adopt.Baking temperature can be 150 ± 10 degrees centigrade, is preferably 150 degrees centigrade.
S120, in the first cavity by physical vapor deposition process deposit titanium coating and titanium nitride layer on wafer.
In the present embodiment, this step adopts normal temperature to carry out deposit.Adopt lower temperature (for example normal temperature) to be deposited with and help improve in the step of subsequent deposition albronze layer, the crystallite dimension of crystal makes it become less.Titanium nitride layer 20 is covered on the titanium coating 10, as shown in Figure 5.It is pointed out that the structure under the titanium coating 10 is omitted in Fig. 5.In the present embodiment, the thickness of titanium coating is
The thickness of titanium nitride layer is
S130 passes through physical vapor deposition process cement copper aluminium alloy layer in the second cavity.
Wherein albronze layer 30 is covered on the titanium nitride layer 20, as shown in Figure 5.Deposition temperature can be 250 ± 10 degrees centigrade, is preferably 250 degrees centigrade.
S140, whether the temperature of monitoring in the second cavity surpasses the first temperature threshold, if surpass then execution in step S142, otherwise execution in step S150.
If it is too high that the first temperature threshold arranges, then the color distortion of grid and source pad is just obvious not; If the low frequent cooling that then needs was set, affected production efficiency.In the present embodiment, the first temperature threshold is set to 255 degrees centigrade.
S142 interrupts deposit and wafer is shifted out the cooling of the second cavity, simultaneously the second cavity cavity is carried out cooling processing, until the temperature in the second cavity is lower than the second temperature threshold.
Specifically wafer can be moved to the cooling of cooling cavity.The cooling down of wafer and the second cavity can adopt the nature cooling, also can pass into the inactive gas of chemical property---and the nitrogen that for example temperature is lower cools off.When the second cavity cavity is carried out cooling processing, still to continue to monitor the temperature in the second cavity, until the temperature in the second cavity is lower than the second temperature threshold, execution in step S150 then.
If it is too high that the second temperature threshold arranges, then need frequent cooling, affect production efficiency; If arranged lowly, then to be lower than preferred temperature more for deposition temperature, may affect device performance.In the present embodiment, the second temperature threshold is set to 245 degrees centigrade.
In the present embodiment, the target thickness of albronze layer deposit is 44,000 dusts, i.e. 4400 nanometers.
S150 continues deposit until finish the deposit of albronze.After step S150 finishes wafer is cooled off, return at last film magazine.
In one embodiment, measure the interior temperature of the second cavity among the step S140 above behind the first temperature threshold, be not to interrupt immediately deposit, but after this wafer deposit is finished, again the second cavity carried out cooling processing.(namely the temperature in the second cavity is lower than the second temperature threshold) carries out the deposit of albronze layer again to next wafer after the cooling of the second cavity is finished.
Fig. 6 is the flow chart of the formation method of gate pads and source pad among another embodiment, and itself and the main distinction embodiment illustrated in fig. 4 are: the step by physical vapor deposition process cement copper aluminium alloy layer in the second cavity is to carry out in two steps.Be to comprise the following steps: behind step S210 and the S220
S230, the albronze layer by physical vapor deposition process elder generation deposit one half thickness in the second cavity.
Be the albronze layer of 44,000 dusts for target thickness for example, the thick albronze of first deposit 22,000 dusts among the step S230.
S240 shifts out the cooling of the second cavity with wafer, simultaneously the second cavity is carried out cooling processing, until the second cavity temperature is lower than the second temperature threshold.
In the present embodiment, the second temperature threshold is set to 245 degrees centigrade.
S250 remains the albronze layer of a half thickness by the physical vapor deposition process deposit in the second cavity.
Be appreciated that ground, also the deposition thickness among step S230, the S250 can be distributed in other embodiments by each 50% to replace to other ratio, for example prior to the albronze layer of deposit 40% thickness among the step S230, again in step S250 deposit remaining 60%.
In other embodiments, can also be with Fig. 4 and the combination of Fig. 6 two schemes, the deposit of albronze layer was divided into for two steps, for example in first depositing step embodiment illustrated in fig. 6 first deposit half, the second depositing step again deposit second half.Be higher than first threshold if detect temperature in the first depositing step, after then the first depositing step is finished wafer and the second cavity cooled off, carry out again the second depositing step after being cooled to the second temperature threshold; Be higher than first threshold if in the second depositing step, detect temperature, then after the deposit of this wafer albronze layer is finished, again the second cavity cooled off.
The formation method of above-mentioned gate pads and source pad, the deposition temperature of albronze layer can be controlled at target temperature (250 degrees centigrade) ± 6 degrees centigrade in, as shown in Figure 7.Fig. 8 shows respectively the Comparative Examples that adopts the described embodiment of Fig. 6, temperature data shown in Figure 3, the grid that reaches 300 degrees centigrade of traditional technology formation and the photo of source pad.Color distortion is larger between the grid of the formation method of above-mentioned gate pads and source pad formation and the source pad as can be seen from Figure 8, therefore the identification requirement that meets bonding machine platform, can reduce rework rate, and simple to operate, the original production equipment of employing just can be implemented, need not to acquire new equipment, can not increase the cost of purchasing new equipment.
Although above embodiment introduction is the gate pads of DMOS device and the formation method of source pad, but those skilled in the art will envision that for similar other device of structure and material, need to use bonding machine platform that grid and source pad and gold thread are carried out bonding, also can use method of the present invention with the color distortion between the more significant grid of acquisition and the source pad.
The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to claim of the present invention.Should be pointed out that for the person of ordinary skill of the art without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. the formation method of a gate pads and source pad comprises that physical vapor deposition forms the step of the albronze layer of gate pads and source pad at wafer, is characterized in that the deposition temperature of described depositing step maintains 250 ± 10 degrees centigrade.
2. the formation method of gate pads according to claim 1 and source pad, it is characterized in that, described physical vapor deposition specifically carries out in the second cavity in the step of the albronze layer of wafer formation gate pads and source pad, and also comprises the following steps: after this step
Whether the temperature of monitoring in described the second cavity surpasses the first temperature threshold, until the deposit of described albronze layer is complete; In case surpass the first temperature threshold then interrupt the deposit of described albronze layer, and described wafer is shifted out described the second cavity lower the temperature, simultaneously described the second cavity is carried out cooling processing;
Whether the temperature of monitoring in described the second cavity is lower than the second temperature threshold, in case be lower than the second temperature threshold then described wafer retracted described the second cavity proceed deposit.
3. the formation method of gate pads according to claim 2 and source pad is characterized in that, described the first temperature threshold is 255 degrees centigrade.
4. the formation method of gate pads according to claim 1 and source pad, it is characterized in that, the step that described physical vapor deposition forms the albronze layer of gate pads and source pad at wafer is included in the albronze layer of deposit the first thickness in the second cavity and two steps of the albronze layer of deposit the second thickness in the second cavity, and comprise also between described two steps that wafer is shifted out described the second cavity lowers the temperature, simultaneously described the second cavity is carried out cooling processing, until the temperature in described the second cavity is lower than the step of the second temperature threshold.
5. the formation method of gate pads according to claim 4 and source pad is characterized in that, described the first thickness is that 22,000 dusts and the second thickness are 22,000 dusts.
6. according to claim 2 or the formation method of 4 described gate pads and source pad, it is characterized in that described the second temperature threshold is 245 degrees centigrade.
7. according to claim 2 or the formation method of 4 described gate pads and source pad, it is characterized in that, described physical vapor deposition forms at wafer before the step of albronze layer of gate pads and source pad, also is included in the first cavity the step by physical vapor deposition process deposit titanium coating and titanium nitride layer on described wafer.
8. the formation method of gate pads according to claim 7 and source pad, it is characterized in that, describedly in the first cavity, before the step by physical vapor deposition process deposit titanium coating and titanium nitride layer, also be included in the step of the described wafer of baking in the degassed cavity.
9. the formation method of gate pads according to claim 8 and source pad is characterized in that, described in degassed cavity the baking described wafer step in baking temperature be 150 ± 10 degrees centigrade.
10. the formation method of gate pads according to claim 7 and source pad is characterized in that, the step of described deposit titanium coating and titanium nitride layer is to carry out at normal temperatures deposit.
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| CN201210132712.XA CN103377954B (en) | 2012-04-28 | 2012-04-28 | Gate pads and the forming method of source pad |
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| CN201210132712.XA CN103377954B (en) | 2012-04-28 | 2012-04-28 | Gate pads and the forming method of source pad |
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| KR970053037U (en) * | 1996-02-17 | 1997-09-08 | Eccentric motion prevention device of control box | |
| CN1922726A (en) * | 2004-02-20 | 2007-02-28 | 微米技术有限公司 | Methods of fabricating interconnects for semiconductor components |
| CN1921071A (en) * | 2005-08-26 | 2007-02-28 | 三菱电机株式会社 | Semiconductor device manufacturing apparatus, semiconductor device manufacturing method and semiconductor device |
| CN101640179A (en) * | 2008-07-31 | 2010-02-03 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing weld pad structure |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970053037U (en) * | 1996-02-17 | 1997-09-08 | Eccentric motion prevention device of control box | |
| CN1922726A (en) * | 2004-02-20 | 2007-02-28 | 微米技术有限公司 | Methods of fabricating interconnects for semiconductor components |
| US7189642B2 (en) * | 2004-02-20 | 2007-03-13 | Micron Technology, Inc. | Methods of fabricating interconnects including depositing a first material in the interconnect with a thickness of angstroms and a low temperature for semiconductor components |
| CN1921071A (en) * | 2005-08-26 | 2007-02-28 | 三菱电机株式会社 | Semiconductor device manufacturing apparatus, semiconductor device manufacturing method and semiconductor device |
| CN101640179A (en) * | 2008-07-31 | 2010-02-03 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing weld pad structure |
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