CN103616833A - Control circuit of wireless collector - Google Patents
Control circuit of wireless collector Download PDFInfo
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- CN103616833A CN103616833A CN201310587605.0A CN201310587605A CN103616833A CN 103616833 A CN103616833 A CN 103616833A CN 201310587605 A CN201310587605 A CN 201310587605A CN 103616833 A CN103616833 A CN 103616833A
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Abstract
The invention discloses a control circuit of a wireless collector. The control circuit of the wireless collector comprises a central processing single-chip microcomputer integrated circuit, an internal memory integrated circuit, an infrared receiving integrated tube GD 1 control circuit, a USB port control circuit, a level switch integrated circuit and a power supply control circuit, wherein the internal memory integrated circuit, the infrared receiving integrated tube GD 1 control circuit, the USB port control circuit, the level switch integrated circuit and the power supply control circuit are all connected with the central processing single-chip microcomputer integrated circuit. The control circuit of the wireless collector is designed according to the design philosophy of low voltage, low power consumption, low cost and small size, and data can be collected remotely by means of the characteristics such as the effective low level, the high sensitivity and high photoelectromagnetic interference resistance of an infrared receiving integrated tube GD 1.
Description
Technical field
The present invention relates to control circuit field, the control circuit of concrete a kind of wireless collection device.
Background technology
In the high-tech industrialization of information epoch, be also the high-tech electronic information products epoch, and these electronic products be unable to do without the control of electronic circuit.And the information data of numerous electronic products is various, thereby produced all kinds of data acquisition units.
The data acquisition unit volume of use is all larger in the market, gathers distance short, and is must connect civil power just can use, and this has brought and how inconveniently belonged to user.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of control circuit of wireless collection device, with low-voltage, low-power consumption, low cost, design concept that volume is little, design, utilize the strong characteristic of Low level effective, high sensitivity, anti-optical magnetic interference ability of infrared reception integral tube GD1 can carry out far beyond apart from image data.
Technical scheme of the present invention is:
A kind of control circuit of wireless collection device, include central processing single chip integrated circuit, the internal storage integrated circuit being connected with central processing single chip integrated circuit respectively, infrared reception integral tube GD1 control circuit, USB port control circuit, level conversion integrated circuit and power control circuit;
Described central processing single chip integrated circuit includes singlechip chip U1 and peripheral component, one end of peripheral component resistance R 9 connects the stitch 42 of singlechip chip U1, the other end of peripheral component resistance R 9 connects power access end VCC2, after one end of one end of resistance R 71 and capacitor C 71 is in parallel, be connected to the stitch 4 of singlechip chip U1, the other end ground connection of capacitor C 71, the other end of resistance R 71 connects power access end VCC2, stitch 7 and load capacitance C62 one end of singlechip chip U1 is parallel-connected to 2 ends of crystal oscillator X1, stitch 8 and load capacitance C61 one end of singlechip chip U1 is parallel-connected to 1 end of crystal oscillator X1, the other end of load capacitance C61 and load capacitance C62 is parallel-connected to common ground end, the stitch 6 of singlechip chip U1, 18, 39 access common ground ends in parallel, the stitch 5 of singlechip chip U1, 17, 38, 27 access power supply VCC2 in parallel, the stitch 29 of one end access singlechip chip U1 of capacitor C 1, the other end access common ground end of capacitor C 1, the stitch 28 of singlechip chip U1 connects common ground end,
Described internal storage integrated circuit includes internal storage chip U2 and peripheral component, on the stitch 40 of one end access in parallel singlechip chip U1 of the stitch 6 of internal storage chip U2 and peripheral component resistance R EO, the other end access power access end VCC2 of resistance R EO, the stitch 5 of internal storage chip U2 is parallel-connected on the stitch 41 of U1 with one end of resistance R E1, the other end power access end VCC2 of resistance R E1;
Described infrared reception integral tube control circuit includes infrared reception integral tube GD1, peripheral component resistance R G1, has electrode capacitance CG0, resistance R G0; The stitch 1 of infrared reception integral tube GD1 and the stitch 12 of singlechip chip U1 are parallel to one end of resistance R G1, resistance R G1 another termination power access end VCC2, infrared electro receives the stitch 2 access common ground ends of integral tube, there is electrode capacitance CG0 one end anodal and resistance R G0 access in parallel infrared electro to receive the stitch 3 of integral tube, there is the negative pole of electrode capacitance CG0 to connect power access end VCC, the other end access power access end VCC2 of resistance R G0;
Described USB port control circuit includes USB chip U3 and USB interface J1, the stitch 1 of USB chip U3, 2, 3, 4, 6, 7, 8, 9, 16, 15, 28 are connected respectively the stitch 37 of singlechip chip U1, 36, 35, 34, 33, 32, 31, 30, 13, 14, 21, USB interface J1 stitch 1 connects power access end VCC3, one end of one end of resistance R U6 and resistance R U9 is parallel-connected to the stitch 3 of USB interface J1, the other end of resistance R U6 connects common ground end, the other end of resistance R U9 connects the stitch 26 of USB chip U3, one end of one end of resistance R U7 and resistance R U8 is parallel-connected to the stitch 2 of USB interface J1, the other end of resistance R U7 connects power access end VCC3, the other end of resistance R U8 connects the stitch 25 of USB chip U3,
Described level conversion integrated circuit includes level transferring chip U4, the stitch 10 of level transferring chip U4, stitch 9 be connected respectively singlechip chip U1 stitch 10 and stitch 9;
Described power control circuit includes power supply chip U5 and cell apparatus T1, an access common ground end extremely in parallel of the stitch 1 of power supply chip U5 and cell apparatus T1, the stitch 2 of power supply chip U5 connects power access end VCC1, another power access end VCC that is then connected to extremely in parallel of the stitch 3 of power supply chip U5 and cell apparatus T1.
The stitch 5 of described USB chip U3, stitch 10, stitch 11, stitch 12 connect common ground end; The stitch 14 of USB chip U3 connects one end of peripheral component resistance R U4, and the other end of resistance R U4 connects power access end VCC3; The stitch 27 of USB chip U3 connects anodal one end of peripheral component capacitor C 3, and negative pole one end of capacitor C 3 connects common ground end; USB chip U3 stitch 24, stitch 20 connect respectively power access end VCC3; The stitch 21 of USB chip U3 connects anodal one end of blue indicator light DS1, one end of negative pole one end contact resistance RU3 of blue indicator light DS1, the stitch 19 of one end access in parallel USB chip U3 of one end of resistance R U5 and resistance R U2, the other end access common ground end of resistance R U5, the stitch 17 of USB chip U3, stitch 18 and stitch 19 are connected respectively one end of resistance R U0, one end of one end of resistance R U1 and resistance R U2, the other end access in parallel power access end VCC3 of resistance R U0, resistance R U1, resistance R U2 and resistance R U3.
The stitch 1 of described level transferring chip U4 and stitch 3 are connected respectively the two ends of capacitor C RS0; The stitch 4 of level transferring chip U4 and stitch 5 are connected respectively the two ends of capacitor C RS1; The stitch 15 access common ground ends of level transferring chip U4; The stitch 6 of level transferring chip U4 connects one end of capacitor C RS3, the other end access common ground end of capacitor C RS3; The stitch 7 of level transferring chip U4 and stitch 8 be 2 stitch and 3 stitch of attachment plug J3 respectively, the stitch 5 access common ground ends of plug J3; The stitch 16 of level transferring chip U4 connects power access end VCC; The stitch 2 of level transferring chip U4 connects one end of capacitor C RS2, and the other end of capacitor C RS2 connects power access end VCC.
The control circuit of described wireless collection device also includes the control circuit of shift knob KEY1 and shift knob KEY2; The control circuit of described shift knob KEY1 includes shift knob KEY1, the stitch 1 access common ground end of shift knob KEY1, the stitch 42 of the stitch 3 access singlechip chip U1 of shift knob KEY1; The control circuit of described shift knob KEY2 includes shift knob KEY2, the stitch 1 access power access end VCC1 of shift knob KEY2, the stitch 2 access power access end VCC2 of shift knob KEY2, the stitch 3 access power access end VCC3 of shift knob KEY2.
The control circuit of described wireless collection device also includes the control circuit of green image data pilot lamp DS2 and red power switch pilot lamp DS3; The control circuit of described green image data pilot lamp DS2 includes green image data pilot lamp DS2 and resistance R T1, negative pole one end access common ground end of green image data pilot lamp DS2, one end of anodal one end contact resistance RT1 of green image data pilot lamp DS2, the stitch 15 of the other end access singlechip chip U1 of resistance R T1; The control circuit of described red power switch pilot lamp DS3 includes red power switch pilot lamp DS3 and resistance R T2, negative pole one end access common ground end of red power switch pilot lamp DS3, one end of anodal one end contact resistance RT2 of red power switch pilot lamp DS3, the stitch 16 of the other end access singlechip chip U1 of resistance R T2.
The control circuit of described wireless collection device also comprises hummer control circuit, and hummer control circuit includes hummer RING, diode D3, triode TR1 and resistance R R1; A pin of hummer RING and the positive pole of the diode D3 power access end VCC2 that is connected in parallel, another pin of hummer RING and the negative pole of diode D3 are parallel-connected to the pin c of triode TR1, the pin e of triode TR1 connects common ground end, one end of the pin b contact resistance RR1 of triode TR1, the stitch 21 of the other end access singlechip chip U1 of resistance R R1.
The control circuit of described wireless collection device also includes clock chip control circuit, and described clock chip control circuit includes clock chip P4; The stitch 1 of clock chip P4 is connected with the stitch 1 of singlechip chip U1, the stitch 2 of clock chip P4 connects power access end VCC2, the stitch 5 of clock chip P4 is connected with stitch 4 stitch of singlechip chip U1, stitch 7 pin of clock chip P4 are connected with the stitch 3 of the singlechip chip U1 of U1, the stitch 9 of clock chip P4 is connected with the stitch 2 of the singlechip chip U1 of U1, the stitch 4 of clock chip P4, stitch 6, stitch 8, stitch 10 access common ground in parallel end.
The control circuit of described wireless collection device also includes battery supply socket P1, the pin 1 access common ground end of battery supply socket P1, pin 2 access power access end VCC.
Advantage of the present invention:
(1), the present invention large, the anti-light of infrared its infraluminescence angle of reception integral tube GD1, the anti-electromagnetic interference capability that adopt be strong, can to target, receive image data more at a distance;
(2), infrared reception integral tube GD1 of the present invention controls by K switch EY1, KEY2, plug and play, closes and stops, and saved greatly the power consumption of battery, extends the serviceable life of product, reduces costs and reduces consumption, saves the energy;
(3), the present invention adopts indigo plant, red, green three pilot lamp to point out its working stage for client, by USB port, the data importing collecting is inquired about and printed in PC again, circuit design is rationally easy, and production cost is low and be easy to a large amount of production, has met greatly client's demand.
Accompanying drawing explanation
Fig. 1 is central processing single chip integrated circuit diagram of the present invention.
Fig. 2 is internal storage integrated circuit diagram of the present invention.
Fig. 3 is of the present invention infrared reception integral tube control circuit figure.
Fig. 4 is USB port control circuit figure of the present invention.
Fig. 5 is level conversion integrated circuit diagram of the present invention.
Fig. 6 is power control circuit figure of the present invention.
Fig. 7 is the circuit connection diagram of USB interface J1 of the present invention.
Fig. 8 is the control circuit figure of shift knob KEY1 of the present invention.
Fig. 9 is the control circuit figure of shift knob KEY2 of the present invention.
Figure 10 is the control circuit figure of the green image data pilot lamp of the present invention DS2.
Figure 11 is the control circuit figure of the red power switch pilot lamp of the present invention DS3.
Figure 12 is the control circuit figure of hummer of the present invention.
Figure 13 is the control circuit figure of clock chip of the present invention.
Figure 14 is the circuit connection diagram of battery supply socket P1 of the present invention.
Figure 15 is fundamental diagram of the present invention.
Embodiment
A kind of control circuit of wireless collection device, include central processing single chip integrated circuit, control circuit, hummer control circuit, clock chip control circuit and the battery supply socket P1 of the internal storage integrated circuit being connected with central processing single chip integrated circuit respectively, infrared reception integral tube GD1 control circuit, USB port control circuit, level conversion integrated circuit, power control circuit, shift knob KEY1 and the control circuit of shift knob KEY2, green image data pilot lamp DS2 and red power switch pilot lamp DS3;
See Fig. 1, central processing single chip integrated circuit includes singlechip chip U1 and peripheral component, and one end of peripheral component resistance R 9 connects the stitch 42 of singlechip chip U1, and the other end of peripheral component resistance R 9 connects power access end VCC2; After one end of one end of resistance R 71 and capacitor C 71 is in parallel, be connected to the stitch 4 of singlechip chip U1, the other end ground connection of capacitor C 71, the other end of resistance R 71 connects power access end VCC2; Stitch 7 and load capacitance C62 one end of singlechip chip U1 is parallel-connected to 2 ends of crystal oscillator X1, stitch 8 and load capacitance C61 one end of singlechip chip U1 is parallel-connected to 1 end of crystal oscillator X1, and the other end of load capacitance C61 and load capacitance C62 is parallel-connected to common ground end; Stitch 6,18, the 39 access common ground in parallel end of singlechip chip U1; Stitch 5,17,38, the 27 access power supply in parallel VCC2 of singlechip chip U1; The stitch 29 of one end access singlechip chip U1 of capacitor C 1, the other end access common ground end of capacitor C 1; The stitch 28 of singlechip chip U1 connects common ground end;
See Fig. 2, internal storage integrated circuit includes internal storage chip U2 and peripheral component, on the stitch 40 of one end access in parallel singlechip chip U1 of the stitch 6 of internal storage chip U2 and peripheral component resistance R EO, the other end access power access end VCC2 of resistance R EO; The stitch 5 of internal storage chip U2 is parallel-connected on the stitch 41 of U1 with one end of resistance R E1, the other end power access end VCC2 of resistance R E1; Stitch 1,2,3, the 4 access common ground in parallel end of internal storage chip U2; The stitch 7 access common ground ends of internal storage chip U2; The stitch 8 of internal storage chip U2 connects power access end VCC2;
See Fig. 3, infrared reception integral tube control circuit includes infrared reception integral tube GD1, peripheral component resistance R G1, has electrode capacitance CG0, resistance R G0; The stitch 1 of infrared reception integral tube GD1 and the stitch 12 of singlechip chip U1 are parallel to one end of resistance R G1, resistance R G1 another termination power access end VCC2, infrared electro receives the stitch 2 access common ground ends of integral tube; There is electrode capacitance CG0 one end anodal and resistance R G0 access in parallel infrared electro to receive the stitch 3 of integral tube, have the negative pole of electrode capacitance CG0 to connect power access end VCC, the other end access power access end VCC2 of resistance R G0;
See Fig. 4, USB port control circuit includes USB chip U3 and USB interface J1, and the stitch 5 of USB chip U3, stitch 10, stitch 11, stitch 12 connect common ground end; The stitch 14 of USB chip U3 connects one end of peripheral component resistance R U4, and the other end of resistance R U4 connects power access end VCC3; The stitch 27 of USB chip U3 connects anodal one end of peripheral component capacitor C 3, and negative pole one end of capacitor C 3 connects common ground end; USB chip U3 stitch 24, stitch 20 connect respectively power access end VCC3; The stitch 21 of USB chip U3 connects anodal one end of blue indicator light DS1, one end of negative pole one end contact resistance RU3 of blue indicator light DS1; The stitch 19 of one end access in parallel USB chip U3 of one end of resistance R U5 and resistance R U2, the other end access common ground end of resistance R U5; The stitch 17 of USB chip U3, stitch 18 and stitch 19 are connected respectively one end of resistance R U0, one end of one end of resistance R U1 and resistance R U2, the other end access in parallel power access end VCC3 of resistance R U0, resistance R U1, resistance R U2 and resistance R U3; The stitch 1,2,3,4,6,7,8,9,16,15,28 of USB chip U3 is connected respectively the stitch 37,36,35,34,33,32,31,30,13,14,21 of singlechip chip U1; See Fig. 7, USB interface J1 stitch 1 connects power access end VCC3; One end of one end of resistance R U6 and resistance R U9 is parallel-connected to the stitch 3 of USB interface J1, the other end of resistance R U6 connects common ground end, the other end of resistance R U9 connects the stitch 26 of USB chip U3, one end of one end of resistance R U7 and resistance R U8 is parallel-connected to the stitch 2 of USB interface J1, the other end of resistance R U7 connects power access end VCC3, and the other end of resistance R U8 connects the stitch 25 of USB chip U3;
See Fig. 5, level conversion integrated circuit includes level transferring chip U4, the stitch 10 of level transferring chip U4, stitch 9 be connected respectively singlechip chip U1 stitch 10 and stitch 9; The stitch 1 of level transferring chip U4 and stitch 3 are connected respectively the two ends of capacitor C RS0; The stitch 4 of level transferring chip U4 and stitch 5 are connected respectively the two ends of capacitor C RS1; The stitch 15 access common ground ends of level transferring chip U4; The stitch 6 of level transferring chip U4 connects one end of capacitor C RS3, the other end access common ground end of capacitor C RS3; The stitch 7 of level transferring chip U4 and stitch 8 be 2 stitch and 3 stitch of attachment plug J3 respectively, the stitch 5 access common ground ends of plug J3; The stitch 16 of level transferring chip U4 connects power access end VCC; The stitch 2 of level transferring chip U4 connects one end of capacitor C RS2, and the other end of capacitor C RS2 connects power access end VCC;
See Fig. 6, power control circuit includes power supply chip U5 and cell apparatus T1, an access common ground end extremely in parallel of the stitch 1 of power supply chip U5 and cell apparatus T1; The stitch 2 of power supply chip U5 connects power access end VCC1; Another power access end VCC that is then connected to extremely in parallel of the stitch 3 of power supply chip U5 and cell apparatus T1; The pin 1 access common ground end of battery supply socket P1, pin 2 access power access end VCC(are shown in Figure 14);
See Fig. 8, the control circuit of shift knob KEY1 includes shift knob KEY1, the stitch 1 access common ground end of shift knob KEY1, the stitch 42 of the stitch 3 access singlechip chip U1 of shift knob KEY1;
See Fig. 9, the control circuit of shift knob KEY2 includes shift knob KEY2, the stitch 1 access power access end VCC1 of shift knob KEY2, the stitch 2 access power access end VCC2 of shift knob KEY2, the stitch 3 access power access end VCC3 of shift knob KEY2; The stitch 5 of U1, stitch 17, stitch 38 and stitch 27, the stitch 2 of KEY2 all connects with VCC2, thereby realizes the connection of U1 and KEY2;
See Figure 10, the control circuit of green image data pilot lamp DS2 includes green image data pilot lamp DS2 and resistance R T1, negative pole one end access common ground end of green image data pilot lamp DS2, one end of anodal one end contact resistance RT1 of green image data pilot lamp DS2, the stitch 15 of the other end access singlechip chip U1 of resistance R T1;
See Figure 11, the control circuit of red power switch pilot lamp DS3 includes red power switch pilot lamp DS3 and resistance R T2, negative pole one end access common ground end of red power switch pilot lamp DS3, one end of anodal one end contact resistance RT2 of red power switch pilot lamp DS3, the stitch 16 of the other end access singlechip chip U1 of resistance R T2;
See Figure 12, hummer control circuit includes hummer RING, diode D3, triode TR1 and resistance R R1; A pin of hummer RING and the positive pole of the diode D3 power access end VCC2 that is connected in parallel, another pin of hummer RING and the negative pole of diode D3 are parallel-connected to the pin c of triode TR1, the pin e of triode TR1 connects common ground end, one end of the pin b contact resistance RR1 of triode TR1, the stitch 21 of the other end access singlechip chip U1 of resistance R R1;
See Figure 13, clock chip control circuit includes clock chip P4; The stitch 1 of clock chip P4 is connected with the stitch 1 of singlechip chip U1, the stitch 2 of clock chip P4 connects power access end VCC2, the stitch 5 of clock chip P4 is connected with stitch 4 stitch of singlechip chip U1, stitch 7 pin of clock chip P4 are connected with the stitch 3 of the singlechip chip U1 of U1, the stitch 9 of clock chip P4 is connected with the stitch 2 of the singlechip chip U1 of U1, the stitch 4 of clock chip P4, stitch 6, stitch 8, stitch 10 access common ground in parallel end.
See Figure 15, principle of work of the present invention:
(1), No. 5 batteries of 2 joint are put into cell apparatus T1, and cell apparatus TI plug is inserted in battery supply socket P1, from OFF, shift shift knob KEY1 onto ON position, power supply chip U5 is activated, and now red power switch pilot lamp DS3 is bright, singlechip chip U1 is activated simultaneously, clock chip P4 regularly produces a signal, wake infrared reception integral tube GD1 up, now oneself energising of this wireless collection device control circuit is in running order, and all electronic devices and components are standby;
(2), press shift knob KEY2, hummer RING sends the voice prompt of " ticking ", infrared integrated pipe GD1 control circuit is connected simultaneously, and send the information of infrared receiver target door lock, now green image data pilot lamp DS2 lights, infrared integrated pipe GD1 enters the communication collecting in singlechip chip U1, through singlechip chip U1, will after information processing, be stored in internal storage chip U2;
(3), in the time the data that gather need to being derived, with usb data line one end, insert USB interface J1, now blue indicator light DS1 lights, illustrate that oneself connects this wireless collection device and PC computer, USB chip U3 enters communication in singlechip chip U1, simultaneously level transferring chip U4 becomes Transistor-Transistor Logic level by COMS level conversion, keeps the electric charge of whole control circuit to be tending towards the normal load of circuit, reduces power consumption.
Claims (9)
1. the control circuit of a wireless collection device, it is characterized in that: include central processing single chip integrated circuit, the internal storage integrated circuit being connected with central processing single chip integrated circuit respectively, infrared reception integral tube GD1 control circuit, USB port control circuit, level conversion integrated circuit and power control circuit;
Described central processing single chip integrated circuit includes singlechip chip U1 and peripheral component, one end of peripheral component resistance R 9 connects the stitch 42 of singlechip chip U1, the other end of peripheral component resistance R 9 connects power access end VCC2, after one end of one end of resistance R 71 and capacitor C 71 is in parallel, be connected to the stitch 4 of singlechip chip U1, the other end ground connection of capacitor C 71, the other end of resistance R 71 connects power access end VCC2, stitch 7 and load capacitance C62 one end of singlechip chip U1 is parallel-connected to 2 ends of crystal oscillator X1, stitch 8 and load capacitance C61 one end of singlechip chip U1 is parallel-connected to 1 end of crystal oscillator X1, the other end of load capacitance C61 and load capacitance C62 is parallel-connected to common ground end, the stitch 6 of singlechip chip U1, 18, 39 access common ground ends in parallel, the stitch 5 of singlechip chip U1, 17, 38, 27 access power supply VCC2 in parallel, the stitch 29 of one end access singlechip chip U1 of capacitor C 1, the other end access common ground end of capacitor C 1, the stitch 28 of singlechip chip U1 connects common ground end,
Described internal storage integrated circuit includes internal storage chip U2 and peripheral component, on the stitch 40 of one end access in parallel singlechip chip U1 of the stitch 6 of internal storage chip U2 and peripheral component resistance R EO, the other end access power access end VCC2 of resistance R EO, the stitch 5 of internal storage chip U2 is parallel-connected on the stitch 41 of U1 with one end of resistance R E1, the other end power access end VCC2 of resistance R E1;
Described infrared reception integral tube control circuit includes infrared reception integral tube GD1, peripheral component resistance R G1, has electrode capacitance CG0, resistance R G0; The stitch 1 of infrared reception integral tube GD1 and the stitch 12 of singlechip chip U1 are parallel to one end of resistance R G1, resistance R G1 another termination power access end VCC2, infrared electro receives the stitch 2 access common ground ends of integral tube, there is electrode capacitance CG0 one end anodal and resistance R G0 access in parallel infrared electro to receive the stitch 3 of integral tube, there is the negative pole of electrode capacitance CG0 to connect power access end VCC, the other end access power access end VCC2 of resistance R G0;
Described USB port control circuit includes USB chip U3 and USB interface J1, the stitch 1 of USB chip U3, 2, 3, 4, 6, 7, 8, 9, 16, 15, 28 are connected respectively the stitch 37 of singlechip chip U1, 36, 35, 34, 33, 32, 31, 30, 13, 14, 21, USB interface J1 stitch 1 connects power access end VCC3, one end of one end of resistance R U6 and resistance R U9 is parallel-connected to the stitch 3 of USB interface J1, the other end of resistance R U6 connects common ground end, the other end of resistance R U9 connects the stitch 26 of USB chip U3, one end of one end of resistance R U7 and resistance R U8 is parallel-connected to the stitch 2 of USB interface J1, the other end of resistance R U7 connects power access end VCC3, the other end of resistance R U8 connects the stitch 25 of USB chip U3,
Described level conversion integrated circuit includes level transferring chip U4, the stitch 10 of level transferring chip U4, stitch 9 be connected respectively singlechip chip U1 stitch 10 and stitch 9;
Described power control circuit includes power supply chip U5 and cell apparatus T1, an access common ground end extremely in parallel of the stitch 1 of power supply chip U5 and cell apparatus T1, the stitch 2 of power supply chip U5 connects power access end VCC1, another power access end VCC that is then connected to extremely in parallel of the stitch 3 of power supply chip U5 and cell apparatus T1.
2. the control circuit of a kind of wireless collection device according to claim 1, it is characterized in that: stitch 1,2,3, the 4 access common ground in parallel end of described internal storage chip U2, the stitch 7 access common ground ends of internal storage chip U2, the stitch 8 of internal storage chip U2 connects power access end VCC2.
3. the control circuit of a kind of wireless collection device according to claim 1, is characterized in that: the stitch 5 of described USB chip U3, stitch 10, stitch 11, stitch 12 connect common ground end; The stitch 14 of USB chip U3 connects one end of peripheral component resistance R U4, and the other end of resistance R U4 connects power access end VCC3; The stitch 27 of USB chip U3 connects anodal one end of peripheral component capacitor C 3, and negative pole one end of capacitor C 3 connects common ground end; USB chip U3 stitch 24, stitch 20 connect respectively power access end VCC3; The stitch 21 of USB chip U3 connects anodal one end of blue indicator light DS1, one end of negative pole one end contact resistance RU3 of blue indicator light DS1, the stitch 19 of one end access in parallel USB chip U3 of one end of resistance R U5 and resistance R U2, the other end access common ground end of resistance R U5, the stitch 17 of USB chip U3, stitch 18 and stitch 19 are connected respectively one end of resistance R U0, one end of one end of resistance R U1 and resistance R U2, the other end access in parallel power access end VCC3 of resistance R U0, resistance R U1, resistance R U2 and resistance R U3.
4. the control circuit of a kind of wireless collection device according to claim 1, is characterized in that: the stitch 1 of described level transferring chip U4 and stitch 3 are connected respectively the two ends of capacitor C RS0; The stitch 4 of level transferring chip U4 and stitch 5 are connected respectively the two ends of capacitor C RS1; The stitch 15 access common ground ends of level transferring chip U4; The stitch 6 of level transferring chip U4 connects one end of capacitor C RS3, the other end access common ground end of capacitor C RS3; The stitch 7 of level transferring chip U4 and stitch 8 be 2 stitch and 3 stitch of attachment plug J3 respectively, the stitch 5 access common ground ends of plug J3; The stitch 16 of level transferring chip U4 connects power access end VCC; The stitch 2 of level transferring chip U4 connects one end of capacitor C RS2, and the other end of capacitor C RS2 connects power access end VCC.
5. the control circuit of a kind of wireless collection device according to claim 1, is characterized in that: the control circuit of described wireless collection device also includes the control circuit of shift knob KEY1 and shift knob KEY2; The control circuit of described shift knob KEY1 includes shift knob KEY1, the stitch 1 access common ground end of shift knob KEY1, the stitch 42 of the stitch 3 access singlechip chip U1 of shift knob KEY1; The control circuit of described shift knob KEY2 includes shift knob KEY2, the stitch 1 access power access end VCC1 of shift knob KEY2, the stitch 2 access power access end VCC2 of shift knob KEY2, the stitch 3 access power access end VCC3 of shift knob KEY2.
6. the control circuit of a kind of wireless collection device according to claim 1, is characterized in that: the control circuit of described wireless collection device also includes the control circuit of green image data pilot lamp DS2 and red power switch pilot lamp DS3; The control circuit of described green image data pilot lamp DS2 includes green image data pilot lamp DS2 and resistance R T1, negative pole one end access common ground end of green image data pilot lamp DS2, one end of anodal one end contact resistance RT1 of green image data pilot lamp DS2, the stitch 15 of the other end access singlechip chip U1 of resistance R T1; The control circuit of described red power switch pilot lamp DS3 includes red power switch pilot lamp DS3 and resistance R T2, negative pole one end access common ground end of red power switch pilot lamp DS3, one end of anodal one end contact resistance RT2 of red power switch pilot lamp DS3, the stitch 16 of the other end access singlechip chip U1 of resistance R T2.
7. the control circuit of a kind of wireless collection device according to claim 1, it is characterized in that: the control circuit of described wireless collection device also comprises hummer control circuit, hummer control circuit includes hummer RING, diode D3, triode TR1 and resistance R R1; A pin of hummer RING and the positive pole of the diode D3 power access end VCC2 that is connected in parallel, another pin of hummer RING and the negative pole of diode D3 are parallel-connected to the pin c of triode TR1, the pin e of triode TR1 connects common ground end, one end of the pin b contact resistance RR1 of triode TR1, the stitch 21 of the other end access singlechip chip U1 of resistance R R1.
8. the control circuit of a kind of wireless collection device according to claim 1, is characterized in that: the control circuit of described wireless collection device also includes clock chip control circuit, and described clock chip control circuit includes clock chip P4; The stitch 1 of clock chip P4 is connected with the stitch 1 of singlechip chip U1, the stitch 2 of clock chip P4 connects power access end VCC2, the stitch 5 of clock chip P4 is connected with stitch 4 stitch of singlechip chip U1, stitch 7 pin of clock chip P4 are connected with the stitch 3 of the singlechip chip U1 of U1, the stitch 9 of clock chip P4 is connected with the stitch 2 of the singlechip chip U1 of U1, the stitch 4 of clock chip P4, stitch 6, stitch 8, stitch 10 access common ground in parallel end.
9. the control circuit of a kind of wireless collection device according to claim 1, it is characterized in that: the control circuit of described wireless collection device also includes battery supply socket P1, the pin 1 access common ground end of battery supply socket P1, pin 2 access power access end VCC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310587605.0A CN103616833B (en) | 2013-11-21 | 2013-11-21 | A kind of control circuit of wireless collection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310587605.0A CN103616833B (en) | 2013-11-21 | 2013-11-21 | A kind of control circuit of wireless collection device |
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| CN103616833A true CN103616833A (en) | 2014-03-05 |
| CN103616833B CN103616833B (en) | 2016-01-27 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105761476A (en) * | 2016-04-15 | 2016-07-13 | 中国矿业大学 | Mining low-power-consumption data acquisition unit based on infrared transmission |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2671237Y (en) * | 2003-12-22 | 2005-01-12 | 庄革 | Wireless remote transmitting collector |
| CN200953182Y (en) * | 2006-09-27 | 2007-09-26 | 鞍山银宇电子科技有限公司 | Radio data collector |
| US20090093229A1 (en) * | 2007-10-05 | 2009-04-09 | Hand Held Products, Inc. | Panic Button for Data Collection Device |
| CN201984325U (en) * | 2010-12-28 | 2011-09-21 | 重庆恩菲斯软件有限公司 | Multifunctional data acquisition device |
| CN203573127U (en) * | 2013-11-21 | 2014-04-30 | 合肥天智科技发展有限公司 | Control circuit for wireless gatherer |
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2013
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2671237Y (en) * | 2003-12-22 | 2005-01-12 | 庄革 | Wireless remote transmitting collector |
| CN200953182Y (en) * | 2006-09-27 | 2007-09-26 | 鞍山银宇电子科技有限公司 | Radio data collector |
| US20090093229A1 (en) * | 2007-10-05 | 2009-04-09 | Hand Held Products, Inc. | Panic Button for Data Collection Device |
| CN201984325U (en) * | 2010-12-28 | 2011-09-21 | 重庆恩菲斯软件有限公司 | Multifunctional data acquisition device |
| CN203573127U (en) * | 2013-11-21 | 2014-04-30 | 合肥天智科技发展有限公司 | Control circuit for wireless gatherer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105761476A (en) * | 2016-04-15 | 2016-07-13 | 中国矿业大学 | Mining low-power-consumption data acquisition unit based on infrared transmission |
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| CN103616833B (en) | 2016-01-27 |
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