CN1036740C - 一种介质隔离半导体器件及其制造方法 - Google Patents

一种介质隔离半导体器件及其制造方法 Download PDF

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CN1036740C
CN1036740C CN94100576A CN94100576A CN1036740C CN 1036740 C CN1036740 C CN 1036740C CN 94100576 A CN94100576 A CN 94100576A CN 94100576 A CN94100576 A CN 94100576A CN 1036740 C CN1036740 C CN 1036740C
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A·李特温
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Infineon Technologies AG
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Abstract

半导体器件包括衬底、氧化层和负性低掺杂(n)的单晶片。在片中刻蚀出围绕元件区的用于形成介质绝缘层的深槽。通过第1掩膜在元件区进行扩散，元件区的场效应晶体管就具有两个正性掺杂(P)的片状栅区。通过第2掩模在元件区对两个负性重掺杂(n+)区进行扩散，这些区形成晶体管的源区和漏区。该元件区为低掺杂(n)，容易耗尽载流子。根据RESURF法，元件区的电场强度很低，且场效应晶体管能耐高压而无电流击穿。在衬底上元件区只占很小的面积。

Description

一种介质隔离半导体器件及其制造方法
本发明涉及一种介质隔离半导体器件，该器件有降低电场强度的载流子耗尽区，还包括：
—半导体本体；
—元件区，在半导体本体的上表面；
—介质隔离层，用以将半导体本体与元件区划界；
—沉埋区，在元件区内，该沉埋区从元件区上表面向下伸延；
—P-N结，在沉埋区的界定表面上，该表面将所述区与元件区的其余部分划界，所述其余部分掺杂类型与沉埋区掺杂类型相反；以及
—在元件区的半导体元件，在每个沉埋区和元件区的其余部分，至少有一个电连接区；
—其中，降低的电场强度区，因加电压而使载流子耗尽；以及
—一种用来制造该半导体器件的方法。
在众多的不同应用中，要求半导体电路承受较高的电压。在电话交换机的用户线路电路中，就有这种应用的一个例子，瑞典的老式电话交换机中，要给用户线路加48V电压，而现代采用半导体技术的用户线路电路是适应该电压的。而其他国家却要求更高的电压，例如德国为68V，还有，半导体电路的其他应用还可能使用更高的电压，例如400V或以上电压。
因很高电压而来的一个问题是电场强度可能会超过某一元件区内半导体材料的临界场强。如果电流不予限制，这可能造成电流击穿，破坏半导体材料。同样的高场强问题还出现在想用作运算或计算电路的很小快速的半导体元件中。虽然，这些元件与3～5V的低电压相连接，但小尺寸的元件会使电场强度升到高值。
在一些应用中，高电场强度问题明显出在半导体元件的表面，如刊于IEEE，Proceedings from IEDM，1979，pp238-241，J．A．Apples& H.M.J.Vaes：”High Voltage Thin Layer Devices(RESURFDevices)”一文所述，该文内容将被引用于本说明书中。半导体元件包括有PN结的表面层，在给定电压下，达到PN结材料的临界电场强度。PN结的一侧，表面层掺杂较低，因表面层很薄，该低掺杂部分可能耗尽载流子。外加电压沿元件表面分布在很长范围，因此，最大场强仍低于击穿场强值。这个现象在半导体技术领域中是众所周知的，并已有专用的缩写RESURF(REduced SURface Field低表面场)。Philips.J.Res.35，1～13，1980.J.A.Apples等人：“ThinLayer High-Voltage Devices”详细地介绍了RESURF技术。该文也被引用于本说明书中。
半导体元件中，除上述的电流击穿问题外，还有安装在共同半导体衬底上的分立元件以不希望有的方式互相影响的问题，这就是熟知的使元件彼此隔离方法，以克服这个问题，例如，按欧洲专利申请EP-A1-0,418,737所描述的方法来克服。按照这个在先的公开文件，一半导体衬底设置一氧化过的表面，构成为隔离层，其上安装很薄的单晶半导体材料圆片。该单晶圆片被刻蚀出多个槽，这些槽向下延伸到隔离层，并且将槽的侧壁表面予以氧化，这些槽又填以多晶半导体材料。半导体元件就制作在这样形成的介质隔离的盒形区域内。这些元件有外部互连线，该互连线与重掺杂的互连层连接，而重掺杂互连层在各个元件之下，各盒形区域底部，直接与隔离氧化层邻接。可以列举各种不同类型的元件，例如场效应晶体管和双极晶体管。
欧洲专利申请，039156 A2描述了另一种制作有介质隔离区半导体衬底的方法。该隔离区通过重复刻蚀衬底和涂敷半导体材料产生。介质隔离是由氧化过的半导体材料构成，各区都有轻掺杂区域，其中形成有用的元件，而重掺杂连接层位于所述的元件之下且靠着介质隔离层。
常见的一种元件类型是所谓的JFET(结场效应晶体管)例如，在S.M.Sze所著的半导体元件课本：“Physics of SemiconductorDevices”，第二版，第6.1和6.2章，对此作过描述。这本书由JohnWiley&Sons Inc.1981出版。场效应晶体管JFET是按熟知的技术，采用在相互的顶部安置分立的半导体来制作，而在介质隔离区内制作这些晶体管则是一个相当复杂的工艺过程。
根据一个目的，本发明是解决设置半导体元件，例如上述的JFET晶体管的问题，使各个半导体元件能容易地制作在半导体衬底上的介质隔离盒状元件区内。该盒状元件区有电绝缘的底面，且被形成垂直介质绝缘层的盒壁围绕。元件区由预定类型掺杂材料作很轻的掺杂，既可P型也可N型掺杂。该元件有两个片状子区，该子区沿元件区两相互对立的侧边绝缘层伸延。这些子区用与元件区所用掺杂材料类型相反的掺杂材料类型掺杂，使元件区与片状子区间形成P-N结。这些子区可用于，例如，构成JFET晶体管的栅区。这两个片状子区也可互相连结构成以相同掺杂材料类型共同掺杂的连续U-形区。这样的连续区可用于各种各样的元件或元件组合。
各片状子区及其间的连接可以经过所述元件区表面，通过向下扩散或注入掺杂材料到元件区而实现。所以，这样的掺杂区能很容易地制作在介质绝缘的元件区内。这些掺杂区还能很容易地在掺杂过程中，通过适当选用掩模结构简单地得到所需构形。
本发明的另一个目的是解决在限定的介质隔离元件区内，制作耐压元件的问题。
在元件区内的各元件有给元件加电压的电互连线。上述的片状子区和元件区其余部分之间的PN结，借助于这些电压被反向偏置。根据上述的RESURF法，这就是使部分元件区载流子被耗尽，因此，所加电压将分布在元件区内一个很大的范围。所以，元件区的电场强度会降低，仍能维持在半导体材料的击穿场强以下。该元件区和各片状子区含掺杂物浓度都很低，因而能容易耗尽载流子。
参照例举的各实施例以及参照各附图，现在将更详细地描述本发明，其中
图1是一个本发明元件的透视图；
图2是图1所示该元件的剖视图；
图3表示从上面看图1元件；
图4说明从上面看图1所示元件的另一个实施例；
图5说明含有两个串联晶体管的电路；
图6是图5所示本发明晶体管的剖视图；
图7说明从上面看图6的晶体管；以及
图8-14是说明制造图1所示晶体管的各个方法步骤的剖视图。
图1是一个本发明元件，即场效应晶体管JFET的透视图，该图中仅局部显示JFET。将半导体衬底1，这里为硅衬底的上表面氧化，形成二氧化硅介质绝缘层2。制作在该层2上的是单晶硅片3，它的n型载流子浓度相当低，图中标示为n。该单晶片3厚度为A1，在所说明的实施例场合下，A1＝6μm。该衬底1、层2和片3构成半导体本体，而半导体本体含有细长的元件区4。这个元件区做在晶片3内，并且通过由二氧化硅和多晶硅构成的介质绝缘层5，与围绕的区域4a分开。绝缘层5从单晶片3表面向下延伸到介质绝缘层2，从而完全包围着含有结型场效应晶体管JFET的元件区4。因而该元件区是一个盒状的，完全与围绕的半导体本体部分电隔离的半导体区。为清楚起见，绝缘层5的一部分，还有包围区4a的部分都已经从图中除去。场效应晶体管JFET包括由两个片状区G1组成的栅区，该区G1掺以图中标为P的P型载流子。该片状区G1彼此相对，位于相应的元件区4的长边的中间，并靠着介质绝缘层5。该区G1从元件区4的表面向下在所说区中伸至深度A2，在图示的情况下，至深度A2-4μm。每个栅区G1各有相应的P+型重掺杂连接区G2用作外部电连接6，为清楚起见，仅示意性地示出该连接6。PN结10设置在栅区G1和元件区4其余部分之间的交界区域内。对场效应晶体管JFET来说，元件区4的一端有一n+型重掺杂的源区S2，而所述区的另一端有一n+型重掺杂的漏区D2。源区S1和漏区D2还是场效应晶体管JFET的电连接区，并且各有一个外部电连接7，图中已示意性示出。
图2是图1线段A-A处得到的场效应晶体管JFET的剖视图。该图说明元件区4有两个与介质隔离层5邻接的栅区G1。图中示出了栅连接区G2，还有源区S2，虽然后一区域并不在剖面线A-A上。图2还表示出元件区4表面的二氧化硅电绝缘保护层8。图1中未示出的保护层8包括有为外部电连线6和7的开孔9。另一方面，图中虚线L1所指的片状栅区G1可以从元件区4的表面垂直向下伸到介质绝缘层2。
图3是该场效应晶体管JFET的俯视图，其中包括元件区4、绝缘层5、有栅连接区G2的两个栅区G1、源连接区S2以及漏连接区D2。栅电压VG加到外连线6，而源电压VS和漏电压VD分别加到外部连线7。通常的工作条件下，这些电压可以为，例如：
VG＝0V(接地)
VS＝0V
VD＝400V这些电压使PN结10反偏，而形成耗尽区D10。这个区伸展成两枝，如图的链线L2所示。在上述的电压VD＝400V下，这两枝相互合并成共同的耗尽区范围，如链线L3所示。使耗尽区电场的电场强度E仍然能够保持在临界击穿场强，例如硅，ECR=3×105V/cm以下，具有相当高安全度。这是可以实现的，因为元件区4的半导体材料掺杂很低，所以很容易耗尽载流子的缘故。应注意的是，部分栅区G1，特别是靠近漏区D2的那部分栅区是载流子耗尽的。
图4说明本发明的另一个实施例，表示为一种场效应晶体管JFET1。与上述一样，元件区4电气上由介质绝缘层5界定。源区S2位于元件区的一端，而漏区D2位于元件区另一端。如上所述，场效应晶体管JFET1包括两个片状栅区G11，从所述区表面向下延伸到元件区4中，每个栅区G11位于各个元件区4长边的中部，而各所述栅区的后侧边则靠着绝缘层5。栅区G区掺杂P相当低，而每个栅区G11还有一重掺杂，P+连接区G12。每个栅区G11各有面向元件区4的PN结11。与栅区G1不同的是，本实施例的栅区G11，在靠近源区S1那端相当厚，厚度为t1，而靠近漏区D2端相当薄，厚度为t2。当将电压VG、VS和VD分别加到栅、源和漏连线6和7时，PN-结11反偏，而在各栅区G11形成耗尽区D11。由于场效应晶体管的栅区G11呈锥形，所以，耗尽区D11形状不同于图3实施例的场效应晶体管JFET的耗尽区D10。
上面已经描述了介质绝缘元件区4中的场效应晶体管JFET和JFET1。根据本发明，还可以在元件区4内配置两个或更多的串联半导体元件。图5示意性地说明第一场效应晶体管DMOS3与第二场效应晶体管JFET4串联。该晶体管DMOS3的栅区G3与外部连线31连接，而源区S3与外部电连线32连接。该源区S3还与晶体管JFET4的栅区G4连接，晶体管JFET4的源区S4又与晶体管DMOS3的漏区D2连接。最终，晶体管JFET4的漏区D4与外部电连线41相连。
图6和图7用来说明元件区4内形成的两个场效应晶体管DMOS3和JFET4，图7是俯视图，而图6则是图7虚线B-B处的剖视图。图6实施例中，n-掺杂的元件区4为介质绝缘层5所围绕，其上表面则覆盖着二氧化硅介质绝缘层35，还包括电连接的开孔38。晶体管DMOS3有相当低的P-掺杂区33，从所述区表面向下伸入元件区4。该区33位于元件区4的一端，且在元件区的余部邻接的表面有个PN结37。源区S3由在区33表面的重掺杂n+区构成，而外部电连线32与源区S3相连。一重掺杂P+接触区39靠近源区S3且形成该区33的电接触。常规工作条件下，电接触区39与源区S3短路，如虚线连线SS所示。二氧化硅，即所谓栅氧化物的极薄层34位于源区S3一侧的元件区表面上。该栅氧化层34在区33表面，从源区S3的边缘延伸在PN结37上面，并且稍稍延伸到元件区4的负性掺杂部分。晶体管DMOS3的沟道区36处于栅氧化层34下。栅极G3是由位于栅氧化层34顶部的掺杂多晶硅层及该氧化层35构成，且又与外部电连接线31相连。晶体管DMOS3的漏区D3位于沟道区36外侧的元件区4中，直接与PN-结37连接。该漏区D2也成为场效应晶体管JFET4的源区S4。这个场效应晶体管的栅区是由两个P-掺杂材料很低的片状区G4构成，其中每个所述区都沿元件区4两相互对立的长边之一伸延。该片状区G4相当于参照图1上面已详加描述的片状栅区G1。这些片状区，如图6虚线所示，其一端都与低掺杂P区33连接。每个栅区G4都有各自的重掺杂P+栅连接区G41，而G41又与重掺杂P+区39相连，如图7所示。晶体管JFET4的漏区D4是由在元件区4的另一端的重掺杂n+区构成，而该漏区D4又与电连线41相连。
图7是表示俯看的晶体管DMOS3和JFET4，而且除去了所附的介质绝缘层35与栅区G3，以便清楚地现出各晶体管的其他各部件。该区39与引向栅区G4并构成这些区的电连接线的栅连接区G41相连。栅氧化层34覆盖晶体管DMOS3的沟道区36和PN结37。共用的漏区D3和源区S4延伸在栅区G4之间的PN-结37上。该图说明这个栅区G4如何与P-掺杂区33连接，而又靠着沿元件区4两长边的绝缘层5。此外还表示出晶体管JFET4的漏区D4。
片状栅区G4之间的很低n-掺杂的元件区4，通过晶体管DMOS3和JFET4的连线与外加电压相连，会使载流子耗尽。图7的虚线指明为晶体管DMOS3和JFET4的耗尽区DR4，当源区S3和栅区G3都与地电位0V连接，而漏区D4与+100V电压连接时，就会出现这样的耗尽区DR4。如上所述，电接触区39与源连接区S3短路。由线C显示该电场强度E＝1×105v/cm，该强度远在冒着使材料被电流击穿风险的硅临界场强ECR＝3×105V/cm之下。
现在，将参照图8～14，通过实施例描述上述元件的制造方法。所用的原材料是所谓的键合片，它含有硅衬底1、绝缘氧化层2以及单晶硅片3，如图8所示。这种键合片可用，例如上述引用的欧洲专利申请号EP-0,418,737所述的方法生产，也可以是市上现售的。根据图9，晶片3的上表面涂敷上光刻胶层51，以预定图样曝光和显影，使在该层51上形成开孔52。采用等离子刻蚀法，通过这些开孔，刻蚀该绝缘层2，形成深槽53，而后除去光刻胶51。根据图10，氧化各槽53的侧面来形成二氧化硅覆层54，而各槽53的余部再填以多晶硅55。盒状元件区4就是用这种方法从单晶片3的围绕部分4a分出。参照图1，上面陈述的二氧化硅层54和多晶硅55共同构成了介质隔离层5，如图11所示，该晶片3再盖上有两个开孔57的新光刻胶掩模56，图中仅表示其中的一个开孔。开孔57具有狭细长形，沿元件区4的长边靠近介质隔离层伸延。通过这些开孔57实施用正性掺杂材料掺杂，以便获得两个片状栅区G1。除去掩模57，再施加另一个光刻掩模58，如图12所示。通过掩模58的开孔59，实施栅连接区G2的正性重掺杂。除去掩模58，再施加又一个光刻胶掩模60，如图13所示。掩模60有开孔61，通过该开孔实施源区52和漏区D2的负性重掺杂。此后，除去掩模60，再氧化单晶片3表面，来形成绝缘二氧化硅层8，如图14所示。这个层8覆盖的光刻胶掩模62，通过该掩模的开孔63刻蚀该层8中的连接区开孔9。除去掩模62，再给元件制作上述的外部连线6和保护层。图中没有表示出连线和保护层。
为简单起见，栅区G1、源区S2和漏区D2跟叙述制造方法一起，都已表示在同一剖面图中，而不管事实上这些区彼此作了相对横向移动。还应细心注意的是，全部制造各个步骤，例如，氧化、应用掩模、掺杂材料的扩散和刻蚀，对本技术领域的技术人员来说都是众所周知的。
本发明方法的新颖特征，例如，在于以简单的方式在隔离元件区4制作场效应晶体管JFET的可能性，在于本晶体管的结构由简单地选用三块掩模56、58和60确定的结构，还在于简化制造方法的变更，例如，修改掩模结构，就能大量生产各种类型的元件。
前言中已说过，高场强也可能发生在要用作运算或计算电路的元件中，即使元件只与3至5V级的电压相连。这些元件含有高浓度的掺杂材料，尺寸又小、工作速度很快。例如，这种元件的厚度，相当于图1的距离A1，可以仅约0.1μm。本发明也可以应用于那些对元件尺寸来说，高电压连接的元件。可以说，在这种薄元件的情况下，上述的隔离层5可用称之为局部氧化法(LOCOS)，一种相当简单的隔离法制作的层来代替。
本发明针对硅元件已作了举例说明，不过应该知道，其他半导体材料，诸如锗和砷化镓之类也都同样可用。实施例中指称的掺杂类型p和n可以颠倒过来而不会离开本发明的范围。
本发明元件，除耐压性外，还有许多优点。通过以上述方式应用RESURF技术，使外加电压分布于元件的很大部分。因此，如上所述，本元件只需占用衬底的很小表面区域。此外，本元件做薄了有好处，使各元件能用所说明的各个隔离层5和2横向绝缘。其结果进一步减小衬底所需的空间。实施本发明时，安置一定数量元件的半导体衬底的必要表面面积，与早期已知技术比较，至少可以减小一半。特别有利的情况是，例如，各用户都有自己的线路电路的电话系统中的用户线路电路。
本发明能够取得的其他优点是，容易制作元件，因为这些元件都做在抛光的半导体层上，还因为其形状由选用的光刻胶掩模来决定。

Claims (8)

1.一种介质隔离的半导体器件，包括：
—一半导体本体(1，2，3)
—一元件区(4)，位于半导体本体的上表面；
—一介质隔离层(2，5)，使元件区(4)与半导体本体分界；
—一沉埋区(G1)，位于元件区(4)内，该沉埋区从元件区的上表面向下伸延；
—一PN-结(10)，位于沉埋区(G1)的界定表面上，该表面将所述区同元件区(4)的其余部分划界，而所述其余部分掺杂(n)类型与沉埋区(G1)掺杂(p)类型相反；以及
—一半导体元件(JFET)，位于元件区(4)内，该半导体元件在每个沉埋区(G)和元件区(4)的其余部分至少都有一个电连接区(G2、S2、D2)；
其特征在于：
—该元件区(4)有两个相互对置的侧边，通过介质隔离层(2，5)，将元件区(4)与半导体本体(1，2，3)分界；
—还在于该沉埋区包括两个互相对置的片状子区(G1)，该子区(G)在上述的元件区(4)两对边，沿介质隔离层(2)从元件区(4)的上表面，向下伸入所述区，所述子区(G1)具有相当低的掺杂材料(p)浓度；
—在于该元件区(4)，在相互对置的子区(G1)之间的区域具有相当低的掺杂材料(n)浓度。
2.按照权利要求1的介质隔离器件，其特征在于，片状子区(G11)，其一端的厚度(t1)比另一端的大。
3.按照权利要求1的介质隔离器件，其特征在于，该片状子区(G1、G11)都有重掺杂(P+)的电连接区(G2、G12)。
4.按照权利要求1、2或3的介质隔离器件，其特征在于，该片状子区(G1)包括场效应晶体管(JFET)的栅区，其中，在元件区(4)各端，电连接区包括一个与元件区其余部分有相同掺杂类型(n)的重掺杂(n+)区，这些连接区分别形成场效应晶体管的源区(S2)和漏区(D2)。
5.一种介质隔离的半导体器件，包括：
—一半导体本体(1，2，3)；
—一元件区(4)，位于半导体本体的上表面；
—一介质隔离层(2，5)，使元件区(4)与半导体本体分界；
—一沉埋区(33，G4)，位于元件区(4)内，该沉埋区从元件区的上表面向下伸延；
—一PN-结(10)，位于沉埋区(33，G4)的界定表面上，该表面将所述区同元件区(4)的其余部分划界，而所述其余部分掺杂(n)类型与沉埋区(33，G4)掺杂(P)类型相反；以及
—一第一场效应晶体管(DMOS)，它与第二场效应晶体管(JFET4)串联连接，该第一和第二晶体管在各个沉埋区(33，G4)和元件区(4)的其余部分中各至少有一个电连接区(39，S3，G41，D4)；
其特征在于：
—元件区(4)有两个相对侧，该相对侧被介电隔离层(2，5)从半导体本体(1，2，3)划出；
—沉埋区包括两个相对的片状子区(G4)，它在元件区(4)的前述相对侧处从元件区(4)的上表面沿介电隔离层(2)向下延伸进入所述区，所述子区(G4)具有相对低浓度的掺杂材料(P)；
—元件区(4)至少在相对的子区(G4)之间具有相对低浓度的掺杂材料(n)；
—沉埋区(33，G4)包括在元件区(4)一端的一个相当低掺杂(P)的连接区(33)；
—两个片状子区(G4)都在一端与所述的低掺杂连接区(33)相连；
—第1场效应晶体管(DMOS3)有一与元件区(4)其余部分相同掺杂类型(n)的高掺杂(n+)源区(S3)，所述源区(S3)位于连接区(33)内；
—连接区(33)有一个与沉埋区(33，G4)相同掺杂类型(P)的重掺杂(P+)接触区(39)；
—第1场效应晶体管(DMOS3)有一沟道区(36)，该沟道区(36)位于连接区(33)内的源区(S3)与元件区(4)之间所述区的表面处；
—沟道区(36)其表面装有电绝缘栅氧化层(34)，而栅氧化层(34)带有导电的栅区(G3)；
—第2场效应晶体管(JFET4)在元件区(4)的另一端有重掺杂(n+)的漏区(D4)，而该漏区有与元件区(4)其余部分相同的掺杂类型(n)；
—第2场效应晶体管(JFET4)有一栅区，该栅区包括片状子区(G4)，各所述子区都有各自的栅连接区(G41)，与连接区(33)的电接触区(39)相连；以及
—在元件区(4)内，靠近连接区(33)的片状子区(G4)之间的那个区域包括第1场效应晶体管(DMOS3)的漏区(33)和第2场效应晶体管(JFET4)的源区(S4)。
6.一种制造介质隔离半导体器件的方法，所述方法包括下列各步骤：
—氧化半导体衬底(1)的表面，以形成电绝缘氧化物层(2)；
—将掺以第1掺杂材料类型(n)的单晶半导体片施加到氧化层(2)上；
—借助于围绕元件区，且从单晶片(3)表面向下伸到绝缘氧化层(2)的介质绝缘层(5，54)，在单晶片内定界元件区(4)；
—在整个元件区(4)施加设有凹口(57)的第1掩模(56)，该凹口(57)包括两个细长的开孔，该开孔沿介质绝缘层(5，54)的长边，也沿元件区(4)彼此对置的两侧边伸延；
—通过凹口(57)，施加与第1掺杂材料类型(n)相反的第2掺杂材料类型(P)，其中为在元件区中产生沉埋区，而沉埋区包括两个位于元件区(4)对边的片状子区(G1)；
—整个元件区(4)上施加至少一个设有预定开孔(59，61)的第2掩模(58，60)；以及
—通过预定的开孔(59，61)，供给预定类型的掺杂材料，来制作元件区(4)中的半导体元件(JFET)的电连接区(G2、D2、S2)。
7.按照权利要求6的制造介质隔离半导体器件的方法，其特征在于，第1掩模(56)的凹口(57)包括元件区(4)一端的连接孔，该孔将两个细长的凹口(57)的开孔互连。
8.按照权利要求6或7的制造介质隔离半导体器件的方法，其特征在于，该元件区(4)由下列各方法步骤限定：
—将一刻蚀掩模(51)施加到单晶片(3)上，所述刻蚀掩模有用于形成介质绝缘层(5；54；55)的开孔(52)；
—通过刻蚀掩模(51)的开孔(52)，在单晶片(3)中刻槽(53)，所述的槽下伸到半导体衬底(1)的电绝缘层(2)；
—氧化槽(53)的侧边表面，形成半导体氧化层(54)；以及
—槽(53)的余部填以多晶硅半导体材料(55)。
CN94100576A 1993-01-25 1994-01-25 一种介质隔离半导体器件及其制造方法 Expired - Lifetime CN1036740C (zh)

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