CN103678155A

CN103678155A - Memory address mapping processing method and multi-core processor

Info

Publication number: CN103678155A
Application number: CN201210349302.0A
Authority: CN
Inventors: 崔泽汉; 陈明宇; 陈明扬; 阮元
Original assignee: Huawei Technologies Co Ltd; Institute of Computing Technology of CAS
Current assignee: Institute of Computing Technology of CAS; Huawei Cloud Computing Technologies Co Ltd
Priority date: 2012-09-19
Filing date: 2012-09-19
Publication date: 2014-03-26
Anticipated expiration: 2032-09-19
Also published as: CN103678155B

Abstract

The embodiment of the invention provides a memory address mapping processing method and a multi-core processor. The method comprises alternately accessing every set of the first address and the second address of the physical addresses of a memory system through the multi-core processor; obtaining a first average access delay corresponding to every group of the first address and the second address, wherein only the values corresponding to the first address and the second address on two identical address bits are different and the two address bits are the ones aside from row address bits and column address bits of the physical address; determining the address bit of the memory bank of the physical address according to every first average access delay through the multi-core processor. The memory address mapping processing method and the multi-core processor can help obtain the address mapping relation from the physical address and the memory bank of the memory system conveniently and further apply bank partition to a physical computer memory system through the obtained the mapping relation of the memory bank to avoid bank interference sharing of the multi-core processor.

Description

Memory address mapping treatment method and polycaryon processor

Technical field

The embodiment of the present invention relates to computer technology, relates in particular to a kind of memory address mapping treatment method and polycaryon processor.

Background technology

Along with developing rapidly of computer technology, how to avoid polycaryon processor to share the interference causing in cache memory (cache) situation and be widely studied and applied.

In prior art, by page (page coloring) technology that dyes, can realize cache sector (cache partition), by the data of different processes, thread or core or the page, be mapped to different cache set (cache set), to avoid the interference that between different processes, thread or core, cache sharing causes.As long as known cache line (cache line) length, cache size, cache set associative way and operating system page size just can be realized cache sector by page staining technique on entity device.

Inventor finds in realizing the process of the embodiment of the present invention, and the interference problem that polycaryon processor shared drive system is brought still exists, for example the interference of polycaryon processor shared drive bandwidth or shared drive memory bank (bank).Although there is the passage subregion (channel partition) or the research of memory bank subregion (bank partition) to avoid shared bandwidth interference or shared bank to disturb that utilize page staining technique to realize internal memory in the recent period in operating system.But to will utilize a page staining technique realize channel partition or bank partition is applied to entity computer memory system, need physical address in known entities calculator memory system to the address mapping relation of memory system, to comprise that physical address is to the mapping relations of passage (channel) or bank.Because the mapping relations of the physical address on entity device to channel or bank are realized by Memory Controller Hub, and Memory Controller Hub manufacturer often can not disclose the mapping method using in its last word, therefore, how to obtain physical address and become technical matters urgently to be resolved hurrily to the address mapping relation of memory system.

Summary of the invention

The embodiment of the present invention provides a kind of memory address mapping treatment method and polycaryon processor.

The memory address mapping treatment method that the embodiment of the present invention provides comprises: in the physical address of polycaryon processor alternate access memory system, respectively organize the first address and the second address, obtain corresponding with every group of first address and the second address the first average access and postpone, described the first address and described two address bits different with described the second address value corresponding on two identical address bits are the address bit except row address bit and column address bit in each address bit of described physical address; Polycaryon processor postpones according to each first average access, determines the bank-address position of described physical address.

Further, described polycaryon processor postpones according to each first average access, determines the bank-address position of described physical address, comprising: polycaryon processor, according to access delay time length, postpones to divide into groups to described each first average access; If described each first average access postpones to be divided into a plurality of groups, one group of the longest two corresponding address bit XOR of access delay time are treated to the first set, the described bank-address position of determining described physical address comprises in described the first set and in each address bit of described physical address all address bits except described row address bit, described column address bit and described time delay the longest one group of corresponding described two address bit; If described each first average access postpones to be divided into a group, determine that the described bank-address position of described physical address comprises all described two address bits.

Further, before respectively organizing the first address and the second address in the physical address of described polycaryon processor alternate access memory system, also comprise: in polycaryon processor alternate access physical address, respectively organize the 3rd address and the four-address, obtain second average access corresponding with every group of the 3rd address and the four-address and postpone, described the 3rd address is different from a described four-address value corresponding on an identical row address bit and a non-row address bit; Polycaryon processor postpones according to each second average access, determines the column address bit of described physical address.

Further, described polycaryon processor postpones according to each second average access, determine the column address bit of described physical address, comprise: polycaryon processor is according to access delay time length, described each second average access is postponed to divide into groups, the described column address bit of determining described physical address comprise the described access delay time the longest one group of corresponding non-row address bit.

Further, before respectively organizing the 3rd address and the four-address in the physical address of described polycaryon processor alternate access memory system, also comprise: in polycaryon processor alternate access physical address, respectively organize the 5th address and the 6th address, obtain three average access corresponding with every group of the 5th address and the 6th address and postpone, described the 5th address and the 6th address are only different in the value of an identical address bit; Polycaryon processor postpones according to each the 3rd average access, determines the row address bit of described physical address.

Further, described polycaryon processor postpones according to each the 3rd average access, determine the row address bit of described physical address, comprise: polycaryon processor is according to access delay time length, described each the 3rd average access is postponed to divide into groups, determine that the described row address bit in described physical address comprises one group of corresponding address bit that the described access delay time is the longest.

Further, described polycaryon processor postpones according to each first average access, after determining the bank-address position of described physical address, also comprise: the first address sequence in the physical address of a plurality of core Concurrency Access of polycaryon processor memory system, obtain the memory bandwidth that the first address sequence is corresponding, address in described the first address sequence comprises a bank-address position, a plurality of row address bit and a plurality of column address bit, and the value in described the first address sequence on the described bank-address position of adjacent address is different; Polycaryon processor, according to each memory bandwidth, is determined the channel address position of described physical address.

Further, described polycaryon processor, according to each memory bandwidth, is determined the channel address position of described physical address, comprising: polycaryon processor, according to the size of described memory bandwidth, divides into groups to described each memory bandwidth; If described each memory bandwidth is divided into a plurality of groups, the described channel address position of definite described physical address comprises one group of corresponding described bank-address position of described memory bandwidth maximum.

Further, described polycaryon processor is according to each memory bandwidth, after determining the channel address position of described physical address, also comprise: the single core of polycaryon processor is accessed the second address sequence in the physical address of described memory system to skip the mode of cache memory, all the other a plurality of cores of described polycaryon processor, with the 3rd address sequence through in physical address described in the mode Concurrency Access of cache memory, obtain the equal access delay in Siping City that described the second address sequence is corresponding; Value on same channel address position is different with address in the 3rd address sequence in address in described the second address sequence, and the value of other address bit of the address in described the second address sequence is constant, the value of other address bit of the address in described the 3rd address sequence constantly changes; Polycaryon processor, according to the equal access delay in Ge Siping City, is determined the Memory Controller Hub address bit of described physical address.

Further, described polycaryon processor, according to the equal access delay in Ge Siping City, is determined the Memory Controller Hub address bit of described physical address, comprising: polycaryon processor, according to access delay time length, divides into groups to the equal access delay in described Ge Siping City; If the equal access delay in described Ge Siping City is divided into a plurality of groups, determine that the described Memory Controller Hub address bit of described physical address comprises one group of corresponding described channel address position that the described access delay time is the longest.

The polycaryon processor that the embodiment of the present invention provides comprises: memory access module, for the physical address of alternate access memory system, respectively organize the first address and the second address; Measurement module, for obtaining corresponding with every group of first address and the second address the first average access, postpone, described the first address and described two address bits different with described the second address value corresponding on two identical address bits are the address bit except row address bit and column address bit in each address bit of described physical address; Analysis module, for postponing according to each first average access, determine the bank-address position of described physical address.

Further, described analysis module also for: according to access delay time length, described each first average access is postponed to divide into groups; If described each first average access postpones to be divided into a plurality of groups, one group of the longest two corresponding address bit XOR of access delay time are treated to the first set, the described bank-address position of determining described physical address comprises in described the first set and in each address bit of described physical address all address bits except described row address bit, described column address bit and described time delay the longest one group of corresponding described two address bit; If described each first average access postpones to be divided into a group, determine that the described bank-address position of described physical address comprises all described two address bits.

Further, described memory access module is also respectively organized the 3rd address and the four-address for the physical address of alternate access memory system; Described measurement module also postpones for obtaining the second average access corresponding with every group of the 3rd address and the four-address accordingly, and described the 3rd address is different from a described four-address value corresponding on an identical row address bit and a non-row address bit; Described analysis module, also for postponing according to each second average access, is determined the column address bit of described physical address accordingly.

Further, described analysis module is also for according to access delay time length, described each second average access is postponed to divide into groups, the described column address bit of determining described physical address comprise the described access delay time the longest one group of corresponding non-row address bit.

Further, described memory access module is also respectively organized the 5th address and the 6th address for the physical address of alternate access memory system; Described measurement module also postpones for obtaining the 3rd average access corresponding with every group of the 5th address and the 6th address accordingly, and described the 5th address and the 6th address are only different in the value of an identical address bit; Described analysis module, also for postponing according to each the 3rd average access, is determined the row address bit of described physical address accordingly.

Further, described analysis module also, for according to access delay time length, postpones described each the 3rd average access to divide into groups, and determines that the described row address bit in described physical address comprises one group of corresponding address bit that the described access delay time is the longest.

Further, described memory access module is also for the first address sequence of the physical address with multinuclear form Concurrency Access memory system; Described measurement module is also for obtaining the memory bandwidth that the first address sequence is corresponding accordingly, address in described the first address sequence comprises a bank-address position, a plurality of row address bit and a plurality of column address bit, and the value in described the first address sequence on the described bank-address position of adjacent address is different; Described analysis module, also for according to each memory bandwidth, is determined the channel address position of described physical address accordingly.

Further, described analysis module also, for according to the size of described memory bandwidth, divides into groups to described each memory bandwidth; If described each memory bandwidth is divided into a plurality of groups, the described channel address position of definite described physical address comprises one group of corresponding described bank-address position of described memory bandwidth maximum.

Further, described memory access module is also accessed the second address sequence of the physical address of described memory system for skip the mode of cache memory with monokaryon form, with the 3rd address sequence in physical address described in the multinuclear form process mode Concurrency Access of cache memory; Accordingly: described measurement module is for obtaining the equal access delay in Siping City that described the second address sequence is corresponding, value on same channel address position is different with address in the 3rd address sequence in address in described the second address sequence, and the value of other address bit of the address in described the second address sequence is constant, the value of other address bit of the address in described the 3rd address sequence constantly changes; Accordingly: described analysis module, for according to the equal access delay in Ge Siping City, is determined the Memory Controller Hub address bit of described physical address.

Further, described analysis module also, for according to access delay time length, divides into groups to the equal access delay in described Ge Siping City; If the equal access delay in described Ge Siping City is divided into a plurality of groups, determine that the described Memory Controller Hub address bit of described physical address comprises one group of corresponding described channel address position that the described access delay time is the longest.

The memory address mapping treatment method that the embodiment of the present invention provides and polycaryon processor can obtain physical address easily to the address mapping relation of memory system, the address mapping relation that comprises memory bank bank, and then can use the mapping relations of the bank address obtaining that bank partition is applied to entity computer memory system, to avoid polycaryon processor to share bank, disturb.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 is the process flow diagram of memory address mapping treatment method embodiment mono-of the present invention;

Fig. 2 is the process flow diagram of memory address mapping treatment method embodiment bis-of the present invention;

Fig. 3 is the process flow diagram of memory address mapping treatment method embodiment tri-of the present invention;

Fig. 4 is the process flow diagram of memory address mapping treatment method embodiment tetra-of the present invention;

Fig. 5 is the process flow diagram of memory address mapping treatment method embodiment five of the present invention;

Fig. 6 is the process flow diagram of memory address mapping treatment method embodiment six of the present invention;

Fig. 7 is the process flow diagram of memory address mapping treatment method embodiment seven of the present invention;

Fig. 8 is the process flow diagram of memory address mapping treatment method embodiment eight of the present invention;

Fig. 9 is the process flow diagram of memory address mapping treatment method embodiment nine of the present invention;

Figure 10 is the process flow diagram of memory address mapping treatment method embodiment ten of the present invention;

Figure 11 is that this is the structural representation of polycaryon processor embodiment mono-of the present invention.

Embodiment

For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.

In prior art, the physical address of memory system comprises a plurality of address bits, some address bit in physical address is as the index address position of Memory Controller Hub, some address bit is as the index address position of channel, some address bit is as the index address position of bank, some address bit is as the index address position of row, and some address bit is as the index address position of row.For example, the index address position of Memory Controller Hub is that this address of 0 expression is positioned at Memory Controller Hub 0, is that this address of 1 expression is positioned at Memory Controller Hub 1; The index address position of channel is that this address of 0 expression is positioned at channel0, is that 1 expression is positioned at channel1; The index address position of bank is that this address of 000 expression is positioned at bank0, and the index address position of bank is that this address of 001 expression is positioned at bank1, and by that analogy, the index address position of bank is 111 and represents that this address is positioned at bank7.

A plurality of address bits that the memory address mapping treatment method that the embodiment of the present invention provides and device comprise for definite physical address and the corresponding relation of bank address bit, row address bit, column address bit, channel address bit and memory controller address bit.

Fig. 1 is the process flow diagram of memory address mapping treatment method embodiment mono-of the present invention, and as shown in Figure 1, the memory address mapping treatment method that the present embodiment provides can comprise:

In the physical address of step S 102, polycaryon processor alternate access memory system, respectively organize the first address and the second address, obtain corresponding with every group of first address and the second address the first average access and postpone, the first address and two address bits different with the second address value corresponding on two identical address bits are the address bit except row address bit and column address bit in each address bit of physical address.

Particularly, if row address bit and column address bit in each address bit of the physical address of known memory system, get so two address bits except row address bit and column address bit in each address bit of physical address, these two address bits are for example x position and y bit address position.Construct one group of first address and the second address, the x position of the first address is different from the value of two address x position and y position respectively with the value of y position, and for example 0,0, the two address x is got respectively in the x of the first address, y position, y position gets respectively 1,1.This corresponding value of organizing the first address and second address other address bits except x position and y position is all identical.

Polycaryon processor is to skip the mode of cache memory, and this organizes the first address and the second address alternate access, obtains to organize the first average access corresponding to the first address and the second address with this and postpone.In the embodiment of the present invention, the number of times of alternate access can value be 1,000,000 times or other values, can obtain the first average access more accurately, postpones to be as the criterion, and the embodiment of the present invention does not limit this.

All address bits in above-mentioned x position and y position each address bit of traversal physical address except row address bit and column address bit, when x position is different with present position, y position, form not the first address and the second address on the same group, polycaryon processor is to skip the mode of cache memory, alternate access is respectively organized the first address and the second address, obtains to organize the first address and the second address corresponding each first average access and postpone with each.

Step S104, polycaryon processor postpone according to each first average access, determine the memory bank bank address bit of physical address.

Polycaryon processor obtains with after each is organized the first address and the second address corresponding each first average access and postpones, and can postpone to determine according to each the first average access the bank address bit of physical address.

The memory address mapping treatment method that the present embodiment provides can obtain physical address easily to the mapping relations of the bank address of memory system, and then can use the mapping relations of the bank address obtaining that bank partition is applied to entity computer memory system, to avoid polycaryon processor to share bank, disturb.

Fig. 2 is the process flow diagram of memory address mapping treatment method embodiment bis-of the present invention, as shown in Figure 2, the method that the present embodiment provides is on the basis of above-described embodiment, and polycaryon processor postpones according to each first average access, the memory bank bank address bit of determining physical address, can comprise:

Polycaryon processor, according to access delay time length, postpones to divide into groups to each first average access; If each first average access postpones to be divided into a plurality of groups, one group of the longest two corresponding address bit XOR of access delay time are treated to the first set, the memory bank bank address bit of determining physical address comprise in the first set and each address bit of physical address in all address bits except row address bit, column address bit and time delay the longest one group of two corresponding address bit; If each first average access postpones to be divided into a group, determine that the memory bank bank address bit of physical address comprises all two address bits.

Specifically the memory address mapping treatment method that, the present embodiment provides can comprise:

Step S202, the address bit combination of two of all physical addresss the row address bit except known and column address is formed to set B.For example, by the address bit of physical address, the x position in the address bit except row address bit and column address bit and y position are as a combination, and all x positions and this combination of y bit address position form set B jointly.

Step S204, get the address bit of an x, y position in set B, construct one group of first address and the second address, the x position of the first address is different from the value of two address x position and y position respectively with the value of y position, for example 0,0, the two address x is got respectively in the x of the first address, y position, y position gets respectively 1,1.This corresponding value of organizing the first address and second address other address bits except x position and y position is all identical.

Step S206, polycaryon processor with skip cache memory mode alternate access this organize the first address and the second address, obtain and organize the first average access corresponding to the first address and the second address with this and postpone.

Step S208, judge that whether set B is empty, judges whether the address bit of x, y position has traveled through all combination of address bits in set B.If set B is not sky, repeating step S204, if set B is sky, performs step S210.

Step S210, polycaryon processor obtain to be organized the first address and the second address corresponding each first average access and postpones with each, according to access delay time length, each first average access is postponed to divide into groups.

Step S212, each first average access of judgement postpone whether to be divided into a group, if each first average access postpones to be divided into a plurality of groups, perform step S214, if each first average access postpones to be divided into a group, perform step S216.

Step S214, by two address bits in the combination of address bits in the longest one group of corresponding set B of access delay time, for example x position and y bit address position XOR are treated to the first set, determine that the bank address bit of physical address comprises the address bit in the first set.

Step S216, the memory bank bank address bit of determining physical address comprise all address bits of the set B except the first set.

Fig. 3 is the process flow diagram of memory address mapping treatment method embodiment tri-of the present invention, as shown in Figure 3, the memory address mapping treatment method that the present embodiment provides, on the basis of above-described embodiment, before respectively organizing the first address and the second address, also comprises in polycaryon processor alternate access physical address:

In the physical address of step S302, polycaryon processor alternate access memory system, respectively organize the 3rd address and the four-address, obtain second average access corresponding with every group of the 3rd address and the four-address and postpone, the 3rd address is different from a four-address value corresponding on an identical row address bit and a non-row address bit.

Particularly, if in the memory address mapping treatment method embodiment that Fig. 1 or Fig. 2 provide, row address bit in each address bit of physical address is known, and column address bit is unknown, can get so a non-row address bit except row address bit in each address bit of physical address, for example this non-row address bit is c bit address position, and to get a row address bit be for example r bit address position.Construct one group of the 3rd address and the four-address, the 3rd c position of address is different from the value of four address c position and r position respectively with the value of r position, and for example 0,0, the four address c is got respectively in the c of the 3rd address, r position, r position gets respectively 1,1.The corresponding value of this group the 3rd address and the four-address other address bits except c position and r position is all identical.

Polycaryon processor is to skip the mode of cache memory, and this group the 3rd address and four-address of alternate access, obtains second average access corresponding with this group the 3rd address and the four-address and postpone.In the embodiment of the present invention, the number of times of alternate access can value be 1,000,000 times or other values, can obtain the second average access accurately, postpones to be as the criterion, and the embodiment of the present invention does not limit this.

All address bits in each address bit of traversal physical address of above-mentioned c position except row address bit, when present position, c position is different, form not the 3rd address and the four-address on the same group, polycaryon processor is to skip the mode of cache memory, alternate access is respectively organized the 3rd address and the four-address, obtains each second average access corresponding with each group the 3rd address and the four-address and postpones.

Step S304, polycaryon processor postpone according to each second average access, determine the column address bit of physical address.

Polycaryon processor obtains after each second average access delay corresponding with each group the 3rd address and the four-address, can postpone to determine according to each the second average access the column address bit of physical address.

Step S 102 is similar to corresponding step in Fig. 1 with step S 104, repeats no more herein.

The memory address mapping treatment method that the present embodiment provides, by first obtaining physical address to the mapping relations of the column address of memory system, obtain again physical address to the mapping relations of the bank address of memory system, and then can use the mapping relations of the bank address obtaining that bank partition is applied to entity computer memory system, to avoid polycaryon processor to share bank, disturb.

Fig. 4 is the process flow diagram of memory address mapping treatment method embodiment tetra-of the present invention, as shown in Figure 4, the method that the present embodiment provides is on basis embodiment illustrated in fig. 3, and polycaryon processor postpones according to each second average access, the column address bit of determining physical address, comprising:

Polycaryon processor is according to access delay time length, and each second average access is postponed to divide into groups, the column address bit of determining physical address comprise the access delay time the longest one group of corresponding non-row address bit.

Specifically the memory address mapping treatment method that, the present embodiment provides can also comprise before the method that Fig. 1 or Fig. 2 embodiment provide implementing:

Step S402, the address bit of all physical addresss the row address bit except known is formed to set C.

Step S404, get the r address bit in row address bit, get a c address bit in set C and construct one group of the 3rd address and the four-address: the 3rd address is only different with value on r address bit at c address bit with the four-address, for example the c address bit of the 3rd address and r address bit values are all 0, two address c address bit and r address bit values are all 1, and the corresponding value of other address bits is all identical.

Step S406, polycaryon processor, to skip this group of mode alternate access the 3rd address and four-address of cache memory, obtain second average access corresponding with this group the 3rd address and the four-address and postpone.

Whether step S408, judgement set C are empty, judge whether c address bit has traveled through all address bits in set C.If set C is not sky, repeating step S404, if set C is sky, performs step S410.

Step S410, polycaryon processor obtain each second average access corresponding with each group the 3rd address and the four-address to postpone, and according to access delay time length, each second average access is postponed to divide into groups.

Step S412, determine that the column address bit of physical address comprises that one group of second the longest average access of access delay time postpones the address bit in corresponding set C.

Fig. 5 is the process flow diagram of memory address mapping treatment method embodiment five of the present invention, as shown in Figure 5, on the basis of the embodiment that the memory address mapping treatment method that the present embodiment provides provides at Fig. 3 or Fig. 4, respectively organize the 3rd address and the four-address in polycaryon processor alternate access physical address before, also comprise:

In the physical address of step S502, polycaryon processor alternate access memory system, respectively organize the 5th address and the 6th address, obtain three average access corresponding with every group of the 5th address and the 6th address and postpone, the 5th address and the 6th address are only different in the value of an identical address bit.

Particularly, if in the memory address mapping treatment method embodiment that Fig. 3 or Fig. 4 provide, row address bit in each address bit of physical address is unknown, can construct so one group of the 5th address and the 6th address, the 5th address only has the value of r position different from the value of the r position of the 6th address, it is all identical that 1, the five address and the 6th address corresponding value of other address bits except r position is got in the r position that for example 0, the six address is got in the r position of the 5th address.

Polycaryon processor is to skip the mode of cache memory, and alternate access this group the 5th address and the 6th address, obtain three average access corresponding with this group the 5th address and the 6th address and postpone.In the embodiment of the present invention, the number of times of alternate access can value be 1,000,000 times or other values, can obtain the 3rd average access accurately, postpones to be as the criterion, and the embodiment of the present invention does not limit this.

All address bits in the traversal physical address of above-mentioned r position, when present position, r position is different, form not the 5th address and the 6th address on the same group, polycaryon processor is to skip the mode of cache memory, alternate access is respectively organized the 5th address and the 6th address, obtains each three average access corresponding with each group the 5th address and the 6th address and postpones.

Step S504, polycaryon processor postpone according to each the 3rd average access, determine the row address bit of physical address.

Polycaryon processor obtains after each the 3rd average access delay corresponding with each group the 5th address and the 6th address, can postpone to determine according to each the 3rd average access the row address bit of physical address.

Step S302, step S304, step S102 and step S104 are similar with corresponding step in Fig. 3, repeat no more herein.

The memory address mapping treatment method that the present embodiment provides, by first obtaining physical address to the row address of memory system and the mapping relations of column address, obtain again physical address to the mapping relations of the bank address of memory system, and then can use the mapping relations of the bank address obtaining that bank partition is applied to entity computer memory system, to avoid polycaryon processor to share bank, disturb.

Fig. 6 is the process flow diagram of memory address mapping treatment method embodiment six of the present invention, as shown in Figure 6, the method that the present embodiment provides is on basis embodiment illustrated in fig. 5, and polycaryon processor postpones according to each the 3rd average access, the row address bit of determining described physical address, comprising:

Polycaryon processor, according to access delay time length, postpones each the 3rd average access to divide into groups, and determines that the row address bit in physical address comprises one group of corresponding address bit that the access delay time is the longest.

Specifically the memory address mapping treatment method that, the present embodiment provides can also comprise before the method that Fig. 3 or Fig. 4 embodiment provide implementing:

Step S602, the address bit of all physical addresss of the unknown is formed to set R.

Step S604, get set R in a r address bit construct one group of the 5th address and the 6th address: the 5th address is only different from the r address bit value of the 6th address at r address bit, for example the r address bit of the 5th address is 0, the r address bit of the 6th address is 1, and the corresponding value of other address bits is all identical.

Step S606, polycaryon processor, to skip this group of mode alternate access the 5th address and the 6th address of cache memory, obtain three average access corresponding with this group the 5th address and the 6th address and postpone.

Whether step S608, judgement set R are empty, judge whether r address bit has traveled through all address bits in set R.If set R is not sky, repeating step S604, if set R is sky, performs step S610.

Step S610, polycaryon processor obtain each three average access corresponding with each group the 5th address and the 6th address to postpone, and according to access delay time length, each the 3rd average access is postponed to divide into groups.

Step S612, determine that the row address bit of physical address comprises that one group of the 3rd the longest average access of access delay time postpones the address bit in corresponding set R.

Fig. 7 is the process flow diagram of memory address mapping treatment method embodiment seven of the present invention, as shown in Figure 7, the memory address mapping treatment method that the present embodiment provides is on the basis of above-described embodiment, polycaryon processor postpones according to each first average access, after determining the memory bank bank address bit of physical address, can also comprise:

The first address sequence in the physical address of step S702, a plurality of core Concurrency Access of polycaryon processor memory system, obtain memory bandwidth, address in the first address sequence comprises a bank-address position, a plurality of row address bit and a plurality of column address bit, and the value in the first address sequence on the bank-address position of adjacent address is different.

Particularly, in the situation that the bank address bit of physical address is determined, can construct first address sequence, each address in the first address sequence comprises the bank-address position b address bit that position is identical, m row address bit and n column address bit.Wherein the value of m+n should be greater than a threshold value, and for example m+n > 20, to guarantee that the size of constructed address sequence is greater than the size of cache memory Cache.In the first address sequence, the value of the b address bit of adjacent address is different, and for example in the first address sequence, the b address bit of odd positions address gets 0, and the b address bit of the address of even number position gets 1; The m of each address in a first address sequence row address bit and n column address bit sequentially increase progressively, until travel through all array configurations, first m row address bit in the first address sequence all gets 0, n column address bit is incremented to one by one and entirely gets 1 from entirely getting 0, then the value of m row address increases by 1, n column address bit is incremented to one by one and entirely gets 1 from entirely getting 0, by that analogy, until m row address bit and n column address bit value are 1 entirely.

A plurality of cores of polycaryon processor are in the mode through cache memory, and Concurrency Access the first address sequence, can access the different fragments of the first address sequence with different IPs, obtain the access execution time and then obtain memory bandwidth.

B address bit in above-mentioned the first address sequence travels through all bank address bits, when b address bit present position is different, a plurality of cores of polycaryon processor are in the mode through cache memory, Concurrency Access the first address sequence, obtains each memory bandwidth corresponding with the b address bit of variant position.

Step S704, polycaryon processor, according to each memory bandwidth, are determined the passage channel address bit of physical address.

Polycaryon processor obtains after each memory bandwidth, can determine according to each memory bandwidth the channel address bit of physical address.

Step S102 is similar to corresponding step in Fig. 1 with step S104, repeats no more herein.

The memory address mapping treatment method that the present embodiment provides can obtain physical address easily to the mapping relations of the bank address of memory system, thereby obtain physical address to the mapping relations of the channel address of memory system, and then can use the mapping relations of the bank address obtaining and the mapping relations of channel address that bank partition and channel partition are applied to entity computer memory system, with the interference of avoiding the shared bank of polycaryon processor and channel to cause.

Fig. 8 is the process flow diagram of memory address mapping treatment method embodiment eight of the present invention, and as shown in Figure 8, the method that the present embodiment provides is on basis embodiment illustrated in fig. 7, and polycaryon processor, according to each memory bandwidth, is determined the channel address position of physical address, comprising:

Polycaryon processor, according to the size of memory bandwidth, divides into groups to each memory bandwidth;

If each memory bandwidth is divided into a plurality of groups, the passage channel address bit of definite physical address comprises one group of corresponding memory bank bank address bit of memory bandwidth maximum.

Specifically the memory address mapping treatment method that, the present embodiment provides can also comprise after implementing the method that Fig. 1 or Fig. 2 embodiment provide:

Step S802, the bank address bit of all physical addresss is formed to set T.

Step S804, get a b address bit in m row address bit, a n column address bit and set T, structure the first address sequence.

Each address in the first address sequence comprises the bank-address position b address bit that position is identical, m row address bit and n column address bit.Wherein the value of m+n should be greater than a threshold value, and for example m+n > 20, to guarantee that the size of constructed address sequence is greater than the size of cache memory Cache.In the first address sequence, the value of the b address bit of adjacent address is different, and for example in the first address sequence, the b address bit of odd positions address gets 0, and the b address bit of the address of even number position gets 1; The m of each address in a first address sequence row address bit and n column address bit sequentially increase progressively, until travel through all array configurations, first m row address bit in the first address sequence all gets 0, n column address bit is incremented to one by one and entirely gets 1 from entirely getting 0, then the value of m row address increases by 1, n column address bit is incremented to one by one and entirely gets 1 from entirely getting 0, by that analogy, until m row address bit and n column address bit value are 1 entirely.

A plurality of cores of step S806, polycaryon processor, with mode Concurrency Access the first address sequence through cache memory, obtain the memory bandwidth corresponding with b address bit.

Whether step S808, judgement set T are empty, judge whether b address bit has traveled through all address bits in set T.If set T is not sky, repeating step S804, if set T is sky, performs step S810.

Step S810, polycaryon processor obtain each memory bandwidth corresponding with each b address bit, according to memory bandwidth size, each memory bandwidth are divided into groups.

Step S812, judge whether each memory bandwidth is divided into a group, if each memory bandwidth is divided into a plurality of groups, performs step S814, if each memory bandwidth is divided into a group, perform step S816.

Step S814, the channel address bit of determining physical address comprise the address bit in the set T that one group of memory bandwidth of memory bandwidth maximum is corresponding.

Step S816, determine and in physical address, do not comprise channel address bit.If when each memory bandwidth is divided into a group, memory system only has unique channel, so without channel address.

Fig. 9 is the process flow diagram of memory address mapping treatment method embodiment nine of the present invention, as shown in Figure 9, the memory address mapping treatment method that the present embodiment provides provides on the basis of embodiment at Fig. 7 or Fig. 8, polycaryon processor is according to each memory bandwidth, after determining the passage channel address bit of physical address, can also comprise:

The single core of step S902, polycaryon processor is to skip the second address sequence in the physical address of mode access memory system of cache memory, all the other a plurality of cores of polycaryon processor, with the 3rd address sequence through in the mode Concurrency Access physical address of cache memory, obtain the equal access delay in Siping City that the second address sequence is corresponding; Value on same channel address position is different with address in the 3rd address sequence in address in the second address sequence, and the value of other address bit of the address in the second address sequence is constant, the value of other address bit of the address in the 3rd address sequence constantly changes.

Particularly, in the situation that the channel address bit of physical address is determined, can construct the second address sequence and the 3rd address sequence, the second address sequence and the 3rd address sequence all comprise a same channel address bit, and this channel address bit in the second address sequence is different from the value of this channel address bit in the 3rd address sequence.For example the channel address bit of all addresses in the second address sequence, is assumed to be a address bit, and value is all 0; In the 3rd address sequence, a address bit value of all addresses is all 1.

The single core of polycaryon processor is accessed the second address sequence in physical address to skip the mode of cache memory, and other address bit except a address bit of the address in access process in the second address sequence remains unchanged; All the other a plurality of cores of polycaryon processor are with the 3rd address sequence through in the mode Concurrency Access physical address of cache memory, address in access process in the 3rd address sequence other address bit except a address bit continues to change, and can change continuously also can random variation.A plurality of core Concurrency Access the 3rd address sequences are mainly in order to disturb the access of single core to the second address sequence.Polycaryon processor obtains the access execution time of single core to the second address sequence, and then obtains Siping City equal access delay corresponding with the second address sequence.

A address bit in above-mentioned the second address sequence and the 3rd address sequence travels through all channel address bits, when a address bit present position is different, can obtain the equal access delay in Ge Siping City corresponding to a address bit of variant position.

Step S904, polycaryon processor, according to the equal access delay in Ge Siping City, are determined the Memory Controller Hub address bit of physical address.

Polycaryon processor obtains after the equal access delay in Ge Siping City, can determine according to the equal access delay in Ge Siping City the Memory Controller Hub address bit of physical address.

Step S102, step S104, step S702 and step S704 are similar with corresponding step in Fig. 7, repeat no more herein.

The memory address mapping treatment method that the present embodiment provides can obtain physical address easily to the mapping relations of the bank address of memory system and the mapping relations of channel address, thereby obtain the mapping relations of the Memory Controller Hub address of memory system, and then can use the mapping relations of the bank address obtaining, the mapping relations of the mapping relations of channel address and Memory Controller Hub address, by bank partition, channel partition and Memory Controller Hub subregion are applied to entity computer memory system, with the interference of avoiding polycaryon processor shared drive system to cause.

Figure 10 is the process flow diagram of memory address mapping treatment method embodiment ten of the present invention, as shown in figure 10, the method that the present embodiment provides is on basis embodiment illustrated in fig. 9, and polycaryon processor is according to the equal access delay in Ge Siping City, the Memory Controller Hub address bit of determining physical address, comprising:

Polycaryon processor, according to access delay time length, divides into groups to the equal access delay in Ge Siping City; If the equal access delay in Ge Siping City is divided into a plurality of groups, determine that the Memory Controller Hub address bit of physical address comprises one group of corresponding channel address position that the access delay time is the longest.

Specifically the memory address mapping treatment method that, the present embodiment provides can also comprise after implementing the method that Fig. 7 or Fig. 8 embodiment provide:

Step S1002, the channel address bit of all physical addresss is formed to set U.

Step S 1004, get an a address bit in set U, structure the second address sequence and the 3rd address sequence.

The second address sequence and the 3rd address sequence all comprise an a address bit, and a address bit in the second address sequence is different from the value of a address bit in the 3rd address sequence.For example in the second address sequence, a address bit value of all addresses is all 0; In the 3rd address sequence, a address bit value of all addresses is all 1.

The single core of step S1006, polycaryon processor is accessed the second address sequence in physical address to skip the mode of cache memory, all the other a plurality of cores of polycaryon processor, with the 3rd address sequence through in the mode Concurrency Access physical address of cache memory, obtain the equal access delay in Siping City.

Whether step S1008, judgement set U are empty, judge whether a address bit has traveled through all address bits in set U.If set U is not sky, repeating step S1004, if set U is sky, performs step S1010.

Step S1010, obtain the Ge Siping City equal access delay corresponding with each a address bit, according to access delay time length, the equal access delay in Ge Siping City is divided into groups.

Whether step S1012, the equal access delay in Ge Siping City are divided into a group, if the equal access delay in Ge Siping City is divided into a plurality of groups, perform step S1014, if the equal access delay in Ge Siping City is divided into a group, perform step S1016.

Step S1014, determine that the Memory Controller Hub address bit of physical address comprises the address bit in set U corresponding to a longest equal access delay in Zu Siping City of access delay time.

Step S1016, determine and in physical address, do not comprise Memory Controller Hub address bit.If when the equal access delay in Ge Siping City is divided into a group, memory system only has unique Memory Controller Hub, so without Memory Controller Hub address.

Figure 11 is the structural representation of polycaryon processor embodiment mono-of the present invention, and as shown in figure 11, the polycaryon processor 1100 that the present embodiment provides comprises:

Memory access module 1110, respectively organizes the first address and the second address for the physical address of alternate access memory system;

Measurement module 1120, for obtaining corresponding with every group of first address and the second address the first average access, postpone, described the first address and described two address bits different with described the second address value corresponding on two identical address bits are the address bit except row address bit and column address bit in each address bit of described physical address;

Analysis module 1130, for postponing according to each first average access, determine the bank-address position of described physical address.

The polycaryon processor 1100 of the present embodiment, can be for the technical scheme of the embodiment of memory address mapping treatment method shown in execution graph 1, and it realizes principle and technique effect is similar, repeats no more herein.

Above-mentioned analysis module 1130 can also, for according to access delay time length, postpone to divide into groups to described each first average access; If described each first average access postpones to be divided into a plurality of groups, one group of the longest two corresponding address bit XOR of access delay time are treated to the first set, the described bank-address position of determining physical address comprises in described the first set and each address bit of described physical address all address bits except row address bit, described column address bit and described time delay the longest one group of corresponding described two address bit; If described each first average access postpones to be divided into a group, determine that the described bank-address position of described physical address comprises all described two address bits.

Adopt the polycaryon processor 1100 of present embodiment, can be for the technical scheme of the embodiment of memory address mapping treatment method shown in execution graph 2, it realizes principle and technique effect is similar, repeats no more herein.

Memory access module 1110 described above is also respectively organized the 3rd address and the four-address for the physical address of alternate access memory system; Described measurement module 1120 also postpones for obtaining the second average access corresponding with every group of the 3rd address and the four-address accordingly, and described the 3rd address is different from a described four-address value corresponding on an identical row address bit and a non-row address bit; Described analysis module 1130, also for postponing according to each second average access, is determined the column address bit of described physical address accordingly.

Adopt the polycaryon processor 1100 of present embodiment, can be for the technical scheme of the embodiment of memory address mapping treatment method shown in execution graph 3, it realizes principle and technique effect is similar, repeats no more herein.

Analysis module 1130 in a upper embodiment can also be for according to access delay time length, described each second average access is postponed to divide into groups, determine that the described column address bit of described physical address comprises one group of corresponding non-row address bit that the described access delay time is the longest.

Adopt the polycaryon processor 1100 of present embodiment, can be for the technical scheme of the embodiment of memory address mapping treatment method shown in execution graph 4, it realizes principle and technique effect is similar, repeats no more herein.

Memory access module 1110 is also respectively organized the 5th address and the 6th address for the physical address of alternate access memory system; Described measurement module 1120 also postpones for obtaining the 3rd average access corresponding with every group of the 5th address and the 6th address accordingly, and described the 5th address and the 6th address are only different in the value of an identical address bit; Described analysis module 1130, also for postponing according to each the 3rd average access, is determined the row address bit of described physical address accordingly.

Adopt the polycaryon processor 1100 of present embodiment, can be for the technical scheme of the embodiment of memory address mapping treatment method shown in execution graph 5, it realizes principle and technique effect is similar, repeats no more herein.

Analysis module 1130 in a upper embodiment can also be for according to access delay time length, described each the 3rd average access is postponed to divide into groups, determine that the described row address bit in described physical address comprises one group of corresponding address bit that the described access delay time is the longest.

Adopt the polycaryon processor 1100 of present embodiment, can be for the technical scheme of the embodiment of memory address mapping treatment method shown in execution graph 6, it realizes principle and technique effect is similar, repeats no more herein.

Memory access module 1110 is also for the first address sequence of the physical address with multinuclear form Concurrency Access memory system; Described measurement module 1120 is also for obtaining the memory bandwidth that the first address sequence is corresponding accordingly, address in described the first address sequence comprises a bank-address position, a plurality of row address bit and a plurality of column address bit, and the value in described the first address sequence on the described bank-address position of adjacent address is different; Described analysis module 1130, also for according to each memory bandwidth, is determined the channel address position of described physical address accordingly.

Adopt the polycaryon processor 1100 of present embodiment, can be for the technical scheme of the embodiment of memory address mapping treatment method shown in execution graph 7, it realizes principle and technique effect is similar, repeats no more herein.

Analysis module 1130 in a upper embodiment can also, for according to the size of described memory bandwidth, divide into groups to described each memory bandwidth; If described each memory bandwidth is divided into a plurality of groups, the described channel address position of definite described physical address comprises one group of corresponding described bank-address position of described memory bandwidth maximum.

Adopt the polycaryon processor 1100 of present embodiment, can be for the technical scheme of the embodiment of memory address mapping treatment method shown in execution graph 8, it realizes principle and technique effect is similar, repeats no more herein.

Memory access module 1110 is also accessed the second address sequence of the physical address of described memory system for skip the mode of cache memory with monokaryon form, with the 3rd address sequence in physical address described in the multinuclear form process mode Concurrency Access of cache memory; Described measurement module 1120 is for obtaining the equal access delay in Siping City that described the second address sequence is corresponding accordingly, value on same channel address position is different with address in the 3rd address sequence in address in described the second address sequence, and the value of other address bit of the address in described the second address sequence is constant, the value of other address bit of the address in described the 3rd address sequence constantly changes; Described analysis module 1130, for according to the equal access delay in Ge Siping City, is determined the Memory Controller Hub address bit of described physical address accordingly.

Adopt the polycaryon processor 1100 of present embodiment, can be for the technical scheme of the embodiment of memory address mapping treatment method shown in execution graph 9, it realizes principle and technique effect is similar, repeats no more herein.

Analysis module 1130 in a upper embodiment can also, for according to access delay time length, divide into groups to the equal access delay in described Ge Siping City; If the equal access delay in described Ge Siping City is divided into a plurality of groups, determine that the described Memory Controller Hub address bit of described physical address comprises one group of corresponding described channel address position that the described access delay time is the longest.

Adopt the polycaryon processor 1100 of present embodiment, can be for the technical scheme of the embodiment of memory address mapping treatment method shown in execution graph 10, it realizes principle and technique effect is similar, repeats no more herein.

One of ordinary skill in the art will appreciate that: all or part of step that realizes above-mentioned each embodiment of the method can complete by the relevant hardware of programmed instruction.Aforesaid program can be stored in a computer read/write memory medium.This program, when carrying out, is carried out the step that comprises above-mentioned each embodiment of the method; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CDs.

Finally it should be noted that: each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit above; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims

1. a memory address mapping treatment method, is characterized in that, comprising:

In the physical address of polycaryon processor alternate access memory system, respectively organize the first address and the second address, obtain corresponding with every group of first address and the second address the first average access and postpone, described the first address and described two address bits different with described the second address value corresponding on two identical address bits are the address bit except row address bit and column address bit in each address bit of described physical address;

Polycaryon processor postpones according to each first average access, determines the bank-address position of described physical address.

2. method according to claim 1, is characterized in that, described polycaryon processor postpones according to each first average access, determines the bank-address position of described physical address, comprising:

Polycaryon processor, according to access delay time length, postpones to divide into groups to described each first average access;

If described each first average access postpones to be divided into a plurality of groups, one group of the longest corresponding described two address bit XOR of access delay time are treated to the first set, the described bank-address position of determining described physical address comprises in described the first set and each address bit of described physical address all address bits except described row address bit, described column address bit and described time delay the longest one group of corresponding described two address bit;

If described each first average access postpones to be divided into a group, determine that the described bank-address position of described physical address comprises all described two address bits.

3. method according to claim 1 and 2, is characterized in that, before respectively organizing the first address and the second address, also comprises in described polycaryon processor alternate access physical address:

In the physical address of polycaryon processor alternate access memory system, respectively organize the 3rd address and the four-address, obtain second average access corresponding with every group of the 3rd address and the four-address and postpone, described the 3rd address is different from a described four-address value corresponding on an identical row address bit and a non-row address bit;

Polycaryon processor postpones according to each second average access, determines the column address bit of described physical address.

4. method according to claim 3, is characterized in that, described polycaryon processor postpones according to each second average access, determines the column address bit of described physical address, comprising:

Polycaryon processor is according to access delay time length, and described each second average access is postponed to divide into groups, the described column address bit of determining described physical address comprise the described access delay time the longest one group of corresponding non-row address bit.

5. according to the method described in claim 3 or 4, it is characterized in that, before respectively organizing the 3rd address and the four-address in described polycaryon processor alternate access physical address, also comprise:

In the physical address of polycaryon processor alternate access memory system, respectively organize the 5th address and the 6th address, obtain three average access corresponding with every group of the 5th address and the 6th address and postpone, described the 5th address and the 6th address are only different in the value of an identical address bit;

Polycaryon processor postpones according to each the 3rd average access, determines the row address bit of described physical address.

6. method according to claim 5, is characterized in that, described polycaryon processor postpones according to each the 3rd average access, determines the row address bit of described physical address, comprising:

Polycaryon processor, according to access delay time length, postpones described each the 3rd average access to divide into groups, and determines that the described row address bit in described physical address comprises one group of corresponding address bit that the described access delay time is the longest.

7. according to the arbitrary described method of claim 1-6, it is characterized in that, described polycaryon processor postpones according to each first average access, after determining the bank-address position of described physical address, also comprises:

The first address sequence in the physical address of a plurality of core Concurrency Access of polycaryon processor memory system, obtain the memory bandwidth that the first address sequence is corresponding, address in described the first address sequence comprises a bank-address position, a plurality of row address bit and a plurality of column address bit, and the value in described the first address sequence on the described bank-address position of adjacent address is different;

Polycaryon processor, according to each memory bandwidth, is determined the channel address position of described physical address.

8. method according to claim 7, is characterized in that, described polycaryon processor, according to each memory bandwidth, is determined the channel address position of described physical address, comprising:

Polycaryon processor, according to the size of described memory bandwidth, divides into groups to described each memory bandwidth;

If described each memory bandwidth is divided into a plurality of groups, the described channel address position of definite described physical address comprises one group of corresponding described bank-address position of described memory bandwidth maximum.

9. according to the method described in claim 7 or 8, it is characterized in that, described polycaryon processor, according to each memory bandwidth, after determining the channel address position of described physical address, also comprises:

The single core of polycaryon processor is accessed the second address sequence in the physical address of described memory system to skip the mode of cache memory, all the other a plurality of cores of described polycaryon processor, with the 3rd address sequence through in physical address described in the mode Concurrency Access of cache memory, obtain the equal access delay in Siping City that described the second address sequence is corresponding;

Value on same channel address position is different with address in the 3rd address sequence in address in described the second address sequence, and the value of other address bit of the address in described the second address sequence is constant, the value of other address bit of the address in described the 3rd address sequence constantly changes;

Polycaryon processor, according to the equal access delay in Ge Siping City, is determined the Memory Controller Hub address bit of described physical address.

10. method according to claim 9, is characterized in that, described polycaryon processor, according to the equal access delay in Ge Siping City, is determined the Memory Controller Hub address bit of described physical address, comprising:

Polycaryon processor, according to access delay time length, divides into groups to the equal access delay in described Ge Siping City;

If the equal access delay in described Ge Siping City is divided into a plurality of groups, determine that the described Memory Controller Hub address bit of described physical address comprises one group of corresponding described channel address position that the described access delay time is the longest.

11. 1 kinds of polycaryon processors, is characterized in that, comprising:

Memory access module, respectively organizes the first address and the second address for the physical address of alternate access memory system;

Measurement module, for obtaining corresponding with every group of first address and the second address the first average access, postpone, described the first address and described two address bits different with described the second address value corresponding on two identical address bits are the address bit except row address bit and column address bit in each address bit of described physical address;

Analysis module, for postponing according to each first average access, determine the bank-address position of described physical address.

12. polycaryon processors according to claim 11, is characterized in that, described analysis module also for:

According to access delay time length, described each first average access is postponed to divide into groups;

13. according to the polycaryon processor described in claim 11 or 12, it is characterized in that,

Described memory access module is also respectively organized the 3rd address and the four-address for the physical address of alternate access memory system; Accordingly:

Described measurement module also postpones for obtaining the second average access corresponding with every group of the 3rd address and the four-address, and described the 3rd address is different from a described four-address value corresponding on an identical row address bit and a non-row address bit; Accordingly:

Described analysis module also, for postponing according to each second average access, is determined the column address bit of described physical address.

14. polycaryon processors according to claim 13, it is characterized in that, described analysis module is also for according to access delay time length, described each second average access is postponed to divide into groups, the described column address bit of determining described physical address comprise the described access delay time the longest one group of corresponding non-row address bit.

15. according to the polycaryon processor described in claim 13 or 14, it is characterized in that,

Described memory access module is also respectively organized the 5th address and the 6th address for the physical address of alternate access memory system; Accordingly:

Described measurement module also postpones for obtaining the 3rd average access corresponding with every group of the 5th address and the 6th address, and described the 5th address and the 6th address are only different in the value of an identical address bit; Accordingly:

Described analysis module also, for postponing according to each the 3rd average access, is determined the row address bit of described physical address.

16. polycaryon processors according to claim 15, it is characterized in that, described analysis module is also for according to access delay time length, described each the 3rd average access is postponed to divide into groups, determine that the described row address bit in described physical address comprises one group of corresponding address bit that the described access delay time is the longest.

17. according to the arbitrary described polycaryon processor of claim 11-16, it is characterized in that,

Described memory access module is also for the first address sequence of the physical address with multinuclear form Concurrency Access memory system; Accordingly:

Described measurement module is also for obtaining the memory bandwidth that the first address sequence is corresponding, address in described the first address sequence comprises a bank-address position, a plurality of row address bit and a plurality of column address bit, and the value in described the first address sequence on the described bank-address position of adjacent address is different; Accordingly:

Described analysis module also, for according to each memory bandwidth, is determined the channel address position of described physical address.

18. polycaryon processors according to claim 17, is characterized in that, described analysis module also, for according to the size of described memory bandwidth, divides into groups to described each memory bandwidth;

19. according to the polycaryon processor described in claim 17 or 18, it is characterized in that,

Described memory access module is also accessed the second address sequence of the physical address of described memory system for skip the mode of cache memory with monokaryon form, with the 3rd address sequence in physical address described in the multinuclear form process mode Concurrency Access of cache memory; Accordingly:

Described measurement module is for obtaining the equal access delay in Siping City that described the second address sequence is corresponding, value on same channel address position is different with address in the 3rd address sequence in address in described the second address sequence, and the value of other address bit of the address in described the second address sequence is constant, the value of other address bit of the address in described the 3rd address sequence constantly changes; Accordingly:

Described analysis module, for according to the equal access delay in Ge Siping City, is determined the Memory Controller Hub address bit of described physical address.

20. polycaryon processors according to claim 19, is characterized in that, described analysis module also, for according to access delay time length, divides into groups to the equal access delay in described Ge Siping City;