CN103778943A - One-time programming cellular structure and transistor array consisting of same - Google Patents
One-time programming cellular structure and transistor array consisting of same Download PDFInfo
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- CN103778943A CN103778943A CN201210411263.2A CN201210411263A CN103778943A CN 103778943 A CN103778943 A CN 103778943A CN 201210411263 A CN201210411263 A CN 201210411263A CN 103778943 A CN103778943 A CN 103778943A
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Abstract
The invention discloses a one-time programming cellular structure which comprises three MOS (Metal Oxide Semiconductor) tubes of the same model, namely, a selecting tube T1, a transmission tube T2 and a programming tube T3, wherein the selecting tube T1 and the transmission tube T2 are connected in such a mode that the source is connected in series with the drain; the source of the selecting tube T1 is connected with a bit line BL of the transistor array; the drain of the transmission tube T2 is connected with the liner of the programming tube T3; the grid of the programming tube T3 is used for inputting programming voltage PL; the grid of the selecting tube T1 is connected with a word line WL of the transistor array. The invention further discloses a transistor array consisting of the one-time programming cellular structures. The cellular structure disclosed by the invention adopts minimum layout design rules, and is small in cellar area, and high in array integration degree; the cellar structure is simple and high in portability and applicable to various CMOS (Complementary Metal-Oxide-Semiconductor Transistor) processes; most basic MOS tubes are used, so that the process cost is not increased; the reading condition and the programming condition are simple and easy to operate; the programming is accomplished, and grind oxidation films of the programming tubes are broken through, so that high reliability is achieved.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to a kind of one-time programming structure cell.The invention still further relates to a kind of transistor array being formed by described one-time programming structure cell.
Background technology
Utilize Floating poly(floating boom) store electrons is common OTP (one-time programmable memory) principle of work.Floating boom OTP can embed common logic process, generally realizes the basic programming of OTP and the function of charge storage by the additional floating boom electric capacity of transistor.Due to the existence of floating boom coupling capacitance, cell density increases greatly.Floating boom OTP generally needs higher program voltage (being usually the more than 2～3 times of circuit voltage), and for tolerating this high voltage, the inner each well region of structure cell just needs larger isolation distance, and the integrated level of structure cell array also can reduce greatly.
Along with the progress of manufacture of semiconductor, technique live width further reduces, also attenuate again and again of the thickness of gate oxidation films.But compare the speed of gate oxidation films attenuate, underspeeding of circuit voltage wants much slow.The relatively voltage breakdown of gate oxidation films and the operating voltage of circuit, both gaps are more and more less, cause the OTP structure cell of high integration to be subject to the restriction that technique live width is dwindled, and a little less than portability, reliability is low.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of one-time programming structure cell that is not subject to technique line width limit.
For solving the problems of the technologies described above, one-time programming structure cell of the present invention, comprising: three homotype metal-oxide-semiconductors, are respectively and select pipe T1, transfer tube T2 and programming pipe T3;
Select pipe T1 and transfer tube T2 to adopt the mode of source-drain electrode series connection to be connected, select the source electrode of pipe T1 to link the bit line BL of transistor array, the drain electrode of transfer tube T2 is connected with the substrate of programming pipe T3, the grid of programming pipe T3, in order to input program voltage PL, selects the grid of pipe T1 to link the word line WL of transistor array.
Wherein, after described structure cell is programmed, the gate oxidation films of its programming pipe T3 is breakdown.
The present invention also provides a kind of transistor array being made up of described one-time programming structure cell, the grid that forms all one-time programming structure cell transfer tube T2 of this transistor array links together by connecting line SL, to reach the object of this array page integrated operation;
Wherein, the word line WL of described transistor array and the bit line BL of transistor array can choose in transistor array needs operated target structure cell, by executing alive mode at programming pipe T3 grid, target structure cell is programmed;
Wherein, input program voltage PL can apply program voltage condition to each structure cell, by reading the electric current of transistor array bit line BL, can distinguish each structure cell and be programmed or be not programmed.
One-time programming structure cell of the present invention, this structure cell utilizes gate oxidation films anti-fuse characteristic (i.e. anti-operating chacteristics), realizes the function of one-time programming.Three transistors that adopt in structure cell of the present invention are homotype, are N-type or entirely for P type entirely.Below to the explanation of structure cell principle of work take N-type pipe as example, P type pipe only need be by condition negate.
Transistor size in structure cell of the present invention, isolation size, connection line size can adopt domain minimum design rule, to reach the minimized object of cell density.
The key of the programming of structure cell of the present invention is the potential difference (PD) of programming pipe substrate and grid, as long as this potential difference (PD) can make to programme, the gate oxidation films of pipe mountain occurs is worn, and the programming of structure cell has just completed.
Concrete operations condition is as follows:
At SL input service voltage Vdd, can programme to the indivedual cellulars in this page.If SL access zero potential GND, PL input program voltage Vpp, whole page structure cell all can not be programmed;
WL and BL not selected state are zero potential GND, and the WL of target structure cell and BL cut-in operation voltage Vdd have been chosen to this structure cell;
PL input program voltage Vpp, cellular has been programmed.Program voltage Vpp need to meet three conditions:
1. program voltage Vpp is negative value;
2.|Vdd-Vpp| is greater than programming pipe gate oxidation films mountain and wears voltage;
3.|Vpp| is less than programming pipe gate oxidation films mountain and wears voltage.
Reading conditions is as follows:
SL input service voltage Vdd chooses page, and WL input service voltage Vdd chooses word, and BL input service voltage Vdd selected bit can be chosen target structure cell in matrix.SL, WL, the unchecked equal cut-in operation voltage Vdd of BL, PL connecting to neutral current potential GND.
Read BL electric current, if BL electric current shows as electric leakage (< InA), think that this structure cell is not programmed, if BL electric current magnitude is wanted to work as with selecting pipe T1 saturation current (Idsat), this structure cell is programmed.
Principle explanation, as SL access zero potential GND, transfer tube T2 closes.The substrate of the programming pipe T3 being connected with transfer tube T2 source electrode is in zero potential, PL input program voltage Vpp, bias voltage deficiency between programming pipe T3 grid and substrate is so that gate oxidation films punctures, and now all structure cells of linking same SL all can not be programmed, and are whole page operations.If SL cut-in operation voltage Vdd, transfer tube T2, all the time in opening, therefore exists as just transmitting effect, and all cellulars of this page are selected, had the possibility being programmed.Next, in this page, by being applied to operating voltage Vdd, WL and SL just can select the structure cell that specifically need to be programmed.Selected programming structure cell, it selects pipe T1 in state of saturation, the current potential of source electrode arrives the substrate of programming pipe by transfer tube T2, now the bias voltage between substrate and the grid of programming pipe T2 makes gate oxidation films occur to puncture, and structure cell completes programming.Structure cell on the upper not selected BL of same WL, owing to selecting pipe T1 drain potential in zero potential, is transferred to the substrate of programming pipe T3, makes programming pipe T3 cannot complete programming.In like manner, not selected as WL, the grid of the selection pipe T1 of whole piece WL is all turned off, and selects the drain potential of pipe T1 cannot be transferred to programming pipe substrate, and therefore the upper all structure cells of this WL also cannot be programmed.Use above scheme, can reach in specific structure cell array page, the object of choosing specific structure cell to programme to it, and other structure cell around is not affected.
Structure cell of the present invention adopts minimum layout design rules, and cell density is little, and array integrated level is high; Structure cell is simple, uses the metal-oxide-semiconductor on basis the most, without increasing process costs, and is applicable to all kinds of CMOS technique, portable strong; Reading conditions and program conditions are simple to operation; After having programmed, the gate oxidation films of programming pipe is breakdown, and this state has very high reliability.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the structural representation of one embodiment of the invention.
Description of reference numerals
T1 selects pipe
T2 is transfer tube
T3 is programming pipe
WL is the word line of transistor array
BL is the bit line of transistor array
PL is program voltage
SL is the grid connecting line of transfer tube
Embodiment
As shown in Figure 1, one embodiment of the invention, comprising: three PMOS pipes, are respectively and select pipe T1, transfer tube T2 and programming pipe T3;
Select pipe T1 and transfer tube T2 to adopt the mode of source-drain electrode series connection to be connected, select the source electrode of pipe T1 to link the bit line BL of transistor array, the drain electrode of transfer tube T2 is connected with the substrate of programming pipe T3, the grid of programming pipe T3 is in order to input program voltage PL, select the grid of pipe T1 to link the word line WL of transistor array, after structure cell is programmed, the gate oxidation films of its programming pipe T3 is breakdown.
A transistor array for described one-time programming structure cell composition, the grid that forms the transfer tube T2 of all one-time programming structure cells of this transistor array links together by connecting line SL, to reach the object of this array page integrated operation;
Wherein, the word line WL of transistor array and the bit line BL of transistor array can choose in transistor array needs operated target structure cell, by executing alive mode at programming pipe T3 grid, target structure cell is programmed;
Wherein, input program voltage PL can apply program voltage condition to each structure cell, by reading the electric current of transistor array bit line BL, can distinguish each structure cell and be programmed or be not programmed.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (5)
1. an one-time programming structure cell, is characterized in that, comprising: the metal-oxide-semiconductor of three homotypes, is respectively and selects pipe (T1), transfer tube (T2) and programming pipe (T3);
Select pipe (T1) and transfer tube (T2) to adopt the mode of source-drain electrode series connection to be connected, select the source electrode of pipe (T1) to link the bit line (BL) of transistor array, the drain electrode of transfer tube (T2) is connected with the substrate of programming pipe (T3), the grid of programming pipe (T3), in order to input program voltage (PL), selects the grid of pipe (T1) to link the word line (WL) of transistor array.
2. one-time programming structure cell as claimed in claim 1, is characterized in that: after described structure cell is programmed, the gate oxidation films of its programming pipe (T3) is breakdown.
3. one kind by transistor array that described in claim 1, one-time programming structure cell forms, it is characterized in that: the grid that forms all one-time programming structure cell transfer tubes (T2) of this transistor array links together by connecting line (SL), to reach the object of this array page integrated operation.
4. transistor array as claimed in claim 3, it is characterized in that: the word line (WL) of described transistor array and the bit line (BL) of transistor array can be chosen in transistor array needs operated target structure cell, by executing alive mode at programming pipe (T3) grid, target structure cell is programmed.
5. transistor array as claimed in claim 3, it is characterized in that: input program voltage (PL) can apply program voltage condition to each structure cell, by reading the electric current of transistor array bit line (BL), can distinguish each structure cell and be programmed or be not programmed.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210411263.2A CN103778943B (en) | 2012-10-25 | 2012-10-25 | One-time programming structure cell and the transistor array of composition thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210411263.2A CN103778943B (en) | 2012-10-25 | 2012-10-25 | One-time programming structure cell and the transistor array of composition thereof |
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| CN103778943A true CN103778943A (en) | 2014-05-07 |
| CN103778943B CN103778943B (en) | 2016-11-16 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050007855A1 (en) * | 2003-06-28 | 2005-01-13 | Korea Advanced Institute Of Science And Technology | 3-Transistor OTP ROM using CMOS gate oxide antifuse |
| US20060067152A1 (en) * | 2004-09-29 | 2006-03-30 | Ali Keshavarzi | Crosspoint memory array utilizing one time programmable antifuse cells |
| US20070008800A1 (en) * | 2005-06-28 | 2007-01-11 | Cypress Semiconductor Corporation | Antifuse capacitor for configuring integrated circuits |
| US20070076463A1 (en) * | 2005-09-30 | 2007-04-05 | Ali Keshavarzi | Dual gate oxide one time programmable (OTP) antifuse cell |
| US20100110750A1 (en) * | 2008-11-04 | 2010-05-06 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
-
2012
- 2012-10-25 CN CN201210411263.2A patent/CN103778943B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050007855A1 (en) * | 2003-06-28 | 2005-01-13 | Korea Advanced Institute Of Science And Technology | 3-Transistor OTP ROM using CMOS gate oxide antifuse |
| US20060067152A1 (en) * | 2004-09-29 | 2006-03-30 | Ali Keshavarzi | Crosspoint memory array utilizing one time programmable antifuse cells |
| US20070008800A1 (en) * | 2005-06-28 | 2007-01-11 | Cypress Semiconductor Corporation | Antifuse capacitor for configuring integrated circuits |
| US20070076463A1 (en) * | 2005-09-30 | 2007-04-05 | Ali Keshavarzi | Dual gate oxide one time programmable (OTP) antifuse cell |
| US20100110750A1 (en) * | 2008-11-04 | 2010-05-06 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
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| CN103778943B (en) | 2016-11-16 |
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