CN103890945A - Devices including a diamond layer - Google Patents

Devices including a diamond layer Download PDF

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Publication number
CN103890945A
CN103890945A CN201180074487.2A CN201180074487A CN103890945A CN 103890945 A CN103890945 A CN 103890945A CN 201180074487 A CN201180074487 A CN 201180074487A CN 103890945 A CN103890945 A CN 103890945A
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layer
diamond
waveguide
pattern structure
dielectric
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CN103890945B (en
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梁迪
雷蒙德·G·博索雷
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Hewlett Packard Enterprise Development LP
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Hewlett Packard Development Co LP
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02444—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A device includes a substrate layer, a diamond layer, and a device layer. The device layer is patterned. The diamond layer is to conform to a pattern associated with the device layer.

Description

Comprise the device of diamond layer
Background technology
Silicon-on-insulator (Si) is (SOI) a kind of silicon-based devices platform of standard, comprises and can be such as SiO 2the insulator layer of oxide (be buried oxide (BOX) layer).But, SiO 2the thermal conductivity (approximately 1.3W/m/ ℃) with extreme difference, has hindered effective heat radiation and has caused device heating and performance and/or reliability decrease.
Accompanying drawing explanation
Fig. 1 is according to the side cross-sectional view of the device that comprises diamond layer of example.
Fig. 2 is according to the side cross-sectional view of device of comprising of example multiple parts, intermediate layer of material and diamond layer.
Fig. 3 is according to the side cross-sectional view of the device that comprises diamond layer and asymmetric device layer of example.
Fig. 4 is according to the side cross-sectional view of the device that comprises diamond layer and asymmetric device layer of example.
Fig. 5 A is according to the side cross-sectional view of the device that comprises insulating pattern structure and diamond layer of example.
Fig. 5 B is according to the side cross-sectional view of the device that comprises insulating pattern structure and diamond layer of example.
Fig. 5 C is according to the side cross-sectional view of the device that comprises insulating pattern structure and diamond layer of example.
Fig. 5 D is according to the side cross-sectional view of the device that comprises insulating pattern structure and diamond layer of example.
Fig. 6 A is according to the side cross-sectional view of the device that comprises diamond layer of example.
Fig. 6 B is according to the side cross-sectional view of the device that comprises diamond layer of example.
Fig. 7 A-7J is according to the side cross-sectional view of the manufacture method of the device that comprises diamond layer of example.
Now in connection with accompanying drawing, current example is described.In the accompanying drawings, identical Reference numeral can refer to identical or functionally similar element.
Embodiment
Device Platform can comprise that diamond layer is to strengthen the property.Silicon on diamond (SOD) or other diamond semiconductor-on-insulator (for example GaAs (GaAs)) device Platform, can be used to electronics and photonic device, for example high-end microprocessors, for LASER Light Source and other device of optical interconnection.For example, diamond layer can provide splendid heat-sinking capability, and can provide thermal conductivity so that heat is spread out of from device layer.
Fig. 1 is according to the side cross-sectional view of the device that comprises diamond layer 104 100 of example.Diamond layer 104 is attached to substrate layer 102 and device layer 106.Device layer 106 can be the semiconductor such as silicon (Si), and can use Smart Cut tMor other technology is from obtaining such as the semiconductor crystal wafer of naked Si substrate or SOI substrate.Substrate layer 102 can be used as processing substrate (handle substrate) and obtains.Diamond layer 104 can be polished so that substrate layer 102 is attached to diamond layer 104.In example, substrate layer 102 can be engaged to diamond layer 104 by direct wafer.
Device layer 106 can be the semiconductor such as Si, GaAs (GaAs) etc., comprises the material of the waveguide device for high index of refraction is provided.Device layer 106 can be from obtaining such as the semiconductor crystal wafer of naked Si substrate or SOI substrate.Device layer 106 can use Smart Cut tMor other technology obtains, comprise that polishing removes or otherwise remove the part of source wafer.
Device layer 106 can comprise pattern structure 108.For example, pattern structure 108 can comprise device circuitry, waveguide and/or other structure.At least a portion of pattern structure 108 can extend downward in diamond layer 104.Pattern structure 108 can form by the downside of patterning/etch device layer 106.In example, pattern structure 108 can be such as the optics of waveguide and/or such as the electronic device of device circuitry.Pattern structure 108 can comprise further feature, comprises the part of silicon-on-insulator (SOI) encapsulation and/or the metal level of deposition, because pattern structure 108 is not limited to blank silicon, and can comprise different regions and different structures.
Diamond layer 104 can be harmonious with the pattern structure of device layer 106 108.In example, diamond can use chemical vapour deposition (CVD) (CVD) or other technique to be deposited on pattern structure 108 blankly, makes thus the various surfaces mate of diamond layer 104 and pattern structure 108.The diamond layer 104 being harmonious can fill up the whole pattern of the pattern structure 108 of device layer 106, comprises the sidewall of pattern structure 108.
Diamond layer 104 can comprise monocrystalline or polycrystalline structure.Single-crystal diamond has very high thermal conductivity, and price is high, and is difficult to large scale and obtains, and has limited potentially the cost benefit size of single-crystal diamond wafer and/or has increased the cost of this diamond based device.Polycrystalline diamond has the thermal conductivity lower than single-crystal diamond, but price is lower and be easy to expansion scale.
Diamond layer 104 can provide the thermal conductivity up to 2400 watts/meter/Kelvin degree (W/m/K).Diamond layer 104 can be sandwiched between between device layer 106 and substrate layer 102, thinks that device layer 106 provides heat conduction.The heat of device, for example, from the heat of device layer 106, can be dissipated to substrate layer 102 via diamond layer 104 rapidly.
The upper part of device layer 106 can obtain by a part that optionally removes device layer 106.In example, device layer 106 can be formed by SOI wafer, and thus, silicon part and oxide part (for example buried oxide (BOX) layer) can remove and leave silicon layer for obtaining device layer 106 from SOI wafer.In addition, the BOX layer of source SOI wafer can be used as mask layer before it removes.Alternately, device layer 106 can be formed by Silicon Wafer by " smart-cut (Smart-cut) " technology, and this technology splits off device layer 106 from its female Silicon Wafer, thereby female Silicon Wafer can be reused.The upper part of device layer 106 can be prepared as be attached to can be mutual with device layer 106 parts, or be in the state that will be attached to parts that can be mutual with device layer 106.
Fig. 2 is according to the side cross-sectional view of device 200 of comprising of example multiple parts 210, intermediate layer of material 212 and diamond layer 204.
Device 200 can comprise the III-V family mixture on SOD device.A part for parts 210 can comprise the III-V family layer such as indium phosphide.Device 200 can comprise hybrid laser and modulator and the hybrid optical electric explorer with resonator geometries, this device 200 can be used as comprising light source on the chip of photonic integrated circuits (PIC) of photonic data link, and can be used for optics interconnection applications on wavelength division multiplexing (WDM), increase and decrease filter/router, switch, transducer, modulator, buffer and chip, such as the passive component of multiplexer and other waveguide elements and such as the active parts of laser, photodetector and modulator.
The pattern structure 208 being associated with device layer 206 can for example be attached to parts 210 based on optical coupled, so that optics mode region 230 to be provided.The waveguide lateral dimension 222 being associated with pattern structure 208 can provide the ripple guiding of single transverse hybrid mode.The comparable waveguide lateral dimension 222 of parts lateral dimension 220 is wide, because parts 210 may be associated with fabrication tolerance and device series resistance aspect.By forming narrow waveguide or other pattern structure 208, for example, even if parts 210 (III-V family ring waveguide) have for single mode system too wide on the contrary parts lateral dimension 220, the operation of device 200 also can realize single hybrid mode.
More specifically, waveguide mode can be dependent on the width of waveguide, and waveguide can be single mode waveguide or multi-modal waveguide.Single mode can be associated with narrow waveguide, is enough to support basic mode so that its width is too narrow to.But top section/parts 210 can be associated to solve other consideration that relates to parts 210 with the width increasing.For example, parts lateral dimension 220 can be conducive to the aligning of parts 210 with respect to this pattern structure 208, the electrical resistance problem due to the too narrow parts due to the too close optics mode of the quantum well active area in parts 210 and etched sidewall region 230 is avoided in help, and other electric property problem of leaking such as electricity.Pattern structure 208 can be independent of parts 210 and provide, for example, by patterned devices layer 206 before depositing diamond layer 204.Therefore, for the SOD platform such as device 200, narrow with the lateral dimension 222 comparable component lateral dimensions 220 that waveguide (or other pattern structure 208) is associated.Therefore,, in the situation that not needing dwindle parts 210 or cause relative dimensions problem, hybrid optical mode region 230 can be subject to the impact of waveguide lateral dimension 222 so that the benefit of single mode to be provided.
In view of material resistance is proportional to the length of material and is inversely proportional to the sectional area of material, wider parts lateral dimension 220 can be favourable.For parts 210, charge carrier can inject from top area.For example, if parts lateral dimension 220 (ring length of resonant ring) is wider, its cross section may be larger, and its resistance is lower, reduces heat and further keep single mode operation.
Intermediate layer of material 212 can be provided to diamond layer 204 to be attached to substrate layer 202.In example, intermediate layer of material 212 can be deposited on diamond layer 204.Intermediate layer of material 212 can with polishing compatibility, for example, for being enhanced to the joint such as other layer of substrate layer 202.Intermediate layer of material 212 can comprise such as the oxide of the oxide of aluminum metal, copper metal, aluminium, beryllium, polysilicon and can survive in CMOS manufacturing environment, has good thermal conductivity and can for example, by other CMOS compatible material of easily polishing (, can be compatible mutually with chemical-mechanical planarization or polishing (CMP)).More specifically, intermediate layer of material 212 can have than the thermal conductivity that is used in the transparent insulation height in CMOS environment, and for instance, transparent insulator is such as oxide (SiO 2), dissimilar glass, such as quartzy crystal (comprising unsetting crystal) and for the insulator of the broad sense class of mirror substrate.Intermediate layer of material 212 can be formed thin layer, and can be omitted by the intermediate layer of material 212 to be engaged to substrate layer 202 in the situation that of polishing effectively at diamond layer 204.
Fig. 3 is according to the side cross-sectional view of the device 300 that comprises diamond layer 304 and asymmetric device layer 306 of example.Substrate layer 302 is attached to intermediate layer of material 312, and intermediate layer of material 312 is attached to the diamond layer 304 being harmonious with device layer 306.Parts 310 are attached to device layer 306.
For example, parts 310 and device layer 306 can be used as micro-ring modulator.Asymmetric device layer 306, such as waveguide, can provide specific structure, and the wherein lower part of pattern structure 308, for example towards the part of diamond layer 304, is different from the upper part that is attached to parts 310.Be injected into or exhaust in the example of the change that for example causes the change of mode index and the loss of modulation, switching or decay application at charge carrier, in view of charge carrier path 332, the dissymmetrical structure of device layer 306 can be advantageous particularly.
Charge carrier path 332 can provide the overlapping of enhancing between charge carrier and optics mode region 330.For example, in view of the position in optics mode region 330, due to the asymmetry being associated with device layer 306 and charge carrier path 332, charge carrier can flow through 330 center, optics mode region.For example, device layer 306 can be from two sides etched crystal circle structure, so that asymmetrical characteristic to be provided, and needn't incrementally set up device layer 306 at the top of diamond layer 304.Therefore, obtain device layer 306 from source wafer manufacture efficiency, output, reliability and other benefit are provided.
Can be induced, for flowing through waveguide to another corner from a corner, effectively to interact with waveguide with the interactional charge carrier of asymmetrical guide device layer 306, this can comprise through 330 center, optics mode region.The thickness of device layer 306 is not uniformly, and can be greater than or less than the thickness of waveguide.Therefore,, with respect to symmetrical waveguide, asymmetric device layer 306 can reduce or eliminate the charge carrier that is injected into can avoid flowing into or leaving with the mode of the whole regional interaction of waveguide the possibility of waveguide with them.
Fig. 4 is according to the side cross-sectional view of the device 400 that comprises diamond layer 404 and asymmetric device layer 406 of example.Substrate layer 402, intermediate layer of material 412, diamond layer 404, device layer 406 and parts 410 can be linked together.
In device 400, parts 410 can be used as the III-V family mixture on the micro-cyclic laser of SOD, modulator or photodetector.From device layer 406 via diamond layer 404 (and in the time comprising intermediate layer of material 412, via intermediate layer of material 412) can avoid to the heat dissipation of substrate layer 402 problem that heat is relevant, drift about such as the resonance wavelength in the micro ring device being associated with parts 410.
Therefore, asymmetric device layer 406, such as asymmetrical guide, can be incorporated in the micro-cyclic laser of mixed type silicon, modulator or photodetector.The lateral dimension of pattern structure 408 (for example waveguide) can provide single transverse hybrid mode.For example, even if parts 410 (, III-V family ring waveguide) are still wide than the parts that are limited to potentially single mode system due to size, also can realize single hybrid mode of micro-ring waveguide structure.
Fig. 5 A is according to the side cross-sectional view of the device 500A that comprises insulating pattern structure 540A and diamond layer 504A of example.Substrate layer 502A is attached to diamond layer 504A via intermediate layer of material 512A.Diamond layer 504A is attached to device layer 506A.Parts 510A is attached to device layer 506A, and is associated with optics mode region 530A.Device layer 506A is patterned as has pattern structure 508A and insulating pattern structure 540A.The patterning of diamond layer 504A and device layer 506A is harmonious, and comprises with pattern structure 508A and insulating pattern structure 540A and being harmonious.
Device 500A is hybrid device, comprises the region (for example SOD) being associated with diamond and the region (for example SOI) being associated with insulator.The region being associated with diamond can be rapidly by device heat dissipation to substrate layer 502A.Some other device/component, is used to the device of manufacturing function photonic integrated circuits such as those, may with produce device heating and/or do not have associated because of device heating damaged.Example device/the parts with this feature can comprise passive wave guide and/or grating coupler.Other device can carry out tuning their performance (for example filter, silicon modulator) by heat, and therefore can acquire benefit from heating by avoiding heat dissipation to diamond layer 504A.This not To Be Protected from Heat and/or utilize the device of thermal tuning, can be provided as insulating pattern structure 540A, so that the external heat being injected into can affect those parts, rather than dissipates (waste) to substrate layer 502A by diamond layer 504A.
Dielectric 542A, such as buried oxide, can provide local SOI region, so that the diamond of lower floor has a little heat and other effect to the insulating pattern structure 540A of dielectric 542A top.Therefore, general-purpose platform can be provided as both having had the SOD region (or other semiconductor regions) on diamond of the good heat dissipation for being associated with pattern structure 508A, is also useful on the local SOI region (insulating pattern structure 540A) of the device with thermal tuning or hot immunity.General-purpose platform can meet the different needs, and can comprise the photon and the electronic device that are integrated thereon.
Thermal oxidation can be used to provide dielectric 542A.For example, a part of device layer 506A can be oxidized before the formation of pattern structure 508A, thereby form SOI insulating pattern structure 540A at the top of diamond layer 504A.Alternately, dielectric 542A can be deposited and be formed by outside dielectric before the formation of pattern structure 508A.Insulating pattern structure 540A can by using the encapsulation of oxide dielectric selectivity to form, for example, use SiO 2silicon encapsulation.
Soi structure above diamond substrate makes device can utilize thermal tuning not lose to diamond layer 504A and substrate layer 502A effectively to absorb heat.The combination of SOI and SOD device, be similar to device 500A, can provide the degree of freedom in device design to allow the device that heating can have a negative impact and heating can produce positive influences and/or no problem device exists (local environment that wherein insulating pattern structure 540A can provide a heat isolation) simultaneously.The device being associated with thermal tuning can comprise modulator, increase and decrease device and other device.Device 500A can comprise hybrid device, such as mixing photonic integrated circuits (PIC) structure, mixing laser, mixing or Si photodetector, mixing or Si modulator, surface grating, passive Si waveguide elements, switch and other device, they can all be positioned on same chip.The device with serious device heating may be associated such as pattern structure 508A with SOD waveguiding structure.Utilize the device (for example encircling modulator, increase and decrease device etc.) of thermal tuning and/or can for example, can not be provided as being formed on the minor insulation pattern structure 540A (for example SOI region) on blank depositing diamond layer 504A because of the device of device heating damaged (surface grating coupler).
Insulating pattern structure 540A can comprise metal level 560A.Metal level 560A can be associated with wherein the region of placement surface grating (being positioned at the region under insulating pattern structure 540A).Metal level 560A can be omitted.In example, passive wave guide region metal level 560A can be omitted to avoid the metal of light to absorb.
Metal level 560A can be reflected back into light the surface (for example insulating pattern structure 540A) in surface grating coupler region.A part of oxide dielectric 542A can be removed to hold metal level 560A.In the regional area (comprising that those have the region of metal level 560A) that diamond need to not be associated with insulating pattern structure 540A at those.But the part that diamond layer 504A is positioned at those regional areas does not need to be removed, and realizes thus effective device manufacture.
The side cross-sectional view of Fig. 5 A based on as shown in Figure 5 A, Fig. 5 B is according to the side cross-sectional view of the device that comprises insulating pattern structure 540B and diamond layer 504B of example.Insulating pattern structure 540B can be attached to diamond layer 504B, intermediate layer of material 512B (can comprising or omit, as other example) and substrate layer 502B.Insulating pattern structure 540B can be a part of device layer 506B, and can comprise metal level 560B, dielectric 542B and pattern structure 508B.
Incident light can pass pattern structure 508B.Light loss is to increase or reduce the thickness that can be dependent on the dielectric 542B between pattern structure 508B and metal level 560B.In example, if dielectric is 1 μ m or thicker, the light absorption of metal level 560B can be ignored.For example, if 508B comprises periodic patterns structure (grating), it can produce the light reflection of while up and down.In the situation that preferably upwards reflecting, downward part can be by metal level 560B upwards reflection again.Solid metal reflector can provide high reflectance with the initial light of reflection downwards that avoids waste.Dielectric can be thicker or thinner, and can for example, for example, in view of the material (SiO of the material of pattern structure 508B (silicon) and dielectric 542B 2) between refractive index contrast elect.The thickness of dielectric 542B is to provide the degree of freedom to adjust the phase place of the light reflection in dielectric 542B, so that constructive interference or destructive interference can occur for the part of initial upwards reflection and the light from solid metal reflector bounce-back.
Light reflection from two parts can be out-phase or homophase, to strengthen in a direction or counteracting light.For example, phase cancellation can be and merges the device portions of phase cancellation a kind of isolation is provided.By selecting the suitable original depth of dielectric 542B, phase relation can also and then the incident light of formation light reflection upwards be adjusted downwards at the light upwards being reflected by grating 508B with through dielectric 542B.For example, from the light reflection of metal level 560B can with the light homophase (for example constructive interference) from grating 508B reflection, this can make grating emission effciency surge.Other phase relation is possible, comprises that constructive interference and/or destructive interference are to affect grating emission effciency.Interferometric device can utilize insulating pattern structure 540B that the relative phase in the different paths of appointment is provided, to provide specific phase/amplitude in the output of those parts.Various device (such as interferometer) can be provided as providing phase place adjustment (for example phase place adjustment of 0 degree, 90 degree, 180 degree etc.), and interferometer/device can comprise that Mach-Zehnder interferometers is to determine from the relative phase shift between two collimated light beams of coherent source.
Fig. 5 C is according to the side cross-sectional view of the device 500C that comprises insulating pattern structure 540C and diamond layer 504C of example.Substrate layer 502C can be attached to diamond layer 504C via intermediate layer of material 512C.Diamond layer 504C can be attached to device layer 506C.Parts 5l0C can be attached to device layer 506C and be associated with optics mode region 530C.Device layer 506C can be patterned pattern structure 508C and insulating pattern structure 540C.Diamond layer 504C can be harmonious with the patterning of device layer 506C, comprises with pattern structure 508C and insulating pattern structure 540C and being harmonious.
The dielectric 542C of insulating pattern structure 540C can comprise air gap 544C, and it can provide by least a portion that optionally removes dielectric 542C.Air gap 544C can be provided at the below of the patterning part of insulating pattern structure 540C.Air gap 544C can provide heat isolation and ripple guiding, and the initial oxide that is therefore used to the dielectric 542C that forms air gap 544C can be than thin in the example of oxide dielectric 542C with the relevant air gap 544C of nothing.For example, with light path through compared with the thickness 1-3 μ m in the situation of dielectric 542C, the 500nm that air gap 544C can be about and be associated through the light path of air gap 544C.
The side cross-sectional view of Fig. 5 C based on shown in Fig. 5 C, Fig. 5 D is according to the side cross-sectional view of the device that comprises insulating pattern structure 540D and diamond layer 504D of example.Insulating pattern structure 540D is attached to diamond layer 504D, intermediate layer of material 512D (in the time being included) and substrate layer 502D.Insulating pattern structure 540D can be the part of device layer, and can comprise metal level 560D, air gap 544D and pattern structure 508D.Compared to substituting air gap 544D with the dielectric of another kind of type, air gap 544D can provide for example, extra selection about optical property (light reflection, constructive interference/destructive interference etc.) and other performance standard (heat).
Fig. 6 A is according to the side cross-sectional view of the device 600A that comprises diamond layer 604A of example.Because diamond layer 604A and pattern structure are harmonious, so diamond layer 604A itself can provide waveguide or other performance to strengthen structure/feature.
CVD diamond technology can be employed to form diamond-core waveguide (for example quantum device application), comprises the formation of the waveguide such as Buddha's warrior attendant stone cistern, diamond rib, the rib of falling diamond, diamond nano line, the line of falling diamond nano and stripe waveguide.In example, dielectric 642A, for example SiO 2layer (heat of CVD), for example can be formed on, on substrate layer 602A (pure Si wafer).Groove can be etched in dielectric 642A.On dielectric 642A, after blank deposition CVD diamond layer 604A, the surface of diamond layer 604A can be polished.Upper dielectric 643A (for example, another SiO 2layer) can be deposited over diamond layer 604A above, to be used as the top covering of the rib of the falling diamond waveguide as shown in Fig. 6 A, the rib of the falling diamond waveguide shown in Fig. 6 A also can represent to comprise other waveguide of the diamond nano line waveguide that is illustrated as 650A.Device 600A can be called as SOD type II device, and wherein waveguide is formed and groove is filled and diamond provides device function by diamond.Therefore, diamond waveguide can provide good heat extraction.
Waveguide described here also can comprise strip (being raceway groove) waveguide, it can represent the limit of rib shape waveguide (rib waveguide), wherein rib thickness is close to zero, so that in fact stratum nucleare is removed in the unglazed region that is guided propagation.Stripe waveguide also can be provided with triangular-section.
Fig. 6 B is according to the side cross-sectional view of the device 600B that comprises diamond layer 604B of example.Dielectric 642B is attached to substrate layer 602B.Diamond layer 604B is attached to dielectric 642B, and then waveguiding structure is formed, and upper dielectric 643B is attached to diamond layer 604B.
Diamond waveguide structure in Fig. 6 A and 6B can make the powerful interaction in the center, nitrogen room of optics mode and diamond layer inside, thereby improves the efficiency of the quantum optics device that comprises diamond layer.Exemplary process can be used to provide this structure in more effective mode, and without in order to the step as waveguide cores material on using gallium phosphide (GaP) film transfer to diamond.
Fig. 7 A-7J is according to the side cross-sectional view of the manufacture method of the device that comprises diamond layer of example.In Fig. 7 A, silicon-on-insulator (SOI) substrate 701A is shown, but can uses blank silicon or other semi-conductive wafer.SOI substrate 701A can comprise dielectric 742A layer, and SOI substrate 701A is divided into substrate upper strata and lower substrate part.The upper strata of substrate can be used as device layer 706A.The in the situation that of blank material wafer, blank ion is injected and can be for example used to prepare substrate 701A, for separating subsequently (, use Smart Cut based on implanted ions layer (not shown) tMor other is techniques such as division).
Fig. 7 B illustrates device layer 706B, and it comprises formation pattern structure 708B and dielectric 742B, so that the device layer 707B of encapsulation to be provided.For example, pattern structure 708B can be waveguide, and dielectric 742B can provide based on thermal oxidation, with a part of packaging layer 706B.The optical signature that the thickness of the dielectric 742B being associated with the device layer 707B of encapsulation can be dependent on expectation changes with other factors.Metal level 760B can be formed on the top of dielectric 742B as shown, the reflection being associated with the device layer 707B providing and encapsulate.Metal level 760B can form based on selective metal deposition.For example, metal level 760B can be included in the place of placement surface grating, and in the case of form passive wave guide region and prevent light metal absorb can omit.Therefore, device manufacture can be included in and apply more layer patterning SOI wafer before.Device layer 706B can be exposed to other patterning/technology, comprises that implanted ions is optionally to affect the part of device layer 706B, comprises part and other places of pattern structure 708B.The second oxide encapsulation forms (not shown) and can be formed on metal level 760B top, thus package metals layer 760B.Package metals layer 760B can prevent the metallic pollution (for example CVD diamond reactor (CVD)) of diamond layer, and make various types of metals widely, (for example comprise non-CMOS compatible metal, gold, silver) and there is the metal of better optical mirror plane characteristic, can be used in metal level 760B.
Fig. 7 C is illustrated in device layer 706C top and forms diamond layer 704C.Diamond layer 704C can use CVD maybe can make other method that the patterning of diamond layer 704C and device layer 706C is harmonious (comprise with pattern structure 708C, dielectric 742C and/or metal level 760C and being harmonious) and form.
Fig. 7 D is illustrated in diamond layer 704D top and forms intermediate layer of material 712D.Intermediate layer of material 712D can fill any out-of-flatness in diamond layer 704D, and form that can thin layer applies, to prevent from increasing thermal impedance.Alternately, diamond layer 704D can be polished level and smooth, so that intermediate layer of material 7l2D can be omitted.Intermediate layer of material 7l2D can have high heat conductance, can with CMOS process compatible, and can be by easily polishing so that composition surface to be provided.
Fig. 7 E illustrates the polishing of intermediate layer of material 7l2E.Intermediate layer of material 7l2E can use CMP or other technology polishing.Therefore, intermediate layer of material 7l2E is produced for engaging, and its thickness can be reduced to reduce thermal impedance and other benefit is provided.
Fig. 7 F illustrates the joint of intermediate layer of material 7l2F to substrate layer 702F.For example, substrate layer 702 can be silicon and processes wafer.SOI substrate 701 has been reversed, so that intermediate layer of material 7l2F faces down.Substrate layer 702F can comprise underlay pattern 703F (for example a series of grooves or other pattern), but underlay pattern 703F can be omitted in example device, and optics and/or the mechanicalness that can be used to provide extra strengthen.
Fig. 7 G illustrates a part that removes SOI substrate, comprises and removes silicon and dielectric the superiors, exposes device layer 706G using the upper strata as device Platform.This layer can be based on Smart Cut tMor other technology and removing, for example divide by the blank ion implant layer (not shown) place at substrate.Therefore, pattern structure 708G and dielectric 742G are placed at the top of device Platform, carry out a part of packaging layer 706G with dielectric 742G.
Fig. 7 H illustrates the patterning of device layer 706H, to form the insulating pattern structure 740H being encapsulated by dielectric 742G.In addition, although do not specifically illustrate in Fig. 7 H, the upper surface of device layer 706H is exposed with further patterning, comprises that the upper part that is different from lower part by patterning forms asymmetric pattern structure 706H.Device layer 706H can be exposed to other patterning/technology, comprises implanted ions.
Fig. 7 I illustrates the parts 710I that is attached to device layer 706I corresponding to pattern structure 708I.Parts 710I can be engaged to device layer 706I by wafer.Parts 710I also can the III-V family extension based on III-V family layer extension being transferred on device layer 7061 shift (for example, component layer is integrated with mixing of device layer 706I) and be fabricated on device layer 706I.Parts 710I is attached to device layer 706I so that optical mode state region 730I can be formed.The formation of parts 710I can comprise electrode pattern.Therefore, multiple parts (for example, insulating pattern structure 740I and parts 710I) can be put on same device Platform, comprise thermal insulation/insensitive/tuning and heat generator part.The formation of insulating pattern structure 740I can comprise the formation of heater section, to affect the thermal environment of insulating pattern structure 740I, for example, comes the top of packaging insulating pattern structure 740I with covering, and on covering, forms heater section.
Fig. 7 J illustrates the insulating pattern structure 740J that comprises the air gap 744J being associated with dielectric 742J.Air gap 744J can be by optionally etching dielectric 742J, exposing metal layer 760J form.In addition, the thickness of air gap 744J can for example, be accurately controlled based on dielectric formation (, referring to Fig. 7 B), so that the tuning performance of the thickness that relates to air gap 744J to be provided.Diamond layer 704J can be with device layer 706J, comprise that insulating pattern structure 740J and the pattern structure 708J of dielectric 742J/ metal level 760J are harmonious.Based on above-described manufacture method, various feature can be embedded in hot property and other benefit in the hope of strengthening in diamond layer 704J.
Range of the present invention and model are not limited by any in the above example admittedly should, and should limit according to claims and equivalent thereof.

Claims (15)

1. a device comprises:
Substrate layer;
Be attached to the diamond layer of described substrate layer; And
Device layer, comprises by described diamond layer and the separated pattern structure of described substrate layer, wherein said diamond layer and described pattern structure are harmonious.
2. device according to claim 1, the associated parts of the end face of wherein said device layer and described pattern structure are connected, with mutual with described pattern structure.
3. device according to claim 1, the top of wherein said pattern structure with respect to the bottom of described pattern structure by asymmetric patterning.
4. device according to claim 1, wherein said device layer comprises by the insulating pattern structure of dielectric encapsulation.
5. device according to claim 4, the insulating pattern structure of wherein said device layer be at least that one of following parts are associated: (i) parts of thermal tuning, (ii) hot insensitive parts, and (iii) parts of non-heat-dissipating.
6. on a diamond, the device of silicon (SOD) comprising:
Substrate layer;
Be attached to the diamond layer of described substrate layer; And
Silicon device layer, described silicon device layer has been patterned waveguide, and is attached to described diamond layer, and wherein said diamond layer and described waveguide are harmonious.
7. device according to claim 6, wherein said diamond layer is attached to described substrate layer via at least one intermediate layer of material, and described at least one intermediate layer of material is associated with the thermal conductivity larger than the thermal conductivity of transparent insulator.
8. device according to claim 6, the end face of wherein said silicon device layer with respect to the bottom surface of described silicon device layer by asymmetric patterning, so that described waveguide is structured to: for the charge carrier being associated with described waveguide provides the path at the center of flowing through the optics mode region being associated with described waveguide.
9. device according to claim 6, the parts that wherein said waveguide connects with single transverse hybrid mode with described waveguide are associated, and wherein waveguide lateral dimension is narrower than parts lateral dimension.
10. device according to claim 6, wherein said diamond layer and described waveguide are harmonious, with form following one of at least: diamond nuclei waveguide, diamond slot wave are led, the waveguide of diamond rib, the rib of falling diamond waveguide, the waveguide of diamond nano line, the line of falling diamond nano waveguide and stripe waveguide.
11. 1 kinds of devices comprise:
Substrate layer;
Be attached to the diamond layer of described substrate layer;
Device layer, comprises by described diamond layer and the separated pattern structure of described substrate layer, wherein said diamond layer and described pattern structure are harmonious; And
Insulating pattern structure, by dielectric encapsulation, and separates with described substrate layer by described diamond layer, and wherein said diamond layer and described dielectric are harmonious.
12. devices according to claim 11, wherein said dielectric comprises air gap.
13. devices according to claim 11, further comprise the solid metal reflector being associated with described dielectric, and wherein said diamond layer is harmonious via described solid metal reflector and described dielectric.
14. devices according to claim 13, wherein said solid metal reflector is for providing the reflection of the light based on through described dielectric incident light, and wherein said light reflection is associated with the given phase relation of described incident light based on described dielectric thickness.
15. devices according to claim 11, wherein said device is hybrid device, comprise the part of silicon (SOD) on the diamond being associated with described device layer pattern structure and the silicon-on-insulator (SOI) part, wherein said device and the thermal tuning compatibility that are associated with described insulating pattern structure.
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