CN104201229B - Multijunction solar cell and preparation method thereof - Google Patents
Multijunction solar cell and preparation method thereof Download PDFInfo
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- CN104201229B CN104201229B CN201410476796.8A CN201410476796A CN104201229B CN 104201229 B CN104201229 B CN 104201229B CN 201410476796 A CN201410476796 A CN 201410476796A CN 104201229 B CN104201229 B CN 104201229B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 230000000694 effects Effects 0.000 claims abstract description 15
- 230000005641 tunneling Effects 0.000 claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 3
- 230000003111 delayed effect Effects 0.000 claims description 2
- 230000026267 regulation of growth Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 60
- 239000004065 semiconductor Substances 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000013082 photovoltaic technology Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0725—Multiple junction or tandem solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0735—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/544—Solar cells from Group III-V materials
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a kind of multijunction solar cell and preparation method thereof, its structure at least includes the first sub-battery and the second sub-battery of lattice mismatch, one graded buffer layer is formed between described first, second sub-battery, one tunnel junctions is inserted in described graded buffer layer, described tunnel junctions and both sides graded buffer layer mismatch, have stress equilibrium and tunneling effect simultaneously.The present invention tunnels through knot and embeds in the middle of the graded buffer layer of the multijunction cell that there is lattice mismatch, tunnel junctions and both sides graded buffer layer mismatch, both sides Interfacial Dislocations is concentrated, threading dislocation can distort at this layer, turns to or fall into oblivion, avoid threading dislocation and have source region sliding to P N, effectively reduce interface dislocation density, and balance two lateral stresses to a certain extent.
Description
Technical field
The present invention relates to a kind of multijunction solar cell and preparation method thereof, belong to technical field of semiconductor.
Background technology
In the last few years, along with the development of condensation photovoltaic technology, III-V race's compound semiconductor solar cell increasingly received publicity because of its high-photoelectric transformation efficiency.
Group Ⅲ-Ⅴ compound semiconductor field is sayed, absorb solar energy in order to more, multijunction solar cell is suggested, the semiconductor element with different energy gap is stacked by it, and the semiconductor material layer of the most available multiple different energy gaps absorbs the sunlight of different-energy respectively to promote photoelectric transformation efficiency.In many knot Group III-V semiconductor tandem solar cells, owing to each point of battery is made up of p-n junction, if be directly cascaded, then reverse-biased and non-conductive due to p-n knot, use tunnel junction structure can solve this problem.
If it is possible to provide the tunnel knot of high tunnelling current, the light conversion efficiency of multijunction solar cell can be effectively improved.
Summary of the invention
It is an object of the invention to provide a kind of multijunction solar cell of tunnel knot with high tunnelling current and preparation method thereof.Tradition tunnel junctions and the two subcell Lattice Matchings being connected, adulterate higher, and band gap is high, utilizes tunneling effect that the series connection of sub-battery is formed electrical return.The present invention proposes a kind of embedded tunnel junctions, tunnels through knot and embeds in the middle of the graded buffer layer of the multijunction cell that there is the sub-battery of lattice mismatch, and tunnel junctions and both sides graded buffer layer mismatch have stress equilibrium and tunneling effect simultaneously.
According to the first aspect of the invention, a kind of multijunction solar cell, at least include the first sub-battery and the second sub-battery of lattice mismatch, one graded buffer layer is formed between described first, second sub-battery, one tunnel junctions is inserted in described graded buffer layer, described tunnel junctions and both sides graded buffer layer mismatch, have stress equilibrium and tunneling effect simultaneously.
Preferably, the material of described graded buffer layer can be InxAl1-xP, InxGa1-xP, InxGa1-xAs or InAlGaAs etc..
Preferably, the lattice paprmeter of described tunnel junctions and the lattice constant mismatch of both sides graded buffer layer, preferably it is slightly larger than the lattice paprmeter of both sides graded buffer layer.Preferably, described multijunction solar cell structure also includes one the 3rd sub-battery, and it is connected with described second sub-battery, and described three knot batteries constitute upside-down mounting battery, the wherein lattice constant match of second, third sub-battery.
Preferably, described tunnelling becomes n++/p++-InGaP or n++/p++-AlInGaAs.
According to the second aspect of the invention, the preparation method of multijunction solar cell, including the sub-battery of at least form lattice mismatch first, second and a graded buffer layer, the graded buffer layer of described formation is formed between first, second sub-battery, and it is inserted into a tunnel junctions at the graded buffer layer of described formation, the tunnel junctions of described formation and both sides graded buffer layer mismatch, have stress equilibrium and tunneling effect simultaneously.
Preferably, including forming one the 3rd sub-battery, its lattice paprmeter is mated with the second sub-battery.
Preferably, the preparation method of multijunction solar cell, including below step: 1) growth substrates, the most successively sub-battery of upside-down mounting growth regulation three, the second sub-battery are provided, its lattice paprmeter is mated with described growth substrates；2) at the bottom of the second sub-battery Epitaxial growth one graded buffer layer of described formation；3) gradual change in described formation is delayed and is formed a tunnel junctions on layer bottom；4) in the tunnel junctions of described formation, continue epitaxial growth graded buffer layer so that the tunnel junctions of described formation is inserted in graded buffer layer, and with both sides graded buffer layer mismatch, there is stress equilibrium and tunneling effect simultaneously；5) on described graded buffer layer, upside-down mounting grows the first sub-battery, its lattice paprmeter and second, third sub-battery mismatch described.
Preferably, the lattice paprmeter of the tunnel junctions of described formation and the lattice constant mismatch of both sides graded buffer layer.
In the present invention, the tunnel junctions connected between first, second sub-battery is inserted in graded buffer layer, with both sides graded buffer layer mismatch, both sides Interfacial Dislocations is concentrated, threading dislocation can distort at this layer, turns to or fall into oblivion, avoid threading dislocation to P-N junction active area sliding, effectively reduce interface dislocation density；Two lateral stresses can also be balanced to a certain extent simultaneously, while itself undertaking tradition tunnel junctions tunneling effect, the short circuit current that the electric leakage effect offer of high density dislocation is extra can also be passed through, it functions as the combination of short circuit metal layer and tunnel junctions, series resistance can be effectively reduced, improve fill factor, curve factor and electricity conversion.
Other features and advantages of the present invention will illustrate in the following description, and, partly become apparent from description, or understand by implementing the present invention.The purpose of the present invention and other advantages can be realized by structure specifically noted in description, claims and accompanying drawing and be obtained.
Accompanying drawing explanation
Accompanying drawing is for providing a further understanding of the present invention, and constitutes a part for description, is used for together with embodiments of the present invention explaining the present invention, is not intended that limitation of the present invention.Additionally, accompanying drawing data are to describe summary, it is not drawn to scale.
Fig. 1 is the structural representation of a kind of solaode implemented according to the present invention.
Fig. 2 is the structural representation of the three-joint solar cell of present pre-ferred embodiments.
In figure, each label represents:
110: upper sub-battery structure；
120: graded buffer layer I；
130: the tunnel junctions of embedding；
140: graded buffer layer II；
150: under sub-battery structure；
200: substrate；
210: the first sub-batteries；
220: the second sub-batteries；
230: the three sub-batteries；
240: graded buffer layer；
250: embed the tunnel junctions of graded buffer layer；
260: the tunnel junctions of second, third sub-battery.
Detailed description of the invention
The details of the present invention be will now be described, comprise exemplary aspect and the embodiment of the present invention.Referring to diagram and following description, identical Ref. No. is used for identifying identical or functionally similar element, and is intended to the highly simplified exemplary principal character implementing row of graphic mode explanation.
The multijunction solar cell of the present invention is tunneling through in the middle of knot embedding graded buffer layer, tunnel junctions and both sides graded buffer layer mismatch, both sides Interfacial Dislocations is concentrated, threading dislocation can distort at this layer, turns to or fall into oblivion, avoid threading dislocation to P-N junction active area sliding, effectively reduce interface dislocation density, and balance two lateral stresses to a certain extent.
Fig. 1 shows the structural representation of a kind of solaode according to embodiments of the present invention, and it includes the most successively: upper sub-battery structure 110, graded buffer layer I 120, tunnel junctions 130, graded buffer layer II 140 and the lower sub-battery structure 150 of embedding.
Concrete, upper sub-battery structure 110 can be single junction cell can also be that upside-down mounting grows can also be for the structure of formal dress growth for series connection many knots battery structure；Same lower sub-battery structure 150 can also can also be that upside-down mounting growth can also be for the structure of formal dress growth for series connection many knots battery structure for single junction cell.The normal mismatch of lattice between upper sub-battery structure 110 and lower sub-battery structure 150, is adjusted by graded buffer layer I, II.
Graded buffer layer I and graded buffer layer II uses homotype homogeneous material, component is different, lattice alternation, the tunnel junctions 130 being embedded into is divided into two parts, its effect balances the stress that upper and lower sub-battery lattice mismatch causes, fall low threading dislocation density, band gap should be more than the sub-battery of subsequent growth or the sub-battery of growth before according to formal dress or upside-down mounting succession.
Embedding the tunnel junctions 130 in graded buffer layer is double-deck P-N junction structure, and heavy doping is (more than E19cm-3) band gap is not less than both sides graded buffer layer 120,140, lattice and both sides graded buffer layer mismatch.Tunnel junctions 130 and both sides graded buffer layer 120,140 mismatch, both sides Interfacial Dislocations is concentrated, threading dislocation can this layer of distortion, turn to or offset, it is to avoid threading dislocation is to P-N junction active area sliding, effectively reduce interface dislocation density, and balance two lateral stresses to a certain extent.
In the present invention, while the tunnel junctions 130 in embedding graded buffer layer undertakes tradition tunnel junctions tunneling effect, moreover it is possible to provide extra electric current by the electric leakage effect of high density dislocation, it is possible to effectively reduce series resistance, improve fill factor, curve factor and electricity conversion.
Fig. 2 shows the three knot upside-down mounting solaodes implemented according to the present invention, its structure includes: first sub-battery the 210, second sub-battery 230 of sub-battery the 220, the 3rd, between first, second sub-battery, there is graded buffer layer 240, between second, third sub-battery, there is tunnel junctions 250, in the middle of graded buffer layer 260, embed a tunnel junctions 250, below in conjunction with preparation method, the more details of this multijunction solar cell are described.
First, in MOCVD system, select N-shaped doping is 9 to (111) crystal face drift angle0GaAs substrate 200, thickness is at 350 microns, and doping content is 1 × 1018cm-3 -- 4×1018cm-3Between.
Next step, growth InGaP etching cutoff layer, n+-AlInP window, n+-InGaP launch site, p+-InGaP base and p+-AlInGaP back surface field layer the most on this substrate, thus form the sub-battery 230 of InGaP the 3rd.
Next step, grow p++-AlGaAs/n++-InGaP tunnel junctions 260 on the 3rd sub-battery.
Next step, grow n+-AlInP Window layer, n+-GaAs launch site and p+-GaAs base, p+-AlGaAs back surface field layer in tunnel junctions 150 successively, thus form the sub-battery of GaAs second 220.
Next step, upside-down mounting growth InAlGaAs graded buffer layer 240 above the sub-battery of GaAs second 120, Al component remains 0.4, and In content gradually variational increases, the corresponding gradual change of Ga component reduces, and lattice paprmeter incrementally increases and incrementally increased to In by the 0.56533nm of original GaAs0.3Ga0.7As 0.5775 nm.In the present embodiment, InAlGaAs graded buffer layer 240 comprises 10 layers, and every layer of In component increases by 0.03, and along with the increase of In component in growth course, every 2 layer growth temperature reduce by 5 degree；Each thickness in monolayer is about 250nm, doping 1 × 1018cm-3Left and right.N++/p++-In is inserted in the middle of the layer 5 and layer 6 of InAlGaAs graded buffer layer0.773Ga0.227P tunnel junctions 250, its lattice paprmeter is 0.578nm, slightly larger than target lattice paprmeter (In0.3Ga0.7As) and both sides InAlGaAs graded buffer layer, itself has stress equilibrium and tunneling effect simultaneously.
Next step, sequentially form InAlGaAs Window layer, n+-InGaAs launch site, P+-InGaAs base, InAlGaAs back surface field layer on InAlGaAs graded buffer layer 240, thus form the sub-battery of InGaAs first 210.
Method obtains the epitaxial wafer of inverted triple-junction solaode as described above, after the epitaxial growth of battery terminates, enters etching, the stripping of the first substrate, the bonding of the second substrate, bonding, antireflective film is deposited with, electrode such as prepares at the technical process, completes the preparation of whole battery.
Claims (10)
1. multijunction solar cell, at least include the first sub-battery and the second sub-battery of lattice mismatch, one graded buffer layer is formed between described first, second sub-battery, one tunnel junctions is inserted in described graded buffer layer, described tunnel junctions and both sides graded buffer layer mismatch, have stress equilibrium and tunneling effect simultaneously.
Multijunction solar cell the most according to claim 1, it is characterised in that: the band gap of described tunnel junctions is not less than both sides graded buffer layer.
Multijunction solar cell the most according to claim 1, it is characterised in that: the lattice paprmeter of described tunnel junctions is more than the lattice paprmeter of both sides graded buffer layer.
Multijunction solar cell the most according to claim 1, it is characterised in that: graded buffer layer is divided into upper and lower two parts by described tunnel junctions, and described upper and lower two-part graded buffer layer uses homotype homogeneous material, component difference, lattice alternation.
Multijunction solar cell the most according to claim 1, it is characterised in that: also including one the 3rd sub-battery, it is connected with described second sub-battery.
Multijunction solar cell the most according to claim 5, it is characterised in that: described first sub-battery, the second sub-battery, the 3rd sub-battery constitute upside-down mounting battery, the wherein lattice constant match of second, third sub-battery.
7. the preparation method of multijunction solar cell, including the sub-battery of at least form lattice mismatch first, second and a graded buffer layer, the graded buffer layer of described formation is formed between first, second sub-battery, and it is inserted into a tunnel junctions at the graded buffer layer of described formation, the tunnel junctions of described formation and both sides graded buffer layer mismatch, have stress equilibrium and tunneling effect simultaneously.
8. according to the preparation method of the multijunction solar cell shown in claim 7, also including being formed one the 3rd sub-battery, its lattice paprmeter is mated with the second sub-battery.
The preparation method of the multijunction solar cell shown in the most according to Claim 8, including below step:
1) providing a growth substrates, the most successively sub-battery of upside-down mounting growth regulation three, the second sub-battery, its lattice paprmeter is mated with described growth substrates；
2) at the bottom of the second sub-battery Epitaxial growth one graded buffer layer of described formation；
3) gradual change in described formation is delayed and is formed a tunnel junctions on layer bottom；
4) in the tunnel junctions of described formation, continue epitaxial growth graded buffer layer so that the tunnel junctions of described formation is inserted in graded buffer layer, and with both sides graded buffer layer mismatch, there is stress equilibrium and tunneling effect simultaneously；
5) on described graded buffer layer, upside-down mounting grows the first sub-battery, its lattice paprmeter and second, third sub-battery mismatch described.
The preparation method of multijunction solar cell the most according to claim 7, it is characterised in that: the lattice paprmeter of the tunnel junctions of described formation is more than the lattice paprmeter of both sides graded buffer layer.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5009719A (en) * | 1989-02-17 | 1991-04-23 | Mitsubishi Denki Kabushiki Kaisha | Tandem solar cell |
| CN102709349A (en) * | 2012-06-21 | 2012-10-03 | 厦门乾照光电股份有限公司 | Wide-band gap multi-heterojunction tunnel junction structure |
| CN102790119A (en) * | 2012-07-19 | 2012-11-21 | 中国科学院苏州纳米技术与纳米仿生研究所 | GaInP/GaAs/Ge/Ge four-junction solar cell and preparation method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5009719A (en) * | 1989-02-17 | 1991-04-23 | Mitsubishi Denki Kabushiki Kaisha | Tandem solar cell |
| CN102709349A (en) * | 2012-06-21 | 2012-10-03 | 厦门乾照光电股份有限公司 | Wide-band gap multi-heterojunction tunnel junction structure |
| CN102790119A (en) * | 2012-07-19 | 2012-11-21 | 中国科学院苏州纳米技术与纳米仿生研究所 | GaInP/GaAs/Ge/Ge four-junction solar cell and preparation method thereof |
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