CN104298645A - Flexibly configured programmable system-on-chip chip and starting configuration method thereof - Google Patents
Flexibly configured programmable system-on-chip chip and starting configuration method thereof Download PDFInfo
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- CN104298645A CN104298645A CN201410529305.1A CN201410529305A CN104298645A CN 104298645 A CN104298645 A CN 104298645A CN 201410529305 A CN201410529305 A CN 201410529305A CN 104298645 A CN104298645 A CN 104298645A
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Abstract
The invention discloses a flexibly configured programmable system-on-chip chip and a starting configuration method thereof. The chip comprises a kernel module, an on-chip bus, a starting configuration module, a system control module, a storage control module, a floating-point calculation speed-up module, a direct memory access (DMA) control module, a universal external port control module, an embedded storage module and an embedded field programmable gate array (FPGA). By means of the flexibly configured programmable system-on-chip chip and the starting configuration method thereof, various configurations of the FPGA can be achieved through the embedded storage module or an external storer, and diversification of FPGA configuration modes can be effectively improved; by means of any external arrangement of a universal port mounted on bus resources, flexible configuration of the FPGA can be finished, and problems that single configuration mode exists and object-oriented configuration according to practical application cannot be achieved can be effectively solved; after starting of the kernel module, FPGA configuration modes can be guided, the FPGA configuration process can be controlled, and the controllability of the configuration process can be effectively improved; the flexibly configured programmable system-on-chip chip and the starting configuration method thereof are widely applicable to the field of integrated circuits.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of can flexible configuration programmable system on chip chip and start collocation method.
Background technology
Along with the development of microelectric technique, SOC has become the focus that IC designs industry.SOC performance is more and more stronger, and scale is increasing.The scale of SOC is generally much larger than common ASIC, and simultaneously due to the difficult design etc. that deep submicron process brings, the complexity that SOC is designed improves greatly.Especially, short run application or the SOC for the development phase are only for some, produce if drop into flow at once, need to drop into more fund, bear larger trial-production risk.SOPC(System on a Programmable Chip, programmable system on chip) technology then provides a kind of effective solution.
Relatively traditional designing technique, SOPC can better meet the actual demands such as systematization, networking, high speed, low-power consumption, the functional module that the systems such as processor, storer, Peripheral Interface and multi-level user circuit need is integrated on chip piece by it, adopts IP reuse, Hardware/Software Collaborative Design, method that is top-down and that design from end downmix in a large number.Because it is flexible, efficient, design reusable characteristic, SOPC has become the developing direction in integrated circuit future, is widely applied to the fields such as automobile, military affairs, Aero-Space, thermometrically, consumer electronics, radio communication, medical treatment.
Because SOPC inside is integrated with FPGA, need carry out suitable configuration to FPGA, traditional configuration mode mainly comprises parallel holotype, master slave mode, serial mode and peripheral mode etc.The configuration mode of this several configuration mode is all more single, cannot be configured according to practical application by object-oriented.
Summary of the invention
In order to solve the problems of the technologies described above, the object of this invention is to provide the variation of a kind of configuration mode, can according to practical application be configured a kind of can the programmable system on chip chip of flexible configuration.
Another object of the present invention is to provide one and can be configured according to practical application, and a kind of of layoutprocedure controllability can be improved can the programmable system on chip chip enable collocation method of flexible configuration.
The technical solution adopted in the present invention is:
A kind of can the programmable system on chip chip of flexible configuration, comprise kernel module, on-chip bus, start configuration module, system control module, storage control module, floating-point operation accelerating module, DMA control module, Universal peripheral interface control module, embedded memory module and embedded FPGA, described on-chip bus respectively with startup configuration module, system control module, storage control module, floating-point operation accelerating module, DMA control module, Universal peripheral interface control module is connected with kernel module, described startup configuration module respectively with kernel module, embedded memory module is connected with embedded FPGA, described DMA control module is connected with Universal peripheral interface control module.
As described a kind of can the further improvement of programmable system on chip chip of flexible configuration, described kernel module includes embedded system kernel, cache module, memory management module and on-chip bus interface control module, described embedded system kernel is connected with startup configuration module, cache module, memory management module and on-chip bus interface control module respectively, and described on-chip bus interface control module is connected with on-chip bus.
As described a kind of can the further improvement of programmable system on chip chip of flexible configuration, described embedded FPGA comprises configurable logic blocks and input/output module, and described configurable logic blocks is connected with startup configuration module by input/output module.
As described a kind of can the further improvement of programmable system on chip chip of flexible configuration, described embedded memory module is SPI FLASH chip.
As described a kind of can the further improvement of programmable system on chip chip of flexible configuration, described storage control module is also connected with external memory storage.
As described a kind of can the further improvement of programmable system on chip chip of flexible configuration, described external memory storage is NOR FLASH chip or NAND FLASH chip or SPI FLASH chip.
As described a kind of can the further improvement of programmable system on chip chip of flexible configuration, described Universal peripheral interface control module comprises 1553B interface controller, LVDS interface controller, UART interface controller, 429 interface controllers, SPI interface controller, I2C interface controller and CAN interface controller.
Another technical scheme of the present invention is:
Can the programmable system on chip chip enable collocation method of flexible configuration, comprise the following steps:
A, described startup configuration module start data-moving in the cache module of kernel module from the kernel embedded memory module or external memory storage;
B, according to kernel start data, reading command also performs electrifying startup program;
C, by the deposit position of FPGA configuration data notice to starting configuration module;
D, deposit position according to FPGA configuration data, started configuration module and be loaded in embedded FPGA by FPGA configuration data by dma mode.
As described a kind of can the further improvement of programmable system on chip chip enable collocation method of flexible configuration, described deposit position comprises embedded memory module, external memory storage and Universal peripheral interface control module and controls the relevant interface peripheral hardware that on-chip bus is connected.
The invention has the beneficial effects as follows:
The present invention is a kind of the programmable system on chip chip of flexible configuration can realize to FPGA by embedded memory module or peripheral memory various configuration, effectively can improve the variation of FPGA configuration mode.But also any peripheral hardware of the general-purpose interface of carry on bus resource can be relied on, carried out the flexible configuration to FPGA, efficiently solve configuration mode single, cannot the problem that is configured according to practical application of object-oriented.
Another beneficial effect of the present invention is:
The present invention is a kind of the programmable system on chip chip enable collocation method of flexible configuration can realize to FPGA by embedded memory module or peripheral memory various configuration, effectively can improve the variation of FPGA configuration mode.But also any peripheral hardware of the general-purpose interface of carry on bus resource can be relied on, carried out the flexible configuration to FPGA, efficiently solve configuration mode single, cannot the problem that is configured according to practical application of object-oriented.The present invention after kernel module starts, can dominate the mode of FPGA configuration, the process that control FPGA configures, and effectively improves the controllability of layoutprocedure.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further:
Fig. 1 is that the present invention is a kind of can the functional-block diagram of programmable system on chip chip of flexible configuration;
Fig. 2 is that the present invention is a kind of can the functional-block diagram of kernel module in the programmable system on chip chip of flexible configuration;
Fig. 3 is that the present invention is a kind of can the functional-block diagram of embedded FPGA in the programmable system on chip chip of flexible configuration;
Fig. 4 is that the present invention is a kind of can the flow chart of steps of programmable system on chip chip enable collocation method of flexible configuration.
Embodiment
With reference to figure 1, the present invention is a kind of can the programmable system on chip chip of flexible configuration, comprise kernel module, on-chip bus, start configuration module, system control module, storage control module, floating-point operation accelerating module, DMA control module, Universal peripheral interface control module, embedded memory module and embedded FPGA, described on-chip bus respectively with startup configuration module, system control module, storage control module, floating-point operation accelerating module, DMA control module, Universal peripheral interface control module is connected with kernel module, described startup configuration module respectively with kernel module, embedded memory module is connected with embedded FPGA, described DMA control module is connected with Universal peripheral interface control module.
With reference to figure 2, as described a kind of can the further improvement of programmable system on chip chip of flexible configuration, described kernel module includes embedded system kernel, cache module, memory management module and on-chip bus interface control module, described embedded system kernel is connected with startup configuration module, cache module, memory management module and on-chip bus interface control module respectively, and described on-chip bus interface control module is connected with on-chip bus.Described kernel module major function has been that the entirety of programmable system on chip of the present invention controls.
With reference to figure 3, as described a kind of can the further improvement of programmable system on chip chip of flexible configuration, described embedded FPGA comprises configurable logic blocks and input/output module, and described configurable logic blocks is connected with startup configuration module by input/output module.Function and usage comprises several Clock Managing Unit, hundreds thousand of equivalent logic door, more than 100 input/output port, also interconnected by Embedded on-chip bus and kernel module, support Multiple Interrupt, realize hardware programmable capability of the present invention.
As described a kind of can the further improvement of programmable system on chip chip of flexible configuration, described embedded memory module is SPI FLASH chip.Described embedded memory module mainly completes storage kernel being started to data and embedded FPGA configuration data, is transfer rate and all configurable SPI Flash chip of read-write frequency in specific embodiment in the present invention.
As described a kind of can the further improvement of programmable system on chip chip of flexible configuration, described storage control module is also connected with external memory storage.
As described a kind of can the further improvement of programmable system on chip chip of flexible configuration, described external memory storage is NOR FLASH chip or NAND FLASH chip or SPI FLASH chip.
As described a kind of can the further improvement of programmable system on chip chip of flexible configuration, described Universal peripheral interface control module comprises 1553B interface controller, LVDS interface controller, UART interface controller, 429 interface controllers, SPI interface controller, I2C interface controller and CAN interface controller.Described Universal peripheral interface control module can arrange the external unit of the corresponding interface of carry on described on-chip bus by register as main control end, and send the read-write operation that data are carried out in order.
Described startup configuration module mainly completes the function of two parts.First, automatically loading startup data in described embedded memory module or external memory storage when powering on to kernel module, then discharging reset signal, make kernel module instruction fetch run start-up routine; Secondly, after kernel normally starts, the configuration according to kernel module moves FPGA configuration data to described embedded FPGA from corresponding module.
Described floating-point operation accelerating module, support the calculation functions such as sine function, cosine function, evolution, comprise to zero rounding, the multiple rounding mode such as to round to idol, the multiple interruption such as invalid operation, non-specification number input can be produced, be conducive to improving calculation processing power of the present invention.
Described system control module is mainly used in arranging the clock frequency of system, clock division setting, multiplexed port, gated clock are enable etc., and function is configured.
Described DMA control module mainly completes carries out dma operation to the data of each module of described on-chip bus carry and register, comprise the configurable multiple data channel of priority, support that memory-to-memory, internal memory are to external memory storage, external memory storage to internal memory, external memory storage to multiple transmission modes such as external memory storages.
Described storage control module can support the storer of sdram interface, SRAM interface and Flash interface, and major function comprises signals such as producing the address of memory access, data and control, the read-write of control store and related register.
With reference to figure 4, the present invention is a kind of can the programmable system on chip chip enable collocation method of flexible configuration, comprises the following steps:
A, described startup configuration module start data-moving in the cache module of kernel module from the kernel embedded memory module or external memory storage;
B, according to kernel start data, reading command also performs electrifying startup program;
C, by the deposit position of FPGA configuration data notice to starting configuration module;
D, deposit position according to FPGA configuration data, started configuration module and be loaded in embedded FPGA by FPGA configuration data by dma mode.
As described a kind of can the further improvement of programmable system on chip chip enable collocation method of flexible configuration, described deposit position comprises embedded memory module, external memory storage and Universal peripheral interface control module and controls the relevant interface peripheral hardware that on-chip bus is connected.
Embodiment 1, in the present embodiment, chip core starts deposit data in embedded memory module, and described embedded memory module is SPI Flash chip in the present embodiment, FPGA configuration data leaves in external memory storage, and described external memory storage is NOR Flash chip in the present embodiment.
Kernel is first started data and moves the internal memory of chip core module from SPI Flash chip by S11, startup configuration module, saves as the high-speed cache that kernel is integrated in described.After data-moving completes, chip core instruction fetch from internal memory performs electrifying startup program;
S12, after kernel module completes startup, kernel module can notify start configuration module, FPGA configuration data leaves in external memory storage, and described external memory storage is NOR Flash chip in the present embodiment.Meanwhile, kernel module also can configure the offset address of FPGA configuration data in NOR Flash chip;
After S13, startup configuration module start, according to the configuration of kernel module to NOR Flash chip offset address, by the mode of DMA FPGA configuration data moved the configuration interface part in embedded FPGA from NOR Flash chip, realize the configuration to embedded FPGA.
Embodiment 2, in the present embodiment, chip core starts deposit data in external memory storage, described external memory storage is NAND Flash chip in the present embodiment, FPGA configuration data leaves on the relevant interface peripheral hardware that the on-chip bus carry that controlled by Universal peripheral interface control module, the SPI Flash of described external memory storage in the present embodiment for being controlled by SPI controller.
Kernel is first started data and moves the internal memory of chip core module from NAND Flash chip by on-chip bus by S21, startup configuration module, saves as the high-speed cache that kernel is integrated in described.After data-moving completes, chip core instruction fetch from internal memory performs electrifying startup program;
S22, after kernel completes startup, kernel module can notify start configuration module, FPGA configuration data leave in Universal peripheral interface control module control peripheral hardware in, described peripheral hardware in the present embodiment for SPI controller control SPI Flash chip.Meanwhile, kernel module also can configure the offset address of FPGA configuration data in SPI Flash chip;
After S23, startup configuration module start, according to the configuration of kernel module to SPI Flash chip offset address, by the mode of DMA FPGA configuration data moved the configuration interface part in embedded FPGA from SPI Flash chip, realize the configuration to embedded FPGA.
More than that better enforcement of the present invention is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to spirit of the present invention, and these equivalent distortion or replacement are all included in the application's claim limited range.
Claims (9)
1. one kind can the programmable system on chip chip of flexible configuration, it is characterized in that: comprise kernel module, on-chip bus, start configuration module, system control module, storage control module, floating-point operation accelerating module, DMA control module, Universal peripheral interface control module, embedded memory module and embedded FPGA, described on-chip bus respectively with startup configuration module, system control module, storage control module, floating-point operation accelerating module, DMA control module, Universal peripheral interface control module is connected with kernel module, described startup configuration module respectively with kernel module, embedded memory module is connected with embedded FPGA, described DMA control module is connected with Universal peripheral interface control module.
2. according to claim 1 a kind of can the programmable system on chip chip of flexible configuration, it is characterized in that: described kernel module includes embedded system kernel, cache module, memory management module and on-chip bus interface control module, described embedded system kernel is connected with startup configuration module, cache module, memory management module and on-chip bus interface control module respectively, and described on-chip bus interface control module is connected with on-chip bus.
3. according to claim 1 a kind of can the programmable system on chip chip of flexible configuration, it is characterized in that: described embedded FPGA comprises configurable logic blocks and input/output module, described configurable logic blocks is connected with startup configuration module by input/output module.
4. according to claim 1 a kind of can the programmable system on chip chip of flexible configuration, it is characterized in that: described embedded memory module is SPI FLASH chip.
5. according to claim 1 a kind of can the programmable system on chip chip of flexible configuration, it is characterized in that: described storage control module is also connected with external memory storage.
6. according to claim 5 a kind of can the programmable system on chip chip of flexible configuration, it is characterized in that: described external memory storage is NOR FLASH chip or NAND FLASH chip or SPI FLASH chip.
7. according to claim 1 a kind of can the programmable system on chip chip of flexible configuration, it is characterized in that: described Universal peripheral interface control module comprises 1553B interface controller, LVDS interface controller, UART interface controller, 429 interface controllers, SPI interface controller, I2C interface controller and CAN interface controller.
8. can the programmable system on chip chip enable collocation method of flexible configuration, it is characterized in that: comprise the following steps:
A, described startup configuration module start data-moving in the cache module of kernel module from the kernel embedded memory module or external memory storage;
B, according to kernel start data, reading command also performs electrifying startup program;
C, by the deposit position of FPGA configuration data notice to starting configuration module;
D, deposit position according to FPGA configuration data, started configuration module and be loaded in embedded FPGA by FPGA configuration data by dma mode.
9. according to claim 8 a kind of can the programmable system on chip chip enable collocation method of flexible configuration, it is characterized in that: described deposit position comprises embedded memory module, external memory storage and Universal peripheral interface control module and controls the relevant interface peripheral hardware that on-chip bus is connected.
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105988796A (en) * | 2015-02-12 | 2016-10-05 | 深圳市腾讯计算机系统有限公司 | Reconfigurable computing platform |
CN106469075A (en) * | 2015-08-20 | 2017-03-01 | 瑞昱半导体股份有限公司 | Storage device, the method for start quickly program and store controller |
CN111198718A (en) * | 2019-12-27 | 2020-05-26 | 广东高云半导体科技股份有限公司 | FPGA-based processor starting method and processor |
CN112506437A (en) * | 2020-12-10 | 2021-03-16 | 上海阵量智能科技有限公司 | Chip, data moving method and electronic equipment |
CN112835842A (en) * | 2021-03-05 | 2021-05-25 | 深圳市汇顶科技股份有限公司 | Terminal sequence processing method, circuit, chip and electronic terminal |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6704816B1 (en) * | 1999-07-26 | 2004-03-09 | Sun Microsystems, Inc. | Method and apparatus for executing standard functions in a computer system using a field programmable gate array |
CN101634071A (en) * | 2009-08-13 | 2010-01-27 | 浙江理工大学 | Electronic jacquard machine control system based on FPGA |
CN101833534A (en) * | 2010-03-17 | 2010-09-15 | 无锡市同威科技有限公司 | FPGA (Field Programmable Gate Array) high-performance operating PCI (Peripheral Component Interconnect) card |
CN103257612A (en) * | 2012-02-21 | 2013-08-21 | 京微雅格(北京)科技有限公司 | Flexibly configured field-programmable gate array (FPGA) chip and configuration method thereof |
-
2014
- 2014-10-09 CN CN201410529305.1A patent/CN104298645A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6704816B1 (en) * | 1999-07-26 | 2004-03-09 | Sun Microsystems, Inc. | Method and apparatus for executing standard functions in a computer system using a field programmable gate array |
CN101634071A (en) * | 2009-08-13 | 2010-01-27 | 浙江理工大学 | Electronic jacquard machine control system based on FPGA |
CN101833534A (en) * | 2010-03-17 | 2010-09-15 | 无锡市同威科技有限公司 | FPGA (Field Programmable Gate Array) high-performance operating PCI (Peripheral Component Interconnect) card |
CN103257612A (en) * | 2012-02-21 | 2013-08-21 | 京微雅格(北京)科技有限公司 | Flexibly configured field-programmable gate array (FPGA) chip and configuration method thereof |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105988796A (en) * | 2015-02-12 | 2016-10-05 | 深圳市腾讯计算机系统有限公司 | Reconfigurable computing platform |
CN105988796B (en) * | 2015-02-12 | 2019-01-11 | 深圳市腾讯计算机系统有限公司 | A kind of restructurable computing system |
CN106469075A (en) * | 2015-08-20 | 2017-03-01 | 瑞昱半导体股份有限公司 | Storage device, the method for start quickly program and store controller |
CN111198718A (en) * | 2019-12-27 | 2020-05-26 | 广东高云半导体科技股份有限公司 | FPGA-based processor starting method and processor |
WO2022027847A1 (en) * | 2020-08-07 | 2022-02-10 | 航天科工微电子系统研究院有限公司 | Soc chip structure applied to fuse control system |
CN112506437A (en) * | 2020-12-10 | 2021-03-16 | 上海阵量智能科技有限公司 | Chip, data moving method and electronic equipment |
CN112835842A (en) * | 2021-03-05 | 2021-05-25 | 深圳市汇顶科技股份有限公司 | Terminal sequence processing method, circuit, chip and electronic terminal |
CN117034827A (en) * | 2023-10-08 | 2023-11-10 | 华中科技大学 | Multi-path selector, interconnection switch and peripheral interface circuit for eFPGA |
CN117034827B (en) * | 2023-10-08 | 2023-12-15 | 华中科技大学 | Multi-path selector, interconnection switch and peripheral interface circuit for eFPGA |
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