CN104348587A - Single-wire signal transmission device and transmission method - Google Patents

Single-wire signal transmission device and transmission method Download PDF

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Publication number
CN104348587A
CN104348587A CN201310351403.6A CN201310351403A CN104348587A CN 104348587 A CN104348587 A CN 104348587A CN 201310351403 A CN201310351403 A CN 201310351403A CN 104348587 A CN104348587 A CN 104348587A
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CN
China
Prior art keywords
pulse
signal
data
preset range
controller
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CN201310351403.6A
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Chinese (zh)
Inventor
林信佑
冯连兴
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Holtek Semiconductor Inc
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Holtek Semiconductor Inc
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Publication of CN104348587A publication Critical patent/CN104348587A/en
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B14/00Transmission systems not characterised by the medium used for transmission
    • H04B14/02Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation

Abstract

A single-wire signal transmission device and a transmission method are provided, wherein the single-wire signal transmission device comprises a signal receiving interface and a controller. The signal receiving interface receives a receiving data signal on the transmission line, wherein the receiving data signal has a plurality of pulses. The controller obtains a plurality of data signals according to detecting a pulse width of a pulse on the received data signal. When the controller judges that the pulse width of each pulse is within the first preset range, the controller judges that each data corresponding to each pulse is equal to the first logic level. When the controller determines that the pulse width of each pulse is within the second preset range, the controller determines that each data corresponding to each pulse is equal to the second logic level. The first predetermined range is not overlapped with the second predetermined range. The single-wire signal transmission device and the single-wire signal transmission method have certain fault-tolerant capability and can reduce the influence of data correctness caused by frequency drift.

Description

Single-wire signal transmitting device and transmission method
Technical field
The present invention relates to a kind of single-wire signal transmitting device and transmission method, and in particular to a kind of single-wire signal transmitting device and the transmission method with fault-tolerant ability.
Background technology
Along with the progress of electronics technology, electronic product has become instrument indispensable in people's life.And along with people are to the increase of information requirement, by carrying out the function that transfer of data is a kind of indispensability between electronic installation.Under the considering of easy to use and cost, carrying out efficient transmission by fewer transmission line, is the target that this area designer makes great efforts, and corresponding to this, a kind of so-called single-line type transmission means is suggested.
Single-line type transmission means is a kind of transmission means of asynchronous master/slave formula bus.The coded system of transmitted data bits unit wherein encodes with the voltage level signal read in fixing time slot (time slot) to become data bit element 0 or data bit element 1.But, be used as detection zone to carry out the encoding act of data bit element with fixing time slot, producing when temperature, operating voltage the interference produced in variation or environment, the data-signal that transmission line transmits may be caused to produce the phenomenon of frequency drift.The phenomenon of this frequency drift can make cannot be synchronous between data sending terminal and data receiver, and cause the generation mistake when carrying out data encoding.
Summary of the invention
The invention provides a kind of single-wire signal transmitting device and transmission method, there is high fault-tolerant ability.
Single-wire signal transmitting device of the present invention by transmission line to carry out transfer of data.Single-wire signal transmitting device comprises Signal reception interface and controller.Signal reception interface coupled transmission lines the reception data-signal received on transmission line, wherein receive data-signal and have multiple pulse.Controller couples Signal reception interface.Controller obtains multiple data according to the pulse duration detecting the pulse received on data-signal.Wherein, controller judges that the pulse duration of each pulse is when the first preset range, and controller judges that each data of corresponding each pulse equal the first logic level.When controller judges the pulse duration of each pulse between the second preset range, controller judges that each data of corresponding each pulse equal the second logic level.First preset range and the second preset range non-overlapping.
In one embodiment of this invention, above-mentioned pulse comprises at least one positive pulse and at least one negative pulse.
In one embodiment of this invention, above-mentioned each pulse is between receiving between two adjacent state switching points of data-signal.
In one embodiment of this invention, above-mentioned controller detects the pulse duration of pulse according to clock signal.
In one embodiment of this invention, the first above-mentioned preset range has the first median, and controller adjusts the frequency of clock signal according to the pulse duration of pulse and the relation of the first median.
In one embodiment of this invention, the second above-mentioned preset range has the second median, and controller adjusts the frequency of clock signal according to the pulse duration of pulse and the relation of the second median.
In one embodiment of this invention, single-wire signal transmitting device also comprises signal transmission interface.Signal transmission interface couples this controller and transmission line, and wherein, controller receives and sends data, and sends data-signal according to sending data generation.Signal transmission interface receives and sends data-signal and send out transmission data-signal by transmission line.
Single-wire signal transmission method of the present invention comprises: receive the reception data-signal on transmission line, wherein receives data-signal and has multiple pulse; When the pulse duration of each pulse is between the first preset range, judge that each data of corresponding each pulse equal the first logic level; Further, when the pulse duration of each pulse is between the second preset range, judge that respectively these data of corresponding each pulse equal the second logic level, the first preset range and the second preset range non-overlapping.
Beneficial effect of the present invention is, based on above-mentioned, single-wire signal transmitting device of the present invention and method set the first preset range and the second preset range, and to be fallen within the first preset range by the pulse duration detecting the pulse received on data-signal or in the second preset range to judge the data of respective pulses.Thus, under the state of data-signal occurrence frequency drift, single-wire signal transmitting device of the present invention and method still can effectively obtain correct data, to reduce the impact of the data correctness that frequency drift causes.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 illustrates the schematic diagram of the single-wire signal transmitting device of one embodiment of the invention.
Fig. 2 A illustrates the oscillogram of an execution mode of the reception data-signal of the embodiment of the present invention.
Fig. 2 B ~ Fig. 2 D illustrates the oscillogram of other execution modes of the reception data-signal of the embodiment of the present invention respectively.
Fig. 3 illustrates the movement oscillogram of the single-wire signal transmitting device of the embodiment of the present invention.
Fig. 4 illustrates the flow chart of the single-wire signal transmission method of one embodiment of the invention.
Wherein, description of reference numerals is as follows:
100: single-wire signal transmitting device
111: controller
112: Signal reception interface
113: signal transmission interface
110,170: electronic installation
WIR1: transmission line
PIN1: pin position
210,241,251, D01, D02, D11, D12: receive data-signal
ED1, ED2: state switching points
NPS1 ~ NPS4: negative pulse
PPS2 ~ PPS4: positive pulse
T1 ~ T5: detection time is interval
TP1: time point
CNT: count results
CK: clock signal
S410 ~ S440: the step of single-wire signal transmission
Embodiment
Below please refer to Fig. 1, Fig. 1 illustrates the schematic diagram of the single-wire signal transmitting device of one embodiment of the invention.Single-wire signal transmitting device 100 can be arranged in electronic installation 110, and wherein, single-wire signal transmitting device 100 comprises controller 111, Signal reception interface 112 and signal transmission interface 113.Electronic installation 110 is coupled to electronic installation 170 by transmission line WIR1, and carries out the action of transfer of data by transmission line WIR1 and electronic installation 170.In the present embodiment, electronic installation 110 utilizes single-wire signal transmitting device 100 and electronic installation 170 to carry out transfer of data.Wherein, Signal reception interface 112 and signal transmission interface 113 are coupled to transmission line WIR1, and controller 111 is coupled to Signal reception interface 112 and signal transmission interface 113.
Carry out in the reception of data at single-wire signal transmitting device 100, when electronic installation 110 will receive the data reached by electronic installation 170, electronic installation 170 is transmitted by transmission line WIR1 and receives the Signal reception interface 112 of data-signal to single-wire signal transmitting device 100.In the present embodiment, with electronic installation 110 be integrated circuit for example, Signal reception interface 112 connects transmission line WIR1 by pin position PIN1, and is undertaken receiving the receiving action of data-signal by pin position PIN1, wherein, receive data-signal and there is multiple pulse.
Carefully illustrate, receiving data-signal can be the digital signal with multiple state switching points, a namely signal repeatedly switched between logic high and logic low.In the present embodiment, maintained logic high and receive the positive pulse of data-signal to become by logic low transition to logic high when receiving data-signal, maintained logic low and then become the negative pulse receiving data-signal by logic high transition to logic low when receiving data-signal.Above-mentioned positive pulse and negative pulse are all between receiving between two adjacent state switching points of data-signal.
Controller 111 obtains reception data-signal by Signal reception interface 112.Further, controller 111 can detect the pulse duration received on data-signal.Referring to Fig. 1 and Fig. 2 A, wherein, Fig. 2 A illustrates the oscillogram of an execution mode of the reception data-signal of the embodiment of the present invention.In normal state, controller 111 receives data-signal 210, and the pulse duration of data detection signal 210 in detection time interval T1 and T2 respectively.For interval T1 detection time, controller 111 carries out the detection of pulse duration for the negative pulse NPS1 received between the state switching points ED1 of data-signal 210 and ED2, and when the pulse duration of negative pulse NPS1 is between the first preset range, the data that setting receives the transmission of data-signal 210 correspondence are logical one.Relative, if controller 111 detects that the pulse duration of negative pulse NPS1 is when the second preset range, the data that setting receives the transmission of data-signal 210 correspondence are logical zero.The first preset range wherein and the second preset range non-overlapping, and the first preset range is greater than the second preset range.
Furthermore bright, if with in detection time interval T1, the corresponding nominal pulse width at reception data-signal of data of logical one is 64 units is example, it is 48-80 (median is 64) unit that controller 111 can set the first preset range, and to set the second preset range be 24-40 (median is 32) unit, and the pulse duration calculated in interval T1 in detection time between 48-80 unit time, it is logical one that controller 111 can set data corresponding to negative pulse NPS1, relative, if when the pulse duration that detection time calculates in interval T1 is between 24-40 unit, it is logical zero that controller 111 can set data corresponding to negative pulse NPS1.
Can be learnt by above-mentioned explanation, when receiving data-signal 210 because when noise, temperature variations or other any reasons produce frequency drift, such as, when changing into reception data-signal 211 or 212, controller 111 more or less can change for the testing result receiving data-signal 211 or 212 pulse duration of carrying out, such as originally detected that pulse duration equaled the pulse of 64 units, after frequency drift, its pulse duration changes becomes 60 units.But because such drift does not exceed first preset range (48-80 unit) of controller 111 originally setting, therefore, the data corresponding to it still can be judged accurately to equal logical one by controller 111 and be unlikely to produce the wrongheaded phenomenon of data.
Below please refer to Fig. 1 and Fig. 2 B ~ Fig. 2 D, wherein, Fig. 2 B ~ Fig. 2 D illustrates the oscillogram of other execution modes of the reception data-signal of the embodiment of the present invention respectively.It is logical zero that the reception data-signal 221 and 231 that Fig. 2 B and Fig. 2 C illustrates respectively all represents corresponding data.Wherein, hold the continuous above-mentioned example about Fig. 2 A, controller 111 can detect the pulse duration of the negative pulse NPS2 received in data-signal 221 in detection time in interval T3, and learn the pulse duration of negative pulse NPS2 between the second preset range be between 24-40.Thus, controller 111 can set data corresponding to negative pulse NPS2 is logical zero.
It is worth mentioning that, in detection time interval T3, receive data-signal 221 and there is negative pulse NPS2 also there is positive pulse PPS2.Pulse duration due to negative pulse NPS2 and positive pulse PPS2 is complementary, and therefore, controller 111 also can carry out the setting of data according to the pulse duration with positive pulse PPS2.
In fig. 2 c, controller 111 can detect the pulse duration of the positive pulse PPS3 received in data-signal 231 in detection time in interval T4, and learn the pulse duration of positive pulse PPS3 between the second preset range be between 24-40.Thus, controller 111 can set data corresponding to positive pulse PPS3 is logical zero.Or controller 111 can detect the pulse duration of the negative pulse NPS3 received in data-signal 231 in detection time in interval T4, and uses the set action of carrying out data.
In figure 2d, controller 111 can detect in detection time the pulse duration receiving negative pulse NPS4 in data-signal 241 or 251 or positive pulse PPS4 in interval T5.And the pulse duration of foundation negative pulse NPS4 or positive pulse PPS4 is between the first preset range, and the data of setting correspondence are logical one.
Please again with reference to Fig. 1, signal transmission interface 113 couples controller 111 and transmission line WIR1.Wherein, controller 111 receives and sends data, and sends data-signal according to sending data generation.Signal transmission interface 113 is received to send data-signal and sent out by transmission line WIR1 and sends data-signal to electronic installation 170.Specifically, when sending data and equaling logical one, signal transmission interface 113 is be maintained the signal of logic high or logic low in interval in detection time by the signal that transmission line WIR1 sends out, in addition, when sending data and equaling logical zero, the signal that signal transmission interface 113 is sent out by transmission line WIR1, in detection time interval, produces the logical signal of transition close to middle time point.
Below please refer to Fig. 1 and Fig. 3, wherein, Fig. 3 illustrates the movement oscillogram of the single-wire signal transmitting device of the embodiment of the present invention.Wherein, controller 111 carries out the detection action of pulse duration by clock signal CK.That is, clock signal CK is utilized to count the pulse duration of the pulse receiving data-signal.To receive data-signal D01 for example, controller starts the counting action of the pulse duration of the pulse 131 carrying out receiving data-signal D01 at time point TP1, and can learn that according to count results CNT the pulse duration of the pulse 131 receiving data-signal D01 equals the width in the cycle of 32 clock signal CK.Thus, controller can judge that the pulse duration of the pulse 131 receiving data-signal D01 is between the second preset range by this, and the data of separating corresponding to reading are logical zero.
In like manner, the pulse duration that controller 111 also can carry out pulse 132,133 and 134 for reception data-signal D02, D11 and D12 according to clock signal CK respectively detects.Further, whether the pulse duration by detecting pulse 132,133 and 134 carries out the set action of the data of pulse 132,133 and 134 correspondence between the first preset range or the second preset range.In the present embodiment, pulse 132,133 and 134 correspondence is logical zero, " 1 " and " 1 " by the data of separating reading.
It should be noted that controller 111 according to the position of pulse duration place first preset range or the second preset range, can adjust the frequency of clock signal CK.First preset range of 64 is equaled for example with median, if when controller 111 detects the median that pulsewidth that data equal the pulse of logical one has some lower than (or higher than) first preset range, represent that receiving data-signal there occurs frequency drift action to a certain degree.Accordingly, the frequency that controller 111 carries out clock signal CK by the adjustment pulsewidth of pulse and the difference of the median of the first preset range adjusts, to make the carrying out that data transfer activity can be continual and steady.Certainly, the frequency adjustment action of above-mentioned clock signal CK also can be carried out according to the relation of the median of pulse duration and the second preset range.
Bright specifically, if when controller 111 detects the median that the pulsewidth that data equal the pulse of logical one has some lower than the first preset range, the frequency of controller 111 adjustable height clock signal CK, relative, if when controller 111 detects the median that the pulsewidth that data equal the pulse of logical one has some higher than the first preset range, controller 111 can turn down the frequency of clock signal CK.
Below please refer to Fig. 4, Fig. 4 illustrates the flow chart of the single-wire signal transmission method of one embodiment of the invention.The step of single-wire signal transmission method comprises: in step S410, sets first and second preset range; Then, in the step s 420, receive the reception data-signal on transmission line, wherein, receive data-signal and there is multiple pulse, and, in step S430, when the pulse duration of each pulse in detection time interval is between the first preset range, judge that each data of corresponding each pulse equal the first logic level (such as logical one); In step S440, when the pulse duration of each pulse in detection time interval is between the second preset range, judge that each data of corresponding each pulse equal the second logic level (such as logical zero).
About the implementation detail of above steps, there is detailed description in aforesaid embodiment and execution mode, seldom repeat below.And in the setting of first and second preset range, can be set according to the state of affiliated electronic installation practical application by designer.
In sum, the present invention carries out the set action of data corresponding to pulse by detecting the reception pulse duration of data-signal and the relation of preset range.Thus, reception data-signal transmission line transmitted is disturbed and under producing the situation of frequency drift, what the data corresponding to it still can be correct is received.Single-wire signal is transmitted there is higher fault-tolerant ability, promote the efficiency of transmission.

Claims (14)

1. a single-wire signal transmitting device, by a transmission line to carry out transfer of data, comprising:
One Signal reception interface, couple this transmission line and receive the reception data-signal on this transmission line, wherein this reception data-signal has multiple pulse; And
One controller, couples this Signal reception interface, and the pulse duration according to the described multiple pulse detected on this reception data-signal obtains multiple data,
Wherein, this controller setting one first preset range and one second preset range, this controller also judges in a detection time interval, respectively the pulse duration of this pulse is when this first preset range, this controller judges that respectively these data of corresponding respectively this pulse equal one first logic level, when this controller judges the pulse duration of respectively this pulse in this of interval between this second preset range detection time, this controller judges that respectively these data of corresponding respectively this pulse equal one second logic level, this first preset range and this second preset range non-overlapping.
2. single-wire signal transmitting device as claimed in claim 1, wherein said multiple pulse comprises at least one positive pulse and at least one negative pulse.
3. single-wire signal transmitting device as claimed in claim 1, wherein respectively this pulse between two state switching points that this reception data-signal is adjacent.
4. single-wire signal transmitting device as claimed in claim 1, wherein this controller detects the pulse duration of described multiple pulse according to a clock signal.
5. single-wire signal transmitting device as claimed in claim 4, wherein this first preset range has one first median, and this controller adjusts the frequency of this clock signal according to the pulse duration of described multiple pulse and the relation of this first median.
6. single-wire signal transmitting device as claimed in claim 4, wherein this second preset range has one second median, and this controller adjusts the frequency of this clock signal according to the pulse duration of described multiple pulse and the relation of this second median.
7. single-wire signal transmitting device as claimed in claim 1, wherein also comprises:
One signal transmission interface, couples this controller and this transmission line,
Wherein, this controller receives one and sends data, and produces a transmission data-signal according to these transmission data, and this signal transmission interface receives this transmission data-signal and sends out this transmission data-signal by this transmission line.
8. a single-wire signal transmission method, comprising:
Set one first preset range and one second preset range;
Receive one on a transmission line and receive data-signal, wherein this reception data-signal has multiple pulse;
When the pulse duration of respectively this pulse in a detection time interval is between this first preset range, judge that respectively these data of corresponding respectively this pulse equal one first logic level; And
When the pulse duration of respectively this pulse in this interval between this second preset range detection time, judge that respectively these data of corresponding respectively this pulse equal one second logic level, this first preset range and this second preset range non-overlapping.
9. single-wire signal transmission method as claimed in claim 8, wherein said multiple pulse comprises at least one positive pulse and at least one negative pulse.
10. single-wire signal transmission method as claimed in claim 8, wherein respectively this pulse between two liang of state switching points that this reception data-signal is adjacent.
11. single-wire signal transmission methods as claimed in claim 8, also comprise:
The pulse duration of described multiple pulse is detected according to a clock signal.
12. single-wire signal transmission methods as claimed in claim 11, wherein this first preset range has one first median, and this single-wire signal transmission method also comprises:
The frequency of this clock signal is adjusted according to the pulse duration of described multiple pulse and the relation of this first median.
13. single-wire signal transmission methods as claimed in claim 11, wherein this second preset range has one second median, and this single-wire signal transmission method also comprises:
The frequency of this clock signal is adjusted according to the pulse duration of described multiple pulse and the relation of this second median.
14. single-wire signal transmission methods as claimed in claim 8, also comprise:
Receive one and send data; And
Produce one according to these transmission data and send data-signal, and send out this transmission data-signal by this transmission line.
CN201310351403.6A 2013-08-02 2013-08-13 Single-wire signal transmission device and transmission method Pending CN104348587A (en)

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TW102127839A TWI488047B (en) 2013-08-02 2013-08-02 One wire signal transmission apparatus and method
TW102127839 2013-08-02

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9612609B2 (en) 2014-11-18 2017-04-04 Atmel Corporation Single wire system clock signal generation
CN109547120A (en) * 2018-12-29 2019-03-29 杰华特微电子(杭州)有限公司 Method for transmitting signals, transmission control circuit and the Switching Power Supply using it
CN113452934A (en) * 2020-03-26 2021-09-28 瑞昱半导体股份有限公司 Image playing system and image data transmission device and method with synchronous data transmission mechanism

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050185720A1 (en) * 2004-02-24 2005-08-25 Kwok Chung Y. Pseudo-synchronous one wire bidirectional bus interface
CN101901022A (en) * 2010-07-23 2010-12-01 中颖电子有限公司 Clock precision adjustment module, method and universal serial bus equipment using same
CN102236363A (en) * 2010-04-28 2011-11-09 上海华虹集成电路有限责任公司 Full-speed USB (Universal Serial Bus) equipment
CN102279834A (en) * 2011-06-10 2011-12-14 深圳市骏普科技开发有限公司 Serial communication method
CN102346499A (en) * 2010-07-23 2012-02-08 创惟科技股份有限公司 Impulse frequency correction system of serial bus clock and method thereof
TW201229986A (en) * 2011-01-03 2012-07-16 Himax Tech Ltd Display device and timing control module thereof
CN102594741A (en) * 2011-01-06 2012-07-18 三美电机株式会社 Communication circuit and method of adjusting sampling clock signal

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100525096B1 (en) * 2003-04-23 2005-11-01 주식회사 하이닉스반도체 DLL circuit
US7957923B2 (en) * 2007-07-16 2011-06-07 Himax Technologies Limited Device for jitter measurement and method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050185720A1 (en) * 2004-02-24 2005-08-25 Kwok Chung Y. Pseudo-synchronous one wire bidirectional bus interface
CN102236363A (en) * 2010-04-28 2011-11-09 上海华虹集成电路有限责任公司 Full-speed USB (Universal Serial Bus) equipment
CN101901022A (en) * 2010-07-23 2010-12-01 中颖电子有限公司 Clock precision adjustment module, method and universal serial bus equipment using same
CN102346499A (en) * 2010-07-23 2012-02-08 创惟科技股份有限公司 Impulse frequency correction system of serial bus clock and method thereof
TW201229986A (en) * 2011-01-03 2012-07-16 Himax Tech Ltd Display device and timing control module thereof
CN102594741A (en) * 2011-01-06 2012-07-18 三美电机株式会社 Communication circuit and method of adjusting sampling clock signal
CN102279834A (en) * 2011-06-10 2011-12-14 深圳市骏普科技开发有限公司 Serial communication method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9612609B2 (en) 2014-11-18 2017-04-04 Atmel Corporation Single wire system clock signal generation
US9985778B2 (en) 2014-11-18 2018-05-29 Atmel Corporation Single wire system clock signal generation
CN109547120A (en) * 2018-12-29 2019-03-29 杰华特微电子(杭州)有限公司 Method for transmitting signals, transmission control circuit and the Switching Power Supply using it
CN113452934A (en) * 2020-03-26 2021-09-28 瑞昱半导体股份有限公司 Image playing system and image data transmission device and method with synchronous data transmission mechanism
CN113452934B (en) * 2020-03-26 2024-02-13 瑞昱半导体股份有限公司 Image playing system and image data transmission device and method with synchronous data transmission mechanism

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Application publication date: 20150211