CN104363005B - A kind of radioprotective d type flip flop circuit based on three mutual latch units - Google Patents
A kind of radioprotective d type flip flop circuit based on three mutual latch units Download PDFInfo
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- CN104363005B CN104363005B CN201410552986.3A CN201410552986A CN104363005B CN 104363005 B CN104363005 B CN 104363005B CN 201410552986 A CN201410552986 A CN 201410552986A CN 104363005 B CN104363005 B CN 104363005B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
Abstract
The invention discloses a kind of radioprotective d type flip flop circuit based on three mutual latch units, this radioprotective d type flip flop circuit by clock signal generating circuit, D input filter circuit, C cell circuit and voting circuit, main mutual latch cicuit and forms from mutual latch cicuit；Described C cell circuit includes the first C cell circuit, the second C cell circuit and the 3rd C cell circuit；Outside clock signal CK through clock signal generating circuit generate clock signal and external data signal D through D input filter circuit generate data signal through main mutual latch cicuit, from mutual latch cicuit and C cell circuit after, the data signal of output exports output signal Q of whole trigger through voting circuit.Technical scheme uses three mutual latch cicuit reinforcement techniques, and the output of whole d type flip flop circuit is reliable and stable to be caused circuit to can guarantee that when overturning at d type flip flop circuit by interference such as radiation, and the capability of resistance to radiation of d type flip flop circuit is greatly improved.
Description
Technical field
The present invention relates to the design of radiation-hardened ic, be specifically related to a kind of radioprotective D based on three mutual latch units and touch
Send out device circuit.
Background technology
Along with the progress of integrated circuit fabrication process, device size reduce the lifting with operating rate, radiation is to circuit
Impact also become increasingly severe.Radiate the main impact on digital circuit and be presented as single particle effect and total dose effect,
Along with Deep Submicron MOSFETs becomes main flow, when the process node of especially MOS circuit reaches below 65nm, single particle effect
Have become as and affect the topmost radiation effect of MOS device.Single particle effect is broadly divided into single-ion transient state and single-particle inversion.
Under radiation environment, MOS integrated circuit is by the charged particle bombardment of high energy, the particularly electricity in space equipment
Road, is easily subject to radiation, and under the bombardment of charged particle, equipment easily damages.When charged particle bombardment to the MOS of cut-off originally
During pipe drain region, owing to the energy of high energy charged particles transmits, the carrier that can move freely in a large number can be produced in the short time, i.e.
Hole and electronics, so that the metal-oxide-semiconductor conducting of cut-off originally, thus change the output level of device.Owing to high energy particle produces
Carrier passage in time can be quickly compound or release and return to the carrier concentration state before bombardment, therefore hit
Metal-oxide-semiconductor has one and is reflected in circuit output from by the end of being conducting to the process ended again, will produce a positive pulse or
The waveform of negative pulse.The pulse effects of this transient state is referred to as single-ion transient state.For combinational logic circuit, single-ion transient state
Effect can affect the output of circuit.And in sequence circuit, the positive pulse or the negative pulse that produce when single-ion transient state are triggered device
Or other storage circuit receive, or the storage part of circuit is directly hit by high energy particle and is produced upset, due to circuit
Memory function so that this upset cannot recover, so that the output of whole sequential logical circuit produces mistake, this effect claims
Make single-particle inversion.Either single-ion transient state effect or Single event upset effecf all can affect the normal work of circuit, because of
This is necessary that the MOS digital integrated electronic circuit to working under radiation environment is reinforced.Scheme of Strengthening master to sequence circuit at present
Including system-level reinforcing, circuit-level is reinforced and domain level is reinforced, or uses the techniques such as SOI to reinforce.And for sequential
Trigger in circuit carries out circuit-level reinforcing, currently mainly uses triplication redundancy and double interlocking to deposit structure technology and reinforce.
The cardinal principle of triplication redundancy reinforcement technique is that trigger is replicated three parts, by the output warp of three flip-flop circuits
Cross voting circuit and form a final output, select the function of two owing to voting circuit has three.Therefore, even if there being a road trigger
Produce upset, also do not interfere with the output of whole circuit, and the principle that double interlocking deposits reinforcement technique is to add one in trigger
Individual double interlocking deposits structure, has a pair sensitive nodes in double interlocking deposits structure, the overall output of trigger depend on this pair quick
The level of sense node.In the case of not having irradiation, the level of this pair sensitive nodes is consistent.And when receiving irradiation,
When a node in a pair sensitive nodes is produced upset by the effect of high energy particle, the output of circuit is able to maintain that constant,
Simultaneously under the effect of another sensitive nodes, the node of upset can be promptly restored to normal condition, so that whole circuit is protected
Keep steady fixed, the most irradiated impact.But it is that reliability is the highest that triplication redundancy and double interlocking deposit the major defect of circuit reinforcement technique,
Assume that the upset probability not using the trigger of circuit-level reinforcement technique is, do not considering sensitive nodes dependency and node
On the premise of injecting electric charge tolerable differences, after using triplication redundancy to reinforce, the upset probability of trigger output drops to, and the trigger upset probability using double interlocking to deposit reinforcement technique is.Therefore, time in order to ensure circuit long
Between normally work, typically can use the double interlocking of circuit-level deposit reinforce and system-level triplication redundancy reinforce combine way, and
Adopt the rising at double that will necessarily bring circuit area and power consumption in this way, the timing performance of circuit the most also can be made to dislike
Changing, operating frequency declines.
Summary of the invention
It is an object of the invention to provide a kind of radioprotective d type flip flop circuit based on three mutual latch units, this radioprotective D
Flip-flop circuit overcomes the deficiencies in the prior art, uses three mutual latch cicuit reinforcement techniques, is radiated at d type flip flop circuit
Cause circuit to can guarantee that when overturning the output of whole d type flip flop circuit is reliable and stable Deng interference, and d type flip flop circuit is greatly improved
Radioprotective and capacity of resisting disturbance.
For reaching above-mentioned purpose, the technical solution adopted for the present invention to solve the technical problems is: a kind of based on three interlockings
The radioprotective d type flip flop circuit of memory cell, including clock signal generating circuit, D input filter circuit, C cell circuit and voting
Circuit, is characterized in that: this radioprotective d type flip flop circuit also includes main mutual latch cicuit and from mutual latch cicuit；Described C cell electricity
Road includes the first C cell circuit, the second C cell circuit and the 3rd C cell circuit；Outside clock signal CK is produced through clock signal
Raw circuit evolving three road in-phase clock signal bclk1, bclk2 and bclk3 and three road inverting clock signal nclk1, nclk2 and
nclk3；External data signal D generates three circuit-switched data signal D1, D2 and D3 through D input filter circuit；Three road in-phase clock signals
Bclk1, bclk2 and bclk3, three road inverting clock signal nclk1, nclk2 and nclk3 and three circuit-switched data signal D1, D2 and
D3 is input to main mutual latch cicuit, exports three circuit-switched data signal M1, M2 and M3, three road in-phase clock letters after main mutual latch cicuit
Number bclk1, bclk2 and bclk3, three road inverting clock signal nclk1, nclk2 and nclk3 and main mutual latch cicuit output
Three circuit-switched data signal M1, M2 and M3 are all input to from mutual latch cicuit, then produce three ways after from mutual latch cicuit and it is believed that
Number S1, S2 and S3, two paths of data signal S1 and S2 exported from mutual latch cicuit is input to the first C cell circuit and produces data letter
Number Q3, two paths of data signal S2 and S3 exported from mutual latch cicuit are input to the second C cell circuit and produce data signal Q1, from
Two paths of data signal S1 and S3 of latch cicuit output is input to the 3rd C cell circuit and produces data signal Q2, data signal mutually
S1, S2 and S3 are input to voting circuit and export output signal Q of whole trigger.
Preferentially, the mutual latch cicuit of described master be by 9 PMOS PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8,
PM9 and 9 NMOS tube NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9 and three transmission gate TM1, TM2, TM3 groups
Become；
The inverting clock signal nclk1's that the same phase control end of described transmission gate TM1 generates with clock signal generating circuit
Signal output part connects, the in-phase clock signal bclk1 that the inverted control terminals of transmission gate TM1 generates with clock signal generating circuit
Signal output part connect, the inversion clock letter that the same phase control end of described transmission gate TM2 and clock signal generating circuit generate
The signal output part of number nclk2 connects, the in-phase clock that the inverted control terminals of transmission gate TM2 generates with clock signal generating circuit
The signal output part of signal bclk2 connects, and the same phase control end of described transmission gate TM3 is anti-with what clock signal generating circuit generated
The signal output part of clock signal nclk3 connects, and the inverted control terminals of transmission gate TM3 generates with clock signal generating circuit
The signal output part of in-phase clock signal bclk3 connects；The left side bidirectional data port of described transmission gate TM1 and D input filter
The signal output part of data signal D1 of circuit connects, the left side bidirectional data port of transmission gate TM2 and D input filter circuit
The signal output part of data signal D2 connects, the left side bidirectional data port of transmission gate TM3 respectively with the number of D input filter circuit
The signal output part of the number of it is believed that D3 connects, the right side bidirectional data port of transmission gate TM1 respectively with drain electrode, the grid of PM3 of PM2
Drain electrode with NM1, the grid of NM9 connect, the right side bidirectional data port of transmission gate TM2 respectively with drain electrode, the grid of PM6 of PM5
Pole and the drain electrode of NM4, the grid of NM3 connect, the right side bidirectional data port of transmission gate TM3 respectively with the drain electrode of PM8, PM9
The grid of grid and the drain electrode of NM7, NM6 connects；
The grid level of described PM1 is connected with the drain of PM9, the drain electrode of NM9, the grid of NM8 respectively, the external electricity of source electrode of PM1
Source, drain electrode connects with the source electrode of PM2；The inverting clock signal nclk1 that the grid of described PM2 generates with clock signal generating circuit
Signal output part connect, the drain electrode of PM2 respectively with the drain electrode of NM1, the grid of PM3, NM9 grid on connect；The source of described PM3
Pole external power supply, the drain electrode of PM3 is connected with the grid of NM2, the drain electrode of NM3, the grid of PM4 respectively, the drain electrode output data of PM3
Signal M1；The source electrode external power supply of described PM4, the drain electrode of PM4 is connected with the source electrode of PM5；The grid of described PM5 and clock signal
The signal output part of the inverting clock signal nclk2 producing circuit evolving connects, the drain electrode of PM5 respectively with drain electrode, the PM6 of NM4
Grid, NM3 grid connect；The source electrode external power supply of described PM6, the drain electrode of PM6 respectively with drain electrode, the grid of PM7 of NM6
Pole, the grid of NM5, the drain electrode outputting data signals M2 of PM6；The source electrode external power supply of described PM7, the drain electrode of PM7 and the source of PM8
The most connected；The signal output part of the inverting clock signal nclk3 that the grid of described PM8 generates with clock signal generating circuit is even
Connecing, the drain electrode of PM8 grid with the drain electrode of NM7, the grid of PM9 and NM6 respectively is connected；The source electrode external power supply of described PM9,
The drain electrode of PM9 is connected with the drain electrode of NM9, the grid of NM8 respectively, the drain electrode outputting data signals M3 of PM9；
The signal output part of the in-phase clock signal bclk1 that the grid of described NM1 generates with clock signal generating circuit is even
Connecing, the source electrode of NM1 is connected with the drain electrode of NM2；The in-phase clock signal that the grid of described NM4 generates with clock signal generating circuit
The signal output part of bclk2 connects, and the source electrode of NM4 is connected with the drain electrode of NM5；The grid of described NM7 produces electricity with clock signal
The signal output part of the in-phase clock signal bclk3 that road generates connects, and the source electrode of NM7 is connected with the drain electrode of even NM8；Described NM2,
The source grounding of NM3, NM5, NM6, NM8, NM9.
Preferentially, described from mutual latch cicuit be by 9 PMOS PM10, PM11, PM12, PM13, PM14, PM15,
PM16, PM17, PM18 and 9 NMOS tube NM10, NM11, NM12, NM13, NM14, NM15, NM16, NM17, NM18 and three
Individual transmission gate TS1, TS2, TS3 form；
The in-phase clock signal bclk1's that the same phase control end of described transmission gate TS1 generates with clock signal generating circuit
Signal output part connects, the inverting clock signal nclk1 that the inverted control terminals of transmission gate TS1 generates with clock signal generating circuit
Signal output part connect, the in-phase clock letter that the same phase control end of described transmission gate TS2 and clock signal generating circuit generate
The signal output part of number bclk2 connects, the inversion clock that the inverted control terminals of transmission gate TS2 generates with clock signal generating circuit
The signal output part of signal nclk2 connects, and the same phase control end of described transmission gate TS3 is same with what clock signal generating circuit generated
The signal output part of clock signal bclk3 connects, and the inverted control terminals of transmission gate TS3 generates with clock signal generating circuit
The signal output part of inverting clock signal and nclk3 connects, and the left side bidirectional data port of described transmission gate TS1 latches mutually with main
The signal output part of data signal M1 of circuit connects, the left side bidirectional data port of transmission gate TS2 and main mutual latch cicuit
The signal output part of data signal M2 connects, the data letter of the left side bidirectional data port of transmission gate TS3 and main mutual latch cicuit
The signal output part of number M3 connects, the right side bidirectional data port of transmission gate TS1 respectively with the drain electrode of PM11, the grid of PM12 and
The drain electrode of NM10, the grid of NM18 connect, the right side bidirectional data port of transmission gate TS2 respectively with the drain electrode of PM14, PM15
Grid and the drain electrode of NM13, the grid of NM12 connect, the right side bidirectional data port of transmission gate TS3 respectively with the drain electrode of PM17,
The grid of the grid of PM18 and the drain electrode of NM16, NM15 connects；
The grid level of described PM10 is connected, outside the source electrode of PM10 with the drain of PM18, the drain electrode of NM18, the grid of NM17 respectively
Connecing power supply, drain electrode connects with the source electrode of PM11；The in-phase clock letter that the grid of described PM11 and clock signal generating circuit generate
The signal output part of number bclk1 connects, the drain electrode of PM11 respectively with the drain electrode of NM10, the grid of PM12, NM18 grid on connect；
The source electrode external power supply of described PM12, the drain electrode of PM12 is connected with the grid of NM11, the drain electrode of NM12, the grid of PM13 respectively,
The drain electrode outputting data signals S1 of PM12；The source electrode external power supply of described PM13, the drain electrode of PM13 is connected with the source electrode of PM14；Institute
The signal output part stating the in-phase clock signal bclk2 that the grid of PM14 generates with clock signal generating circuit is connected, PM14's
Drain electrode is connected with the drain electrode of NM13, the grid of PM15, the grid of NM12 respectively；The source electrode external power supply of described PM15, PM15's
Drain electrode respectively with the drain electrode of NM15, the grid of PM16, the grid of NM14, the drain electrode outputting data signals S2 of PM15；Described PM16
Source electrode external power supply, the drain electrode of PM16 is connected with the source electrode of PM17；The grid of described PM17 is raw with clock signal generating circuit
Become in-phase clock signal bclk3 signal output part connect, the drain electrode of PM17 respectively with the drain electrode of NM16, the grid of PM18 and
The grid of NM15 connects；The source electrode external power supply of described PM18, the drain electrode of PM18 connects with the drain electrode of NM18, the grid of NM17 respectively
Connect, the drain electrode outputting data signals S3 of PM18；
The signal output part of the inverting clock signal nclk1 that the grid of described NM10 generates with clock signal generating circuit is even
Connecing, the source electrode of NM10 is connected with the drain electrode of NM11；The inversion clock that the grid of described NM13 generates with clock signal generating circuit
The signal output part of signal nclk2 connects, and the source electrode of NM13 is connected with the drain electrode of NM14；The grid of described NM16 and clock signal
The signal output part of the inverting clock signal nclk3 producing circuit evolving connects, and the source electrode of NM16 is connected with the drain electrode of even NM17；
The source grounding of described NM11, NM12, NM14, NM15, NM17, NM18.
In technique scheme, this radioprotective d type flip flop circuit have employed three and latches circuit engineering mutually, at circuit structure
In be provided with three sensitive nodes, the level of these three sensitive nodes is depended in the overall output of trigger, in not radiation etc.
In the case of interference, the level of these three sensitive nodes is consistent.And when receiving the disturbed conditions such as radiation, even if three are quick
When two nodes in sense node are produced upset by the effect of high energy particle, the output of circuit can remain unchanged, and exists simultaneously
Under the effect of another sensitive nodes, the node of upset can be promptly restored to normal condition, so that whole circuit keeps stable,
The impact of the interference factors such as not raying, so that the upset probability of the output signal of whole d type flip flop circuit declines to a great extent, with
Time this d type flip flop circuit this chip area compared with the d type flip flop circuit depositing circuit or triplication redundancy technology based on double interlocking
Little with change of power consumption.Technical scheme overcomes the deficiencies in the prior art, uses three mutual latch cicuit reinforcement techniques,
Being caused circuit to can guarantee that when overturning by interference such as radiation, the output of whole d type flip flop circuit is reliable and stable, and D is greatly improved
The radioprotective of flip-flop circuit and capacity of resisting disturbance.
Accompanying drawing explanation
Fig. 1 is the theory structure block diagram of a kind of radioprotective d type flip flop circuit based on three mutual latch units of the present invention；
Fig. 2 is clock signal generating circuit in a kind of radioprotective d type flip flop circuit based on three mutual latch units of the present invention
Signal input and the structural representation of output relation；
Fig. 3 is the letter of D input filter circuit in a kind of radioprotective d type flip flop circuit based on three mutual latch units of the present invention
Number input and the structural representation of output relation；
Fig. 4 is that in a kind of radioprotective d type flip flop circuit based on three mutual latch units of the present invention, the signal of voting circuit is defeated
Enter the structural representation with output relation；
Fig. 5 is the electricity of main mutual latch cicuit in a kind of radioprotective d type flip flop circuit based on three mutual latch units of the present invention
Road schematic diagram；
Fig. 6 is signal input and the structural representation of signal output relation of main mutual latch cicuit in Fig. 5；
Fig. 7 is from the electricity of mutual latch cicuit in a kind of radioprotective d type flip flop circuit based on three mutual latch units of the present invention
Road schematic diagram；
Fig. 8 is to input from the signal of mutual latch cicuit and the structural representation of signal output relation in Fig. 7.
Detailed description of the invention
Radioprotective d type flip flop circuit of based on three mutual latch units a kind of to the present invention with embodiment are made below in conjunction with the accompanying drawings
Further describe.The accompanying drawing constituting the application is used for providing a further understanding of the present invention, and the present invention's is schematic real
Execute example and illustrate for explaining the present invention, being not intended that inappropriate limitation of the present invention.
From Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, the one of the present embodiment is based on three mutual latch units
The radioprotective d type flip flop circuit of (Triple Interlocked storage Cell DICE) is to be produced by clock signal
Circuit (Clock generator), D input filter circuit (D inputfilter), C cell circuit (C element) and voting
Circuit (voter), main mutual latch cicuit (Master DICE) and from mutual latch cicuit (Slave DICE).Described C cell circuit
It is made up of the first C cell circuit, the second C cell circuit and three identical circuit of the 3rd C cell circuit；Outside clock letter
Number CK generates three road in-phase clock signal bclk1, bclk2 and bclk3 and three road inversion clocks through clock signal generating circuit
Signal nclk1, nclk2 and nclk3；External data signal D generates three circuit-switched data signal D1, D2 and D3 through D input filter circuit；
Three road in-phase clock signal bclk1, bclk2 and bclk3, three road inverting clock signal nclk1, nclk2 and nclk3 and three tunnels
Data signal D1, D2 and D3 are input to main mutual latch cicuit, export after main mutual latch cicuit three circuit-switched data signal M1, M2 and
M3, three road in-phase clock signal bclk1, bclk2 and bclk3, three road inverting clock signal nclk1, nclk2 and nclk3 and
Three circuit-switched data signal M1, M2 and M3 of main mutual latch cicuit output are all input to from mutual latch cicuit, then through from latching electricity mutually
Producing three circuit-switched data signal S1, S2 and S3 behind road, two paths of data signal S1 and S2 exported from mutual latch cicuit is input to a C
Element circuit produces data signal Q3, and two paths of data signal S2 and S3 exported from mutual latch cicuit is input to the second C cell electricity
Road produces data signal Q1, and two paths of data signal S1 and S3 exported from mutual latch cicuit is input to the 3rd C cell circuit generation
Data signal Q2, data signal S1, S2 and S3 are input to voting circuit and export output signal Q of whole trigger.
In the present embodiment, such as Fig. 2, clock signal generating circuit (clock generator) is responsible for time outside
Clock signal CK generates three road in-phase clock signal bclk1, bclk2 and bclk3 by chain of inverters and three road inversion clocks are believed
Number nclk1, nclk2 and nclk3, three road in-phase clock signals and three road inverting clock signal are due to through different chain of inverters
Having different time delays, its main purpose is that interference (SET) pulse in order to make the input of the clock signal CK end of outside is in difference
Moment arrives three mutual latch units circuit (DICE) parts, by main mutual latch cicuit and the machine that latches mutually from mutual latch cicuit
System, makes circuit not affected by the interference (SET) on CK signal, and this circuit can also increase the driving force of clock signal simultaneously.
As Fig. 3, D input filter circuit (D input filter) is responsible for the D signal of input mono-by phase inverter and C
Unit generates three circuit-switched data signal D1, D2 and D3 and latches the mutual latch cicuit of main circuit (Master DICE) circuit mutually for main.Just
When the breadth length ratio of two phase inverters in circuit is set, different time delays can be obtained such that it is able to filter the interference of D input
(SET) pulse.
In C cell circuit (C element), when data signal S1 exported from mutual latch cicuit (Slave TICE) and
S2, S2 and S3, S1 and S3 are separately input to three C cell circuit, and when two signals are identical, C cell circuit is equivalent to anti-phase
Device, after three C cell circuit, difference output signal Q3, Q1, Q2, anti-phase with input signal.When from mutual latch cicuit (Slave
TICE) two paths of signals that data signal S1 exported and S2, S2 and S3, S1 are separately input to three C cell circuit with S3 is different
Time, the upper pull-up network of C cell circuit and pulldown network simultaneously switch off, and output signal relies on the electric charge of electric capacity storage, maintains output
Signal is constant.
Such as Fig. 4, in voting circuit (Voter), when C cell circuit (C element) output signal Q1, Q2 and Q3 have two
Individual or time two or more signal is high level, in voting circuit, outputting data signals Q is high level, otherwise, when in three road signals
When to have two-way or the above signal of two-way be low level, output signal Q is low level.
In the present embodiment, a kind of based on three mutual latch units the radioprotective d type flip flops of the present embodiment as seen from Figure 1
Circuit is having three output signals S1, S2 and S3 from mutual latch cicuit (Slave TICE), it is assumed that under particle effect S1 and
S2 is overturned, then according to the operation principle of C cell circuit, Q1 and Q2 keeps constant, Q3 output switching activity, and Q1, Q2 and Q3 are defeated
Entering after voting machine circuit, the output Q of whole circuit keeps constant.Therefore, even if the three of this trigger sensitive nodes are beaten
Turning over two, circuit output still keeps constant.
As shown in Figure 5, Figure 6, the mutual latch cicuit of the master of the present embodiment (Master DICE) be by 9 PMOS PM1,
PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9 and 9 NMOS tube NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8,
NM9 and three transmission gate TM1, TM2, TM3 compositions.The same phase control end of transmission gate TM1 generates with clock signal generating circuit
The signal output part of inverting clock signal nclk1 connect, the inverted control terminals of transmission gate TM1 and clock signal generating circuit are raw
The signal output part of the in-phase clock signal bclk1 become connects, and the same phase control end of described transmission gate TM2 produces with clock signal
The signal output part of the inverting clock signal nclk2 of circuit evolving connects, and the inverted control terminals of transmission gate TM2 produces with clock signal
The signal output part of the in-phase clock signal bclk2 of raw circuit evolving connects, the same phase control end of described transmission gate TM3 and clock
The signal output part of the inverting clock signal nclk3 that signal generating circuit generates connects, the inverted control terminals of transmission gate TM3 and time
The signal output part of the in-phase clock signal bclk3 that clock signal generating circuit generates connects；The left side of described transmission gate TM1 is two-way
FPDP is connected with the signal output part of data signal D1 of D input filter circuit, the left side bi-directional data end of transmission gate TM2
Mouth is connected with the signal output part of data signal D2 of D input filter circuit, and the left side bidirectional data port of transmission gate TM3 is respectively
Be connected with the signal output part of data signal D3 of D input filter circuit, the right side bidirectional data port of transmission gate TM1 respectively with
The drain electrode of PM2, the grid of PM3 and the drain electrode of NM1, the grid of NM9 connect, and the right side bidirectional data port of transmission gate TM2 is respectively
The drain electrode of drain electrode, the grid of PM6 and NM4, the grid of NM3 with PM5 are connected, and the right side bidirectional data port of transmission gate TM3 is divided
It is not connected with the grid of the drain electrode of PM8, the grid of PM9 and the drain electrode of NM7, NM6.The grid level of PMOS PM1 respectively with the leakage of PM9
Level, the drain electrode of NM9, the grid of NM8 are connected, the source electrode external power supply of PM1, and drain electrode connects with the source electrode of PM2；The grid of described PM2
The signal output part of the inverting clock signal nclk1 that pole generates with clock signal generating circuit is connected, the drain electrode of PM2 respectively with
The drain electrode of NM1, the grid of PM3, NM9 grid on connect；The source electrode external power supply of described PM3, the drain electrode of PM3 is respectively with NM2's
Grid, the drain electrode of NM3, the grid of PM4 connect, the drain electrode outputting data signals M1 of PM3；The source electrode external power supply of described PM4,
The drain electrode of PM4 is connected with the source electrode of PM5；The inverting clock signal that the grid of described PM5 generates with clock signal generating circuit
The signal output part of nclk2 connects, and the drain electrode of PM5 is connected with the drain electrode of NM4, the grid of PM6, the grid of NM3 respectively；Described
The source electrode external power supply of PM6, the drain electrode of PM6 respectively with the drain electrode of NM6, the grid of PM7, the grid of NM5, the drain electrode output of PM6
Data signal M2；The source electrode external power supply of described PM7, the drain electrode of PM7 is connected with the source electrode of PM8；The grid of described PM8 and clock
The signal output part of the inverting clock signal nclk3 that signal generating circuit generates connects, the drain electrode of PM8 respectively with the drain electrode of NM7,
The grid of PM9 and the grid of NM6 connect；The source electrode external power supply of described PM9, the drain electrode of PM9 respectively with the drain electrode of NM9, NM8
Grid connects, the drain electrode outputting data signals M3 of PM9；
In the present embodiment, the signal of the in-phase clock signal bclk1 that the grid of NM1 and clock signal generating circuit generate is defeated
Going out end to connect, the source electrode of NM1 is connected with the drain electrode of NM2；The same phase time that the grid of described NM4 generates with clock signal generating circuit
The signal output part of clock signal bclk2 connects, and the source electrode of NM4 is connected with the drain electrode of NM5；The grid of described NM7 and clock signal
The signal output part of the in-phase clock signal bclk3 producing circuit evolving connects, and the source electrode of NM7 is connected with the drain electrode of even NM8；Institute
State the source grounding of NM2, NM3, NM5, NM6, NM8, NM9.
In the present embodiment, the mutual latch cicuit of master (Master TICE) as shown in Figure 5, Figure 6.The bottom of circuit is three
Transmission gate TM1, TM2 and TM3 that group is controlled by clock signal, when clock signal CK is effective, inverting clock signal nclk1=1；
nclk2=1；Nclk3=1 and in-phase clock signal bclk1=0；bclk2=0；During bclk3=0, the three of D input filter circuit generation
Circuit-switched data signal D1, D2 and D3 will be sent in main mutual latch cicuit (Master TICE) latch, and when anti-phase
Clock signal nclk1=0；nclk2=0；Nclk3=0 and in-phase clock signal bclk1=1；bclk2=1；During bclk3=1, main latch mutually
The signal inversion latched in circuit (Master TICE) is delivered to tri-nodes of M1, M2 and M3 for from mutual latch cicuit (Slave
TICE) use.When any sensitive nodes of circuit is overturned, due to the mutual latch mechanism of circuit, main mutual latch cicuit (Master
TICE) produce M1, M2 and M3 tri-tunnel output can recover rapidly.
As shown in Figure 7, Figure 8, the present embodiment from mutual latch cicuit be by 9 PMOS PM10, PM11, PM12, PM13,
PM14, PM15, PM16, PM17, PM18 and 9 NMOS tube NM10, NM11, NM12, NM13, NM14, NM15, NM16, NM17,
NM18 and three transmission gate TS1, TS2, TS3 compositions.The same phase control end of transmission gate TS1 generates with clock signal generating circuit
The signal output part of in-phase clock signal bclk1 connect, the inverted control terminals of transmission gate TS1 and clock signal generating circuit are raw
The signal output part of the inverting clock signal nclk1 become connects, and the same phase control end of described transmission gate TS2 produces with clock signal
The signal output part of the in-phase clock signal bclk2 of circuit evolving connects, and the inverted control terminals of transmission gate TS2 produces with clock signal
The signal output part of the inverting clock signal nclk2 of raw circuit evolving connects, the same phase control end of described transmission gate TS3 and clock
The signal output part of the in-phase clock signal bclk3 that signal generating circuit generates connects, the inverted control terminals of transmission gate TS3 and time
Inverting clock signal and the signal output part of nclk3 that clock signal generating circuit generates connect, and the left side of described transmission gate TS1 is double
Signal output part to FPDP with data signal M1 of main mutual latch cicuit is connected, the left side bi-directional data of transmission gate TS2
Port is connected with the signal output part of data signal M2 of main mutual latch cicuit, the left side bidirectional data port of transmission gate TS3 and
The signal output part of data signal M3 of main mutual latch cicuit connects, the right side bidirectional data port of transmission gate TS1 respectively with
The drain electrode of PM11, the grid of PM12 and the drain electrode of NM10, the grid of NM18 connect, the right side bidirectional data port of transmission gate TS2
Grid with the drain electrode of PM14, the grid of PM15 and the drain electrode of NM13, NM12 is connected respectively, the two-way number in right side of transmission gate TS3
According to port, grid with the drain electrode of PM17, the grid of PM18 and the drain electrode of NM16, NM15 is connected respectively.The grid fraction of described PM10
Not be not connected with the drain of PM18, the drain electrode of NM18, the grid of NM17, the source electrode external power supply of PM10, drain electrode and the source electrode of PM11
Connect；The signal output part of the in-phase clock signal bclk1 that the grid of described PM11 generates with clock signal generating circuit is connected,
The drain electrode of PM11 respectively with the drain electrode of NM10, the grid of PM12, NM18 grid on connect；The source electrode external power supply of described PM12,
The drain electrode of PM12 is connected with the grid of NM11, the drain electrode of NM12, the grid of PM13 respectively, the drain electrode outputting data signals of PM12
S1；The source electrode external power supply of described PM13, the drain electrode of PM13 is connected with the source electrode of PM14；The grid of described PM14 and clock signal
The signal output part of the in-phase clock signal bclk2 producing circuit evolving connects, the drain electrode of PM14 respectively with the drain electrode of NM13,
The grid of PM15, the grid of NM12 connect；The source electrode external power supply of described PM15, the drain electrode of PM15 respectively with the drain electrode of NM15,
The grid of PM16, the grid of NM14, the drain electrode outputting data signals S2 of PM15；The source electrode external power supply of described PM16, PM16's
Drain electrode is connected with the source electrode of PM17；The in-phase clock signal bclk3 that the grid of described PM17 generates with clock signal generating circuit
Signal output part connect, the drain electrode of PM17 grid with the drain electrode of NM16, the grid of PM18 and NM15 respectively is connected；Described
The source electrode external power supply of PM18, the drain electrode of PM18 is connected with the drain electrode of NM18, the grid of NM17 respectively, the drain electrode output number of PM18
The number of it is believed that S3.In the present embodiment, the signal of the inverting clock signal nclk1 that the grid of NM10 generates with clock signal generating circuit
Outfan connects, and the source electrode of NM10 is connected with the drain electrode of NM11；The grid of described NM13 generates with clock signal generating circuit
The signal output part of inverting clock signal nclk2 connects, and the source electrode of NM13 is connected with the drain electrode of NM14；The grid of described NM16 with
The signal output part of the inverting clock signal nclk3 that clock signal generating circuit generates connects, and the source electrode of NM16 is with even NM17's
Drain electrode connects；The source grounding of described NM11, NM12, NM14, NM15, NM17, NM18.
The present embodiment from mutual latch cicuit (Master TICE).Its circuit structure Fig. 5, Fig. 6's similar with operation principle
Main mutual latch cicuit (Master TICE).Difference is as inverting clock signal nclk1=0；nclk2=0；Nclk3=0 and same phase time
Clock signal bclk1=1；bclk2=1；During bclk3=1, signal is latched, as inverting clock signal nclk1=1；nclk2=1；
Nclk3=1 and in-phase clock signal bclk1=0；bclk2=0；During bclk3=0, the inverted output of signal.Main mutual latch cicuit
(Master TICE) constitutes together with from mutual latch cicuit (Slave TICE) and has hypotactic trigger.
The above, be only embodiments of the invention, not impose any restrictions the present invention, every according to the technology of the present invention
The change of any simple modification, change and equivalent method that above example is made by essence, all still falls within the technology of the present invention
In the protection domain of scheme.
Claims (1)
1. radioprotective d type flip flop circuit based on three mutual latch units, including clock signal generating circuit, D input filter
Circuit, C cell circuit and voting circuit, is characterized in that: this radioprotective d type flip flop circuit also includes main mutual latch cicuit and from mutually
Latch cicuit；Described C cell circuit includes the first C cell circuit, the second C cell circuit and the 3rd C cell circuit；Time outside
Clock signal CK generates three road in-phase clock signal bclk1, bclk2 and bclk3 and three tunnels are anti-phase through clock signal generating circuit
Clock signal nclk1, nclk2 and nclk3；External data signal D generates three circuit-switched data signal D1, D2 through D input filter circuit
And D3；Three road in-phase clock signal bclk1, bclk2 and bclk3, three road inverting clock signal nclk1, nclk2 and nclk3 with
And three circuit-switched data signal D1, D2 and D3 be input to main mutual latch cicuit, export after main mutual latch cicuit three circuit-switched data signal M1,
M2 and M3；Three road in-phase clock signal bclk1, bclk2 and bclk3, three road inverting clock signal nclk1, nclk2 and nclk3
And three circuit-switched data signal M1, M2 and M3 of master's mutual latch cicuit output are all input to from mutual latch cicuit, then through from interlocking
Producing three circuit-switched data signal S1, S2 and S3 after depositing circuit, two paths of data signal S1 and S2 exported from mutual latch cicuit is input to
First C cell circuit produces data signal Q3, and it is mono-that two paths of data signal S2 and S3 exported from mutual latch cicuit is input to the 2nd C
Unit's circuit produces data signal Q1, and two paths of data signal S1 and S3 exported from mutual latch cicuit is input to the 3rd C cell circuit
Producing data signal Q2, data signal Q1, Q2 and Q3 are input to voting circuit and export output signal Q of whole trigger；
The mutual latch cicuit of described master is by 9 PMOS PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, PM9 and 9 NMOS
Pipe NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9 and three transmission gate TM1, TM2, TM3 compositions；
The signal of the inverting clock signal nclk1 that the same phase control end of described transmission gate TM1 generates with clock signal generating circuit
Outfan connects, the letter of the in-phase clock signal bclk1 that the inverted control terminals of transmission gate TM1 generates with clock signal generating circuit
Number outfan connects, the inverting clock signal that the same phase control end of described transmission gate TM2 generates with clock signal generating circuit
The signal output part of nclk2 connects, the in-phase clock letter that the inverted control terminals of transmission gate TM2 and clock signal generating circuit generate
The signal output part of number bclk2 connects, and the same phase control end of described transmission gate TM3 is anti-phase with what clock signal generating circuit generated
The signal output part of clock signal nclk3 connects, and the inverted control terminals of transmission gate TM3 is same with what clock signal generating circuit generated
The signal output part of clock signal bclk3 connects；The left side bidirectional data port of described transmission gate TM1 and D input filter electricity
The signal output part of data signal D1 on road connects, the left side bidirectional data port of transmission gate TM2 and the number of D input filter circuit
The signal output part of the number of it is believed that D2 connects, the left side bidirectional data port of transmission gate TM3 respectively with the data of D input filter circuit
The signal output part of signal D3 connects, the right side bidirectional data port of transmission gate TM1 respectively with the drain electrode of PM2, the grid of PM3 and
The drain electrode of NM1, the grid of NM9 connect, the right side bidirectional data port of transmission gate TM2 respectively with drain electrode, the grid of PM6 of PM5
Drain electrode with NM4, the grid of NM3 connect, the right side bidirectional data port of transmission gate TM3 respectively with drain electrode, the grid of PM9 of PM8
The grid of pole and the drain electrode of NM7, NM6 connects；
The grid level of described PM1 is connected with the drain of PM9, the drain electrode of NM9, the grid of NM8 respectively, the source electrode external power supply of PM1, leakage
Pole connects with the source electrode of PM2；The letter of the inverting clock signal nclk1 that the grid of described PM2 generates with clock signal generating circuit
Number outfan connects, the drain electrode of PM2 respectively with the drain electrode of NM1, the grid of PM3, NM9 grid on connect；Outside the source electrode of described PM3
Connecing power supply, the drain electrode of PM3 is connected with the grid of NM2, the drain electrode of NM3, the grid of PM4 respectively, the drain electrode outputting data signals of PM3
M1；The source electrode external power supply of described PM4, the drain electrode of PM4 is connected with the source electrode of PM5；The grid of described PM5 produces with clock signal
The signal output part of the inverting clock signal nclk2 of circuit evolving connects, the drain electrode of PM5 respectively with drain electrode, the grid of PM6 of NM4
Pole, the grid of NM3 connect；The source electrode external power supply of described PM6, the drain electrode of PM6 respectively with the drain electrode of NM6, the grid of PM7, NM5
Grid, the drain electrode outputting data signals M2 of PM6；The source electrode external power supply of described PM7, the drain electrode of PM7 and the source electrode phase of PM8
Even；The signal output part of the inverting clock signal nclk3 that the grid of described PM8 generates with clock signal generating circuit is connected, PM8
Drain electrode grid with the drain electrode of NM7, the grid of PM9 and NM6 respectively be connected；The source electrode external power supply of described PM9, the leakage of PM9
Pole is connected with the drain electrode of NM9, the grid of NM8 respectively, the drain electrode outputting data signals M3 of PM9；
The signal output part of the in-phase clock signal bclk1 that the grid of described NM1 generates with clock signal generating circuit is connected,
The source electrode of NM1 is connected with the drain electrode of NM2；The in-phase clock signal that the grid of described NM4 generates with clock signal generating circuit
The signal output part of bclk2 connects, and the source electrode of NM4 is connected with the drain electrode of NM5；The grid of described NM7 produces electricity with clock signal
The signal output part of the in-phase clock signal bclk3 that road generates connects, and the source electrode of NM7 is connected with the drain electrode of even NM8；Described NM2,
The source grounding of NM3, NM5, NM6, NM8, NM9；
Described from mutual latch cicuit be by 9 PMOS PM10, PM11, PM12, PM13, PM14, PM15, PM16, PM17, PM18
With 9 NMOS tube NM10, NM11, NM12, NM13, NM14, NM15, NM16, NM17, NM18 and three transmission gate TS1,
TS2, TS3 form；
The signal of the in-phase clock signal bclk1 that the same phase control end of described transmission gate TS1 generates with clock signal generating circuit
Outfan connects, the letter of the inverting clock signal nclk1 that the inverted control terminals of transmission gate TS1 generates with clock signal generating circuit
Number outfan connects, the in-phase clock signal that the same phase control end of described transmission gate TS2 generates with clock signal generating circuit
The signal output part of bclk2 connects, the inversion clock letter that the inverted control terminals of transmission gate TS2 and clock signal generating circuit generate
The signal output part of number nclk2 connects, the homophase that the same phase control end of described transmission gate TS3 generates with clock signal generating circuit
The signal output part of clock signal bclk3 connects, and the inverted control terminals of transmission gate TS3 is anti-with what clock signal generating circuit generated
The signal output part of clock signal and nclk3 connects, and the left side bidirectional data port of described transmission gate TS1 latches electricity mutually with main
The signal output part of data signal M1 on road connects, the left side bidirectional data port of transmission gate TS2 and the number of main mutual latch cicuit
The signal output part of the number of it is believed that M2 connects, the left side bidirectional data port of transmission gate TS3 and the data signal of main mutual latch cicuit
The signal output part of M3 connects, the right side bidirectional data port of transmission gate TS1 respectively with the drain electrode of PM11, the grid of PM12 and
The drain electrode of NM10, the grid of NM18 connect, the right side bidirectional data port of transmission gate TS2 respectively with the drain electrode of PM14, PM15
Grid and the drain electrode of NM13, the grid of NM12 connect, the right side bidirectional data port of transmission gate TS3 respectively with the drain electrode of PM17,
The grid of the grid of PM18 and the drain electrode of NM16, NM15 connects；
The grid level of described PM10 is connected with the drain of PM18, the drain electrode of NM18, the grid of NM17 respectively, the external electricity of source electrode of PM10
Source, drain electrode connects with the source electrode of PM11；The in-phase clock signal that the grid of described PM11 generates with clock signal generating circuit
The signal output part of bclk1 connects, the drain electrode of PM11 respectively with the drain electrode of NM10, the grid of PM12, NM18 grid on connect；Institute
Stating the source electrode external power supply of PM12, the drain electrode of PM12 is connected with the grid of NM11, the drain electrode of NM12, the grid of PM13 respectively,
The drain electrode outputting data signals S1 of PM12；The source electrode external power supply of described PM13, the drain electrode of PM13 is connected with the source electrode of PM14；Institute
The signal output part stating the in-phase clock signal bclk2 that the grid of PM14 generates with clock signal generating circuit is connected, PM14's
Drain electrode is connected with the drain electrode of NM13, the grid of PM15, the grid of NM12 respectively；The source electrode external power supply of described PM15, PM15's
Drain electrode respectively with the drain electrode of NM15, the grid of PM16, the grid of NM14, the drain electrode outputting data signals S2 of PM15；Described PM16
Source electrode external power supply, the drain electrode of PM16 is connected with the source electrode of PM17；The grid of described PM17 is raw with clock signal generating circuit
Become in-phase clock signal bclk3 signal output part connect, the drain electrode of PM17 respectively with the drain electrode of NM16, the grid of PM18 and
The grid of NM15 connects；The source electrode external power supply of described PM18, the drain electrode of PM18 connects with the drain electrode of NM18, the grid of NM17 respectively
Connect, the drain electrode outputting data signals S3 of PM18；
The signal output part of the inverting clock signal nclk1 that the grid of described NM10 generates with clock signal generating circuit is connected,
The source electrode of NM10 is connected with the drain electrode of NM11；The inverting clock signal that the grid of described NM13 generates with clock signal generating circuit
The signal output part of nclk2 connects, and the source electrode of NM13 is connected with the drain electrode of NM14；The grid of described NM16 produces with clock signal
The signal output part of the inverting clock signal nclk3 of circuit evolving connects, and the source electrode of NM16 is connected with the drain electrode of even NM17；Described
The source grounding of NM11, NM12, NM14, NM15, NM17, NM18.
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| CN105141291B (en) * | 2015-06-19 | 2018-02-09 | 北京控制工程研究所 | A kind of radioresistance flip-flop circuit structure based on single-phase bit clock |
| CN105024687B (en) * | 2015-07-17 | 2019-06-18 | 北京控制工程研究所 | A kind of radioresistance trigger circuit based on DICE and TMR |
| CN113114226B (en) * | 2021-05-26 | 2023-02-21 | 北京理工大学 | FPGA-based hybrid architecture time-to-digital conversion method |
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| US7482831B2 (en) * | 2006-05-10 | 2009-01-27 | Alcatel-Lucent Usa Inc. | Soft error tolerant flip flops |
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