CN104375551B - Band gap voltage generative circuit - Google Patents
Band gap voltage generative circuit Download PDFInfo
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- CN104375551B CN104375551B CN201410687830.6A CN201410687830A CN104375551B CN 104375551 B CN104375551 B CN 104375551B CN 201410687830 A CN201410687830 A CN 201410687830A CN 104375551 B CN104375551 B CN 104375551B
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Abstract
The present invention relates to a kind of band gap voltage generative circuit, including: biasing circuit, for providing the first bias current for the first transistor, provide the second bias current for transistor seconds；The emitter stage of the first transistor is connected at primary nodal point with biasing circuit, provides the first bias current for biasing circuit for the first transistor；Transistor seconds is connected at secondary nodal point with biasing circuit, provides the second bias current for biasing circuit for transistor seconds；Voltage sampling circuit, utilize the voltage of the first sampling capacitance C1 sampling primary nodal point, utilize the second sampling capacitance C2 sampling primary nodal point and voltage difference of secondary nodal point, obtain output voltage based on the voltage on the voltage on the first sampling capacitance C1 and the second sampling capacitance C2.The band gap voltage generative circuit that the present invention provides, by regulation dividing ratios, and can change output voltage, improve the precision of output voltage, and have less chip area, and can produce the reference voltage of relatively low temperature-compensating.
Description
Technical field
Electronic circuit field of the present invention, particularly relates to a kind of band gap voltage generative circuit.
Background technology
In the prior art, the implementation of band-gap voltage source as it is shown in figure 1, in FIG, including resistance R1, R2, R3,
PNP bipolar transistor Q1 and Q2, operational amplifier OP.Its output voltage VBG is accurate voltage, the base emitter of Q1
The base emitter voltage Vbe2 of pole tension Vbe1 and Q2 is negative temperature coefficient, and base emitter voltage Vbe2 and Q1 of Q2
The difference of base emitter voltage Vbe1 be positive temperature coefficient.Operational amplifier OP adjusts and makes node VP voltage equal to node VN
Voltage, so the voltage drop on resistance R3 is equal to Vbe2-Vbe1, and the electric current that the electric current of resistance R1 is equal to resistance R3, so resistance
Voltage drop on R1 is equal toFor positive temperature coefficient voltage, wherein R1 and R3 uses same type resistance, its
Temperature coefficient is identical, so R1/R3 does not varies with temperature.Understand output voltage VBG to be equal toLogical
Cross design suitable R1/R3 can realize positive temperature coefficient part (Vbe2-Vbe1) and Vbe2 negative temperature coefficient part compensate,
Thus realize the output voltage VBG that temperature coefficient is less.But above-mentioned analysis is ideal situation, it does not consider operational amplifier
The input imbalance of OP, in actual production, owing to operational amplifier OP internal components exists inconsistent in the course of processing
Phenomenon, cause different chip chamber, there is some difference for the positive and negative terminal input voltage of operational amplifier OP, i.e. VP node saves with VN
There is some difference for point voltage, it is assumed that VP-VN=Vos, and wherein VP is VP node voltage, and VN is VN node voltage, then Vos is permissible
For just, it is also possible to be negative.Recalculating the voltage on R3 and reduce to (Vbe2-Vbe1)-Vos, the voltage drop VR1 on R1 is equal toThe voltage of VN is equal to Vbe2-Vos, VBG=VN+VR1=Vbe2-Vos+ [(Vbe2-
Vbe1)-Vos] * R1/R3=(Vbe2-Vbe1) * R1/R3+Vbe2-(R1/R3+1) * Vos, it is seen that the error that Vos causes for-
(R1/R3+1) * Vos, Vos are different for the performance of different chips, random distribution, therefore, and the input imbalance of operational amplifier
Voltage can affect precision and the noise characteristic of output reference voltage, and therefore this Vos have impact on the precision of output voltage VBG.
Summary of the invention
Present invention aim to address that the pressure reduction Vos of positive and negative terminal input voltage of operational amplifier is to output voltage VBG's
The problem of precision impact.
Embodiments providing a kind of band gap voltage generative circuit, described band gap voltage generative circuit includes: first
Switch controlling signal, second switch control signal, biasing circuit, the first transistor, transistor seconds, voltage sampling circuit；
Described biasing circuit, for providing the first bias current for described the first transistor, carries for described transistor seconds
For the second bias current；
The emitter stage of described the first transistor is connected at primary nodal point with described biasing circuit, for described biasing circuit
The first bias current is provided for described the first transistor；
Described transistor seconds is connected at secondary nodal point with described biasing circuit, is described for described biasing circuit
Two-transistor provides the second bias current；
Described voltage sampling circuit, including the first sampling capacitance C1 and the second sampling capacitance C2,
Utilize first sampling capacitance C1 sampling primary nodal point voltage, utilize second sampling capacitance C2 sampling primary nodal point and
The voltage difference of secondary nodal point, is exported based on the voltage on the voltage on the first sampling capacitance C1 and the second sampling capacitance C2
Voltage.
Preferably, described biasing circuit includes the first current source I1 and the second current source I2, and described the first transistor is
One bipolar transistor Q1, described transistor seconds is the second bipolar transistor Q2；
The anode of described first current source I1 is connected to power supply, and the anode of described second current source I2 is connected to power supply, institute
The negative terminal of the emitter stage and the first current source I1 of stating the first bipolar transistor Q1 is connected, the collection of described first bipolar transistor Q1
Electrode be connected with base stage after ground connection, the emitter stage of described second bipolar transistor Q2 and the negative terminal of the second current source I2 are connected
Connect, ground connection after the colelctor electrode of described second bipolar transistor Q2 and base stage connection.
Preferably, described voltage sampling circuit includes: the first switch K1, second switch K2, the 3rd switchs K3, the 4th switch
K4, the 5th switch K5, the first resistance R1, the second resistance R2, the first sampling capacitance C1, the second sampling capacitance C2, the 3rd sampling electricity
Hold C3；
Described first switch K1, second switch K2, the control end of the 3rd switch K3 and the first switch controlling signal are connected,
Described 4th switch K4, the control end of the 5th switch K5 are connected with second switch control signal, described first resistance R1 and the
Two resistance R2 series connection after be connected to the base stage of described first bipolar transistor Q1, colelctor electrode, one end of the first sampling capacitance C1 and
Between primary nodal point, one end of described first switch K1 is connected between described first resistance R1 and the second resistance R2, and described the
The other end of one switch K1 is connected to the other end of described first sampling capacitance C1, one end of described 3rd switch K3 and first segment
Point is connected, and the described other end of the 3rd switch K3 and one end of the second sampling capacitance C2 are connected, described second sampling capacitance
The other end of C2 is connected with one end of second switch K2, and the other end of described second switch K2 is connected with secondary nodal point, institute
The one end stating the 4th switch K4 is connected between described first switch K1 and the first sampling capacitance C1, and described 4th switch K4's is another
One end is connected between second switch K2 and the 3rd switch K3, and one end of described 5th switch K5 is connected to the 3rd switch K3 and the
Between two sampling capacitance C2, the described other end of the 5th switch K5 and one end of the 3rd sampling capacitance C3 are connected, and the described 3rd
The other end and the base stage of the second bipolar transistor Q2, the colelctor electrode of sampling capacitance C3 are connected；
When described first switch controlling signal is the first level, and described second switch control signal is second electrical level, institute
Stating the first switch K1, second switch K2, the 3rd switch K3 conducting, described 4th switch K4, the 5th switch K5 end, and described first
Node voltage V1 is sampled to the first sampling capacitance by the branch pressure voltage VA after described first resistance R1 and the second resistance R2 dividing potential drop
On C1, the voltage difference of described primary nodal point voltage V1 and secondary nodal point voltage V2 is sampled on the second sampling capacitance C2, works as institute
Stating the first switch controlling signal is second electrical level, when described second switch control signal is the first level, described first switch K1,
Second switch K2, the 3rd switch K3 cut-off, described 4th switch K4, the 5th switch K5 conducting, on described first sampling capacitance C1
Branch pressure voltage VA and the second sampling capacitance C2 on voltage difference be sampled on the 3rd sampling capacitance C3, obtain output voltage.
Preferably, described voltage sampling circuit includes: the 3rd resistance R3, the 4th resistance R4；
Described 3rd resistance R3 and the 4th resistance R4 series connection, one end of described 3rd resistance R3 is connected with secondary nodal point,
One end of described 4th resistance R4 is connected with the base stage of the second bipolar transistor Q2, colelctor electrode, the 3rd sampling capacitance C3.
Preferably, described voltage sampling circuit includes: the first switch K1, second switch K2, the 3rd switchs K3, the 4th switch
K4, the 5th switch K5, the 6th switch K6, the 7th switch K7, the 8th switch K8, the first resistance R1, the second resistance R2, first sampling
Electric capacity C1, the second sampling capacitance C2, the 3rd sampling capacitance C3, the 4th sampling capacitance C4；
Described first switch K1, second switch K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 control end and
First switch controlling signal is connected, described 4th switch K4, the 7th switch K7, the control end of the 8th switch K8 and second switch
Control signal is connected, and is connected to the base of described first bipolar transistor Q1 after described first resistance R1 and the second resistance R2 series connection
Pole, colelctor electrode, the first sampling capacitance C1 one end and primary nodal point between, one end of described first switch K1 is connected to described the
Between one resistance R1 and the second resistance R2, the other end of described first switch K1 is connected to another of described first sampling capacitance C1
End, one end of described 3rd switch K3 is connected with primary nodal point, the other end of described 3rd switch K3 and the second sampling capacitance
One end of C2 is connected, and the described other end of the second sampling capacitance C2 is connected with one end of second switch K2, and described second opens
The other end closing K2 is connected with secondary nodal point, and one end of described 4th switch K4 is connected to described first switch K1 and first and adopts
Between sample electric capacity C1, the other end of described 4th switch K4 is connected between second switch K2 and the 3rd switch K3, and the described 5th
One end of switch K5 is connected with the negative terminal of primary nodal point, the first current source I1, the other end and the 8th of described 5th switch K5
Switch one end of K8, one end of the 3rd sampling capacitance C3 are connected, the other end of described 3rd sampling capacitance C3 and the 6th switch
One end of K6, one end of the 7th switch K7 are connected, the other end of described 6th switch K6 and the negative terminal phase of the second current source I2
Connecting, the other end of described 7th switch K7 is connected between the second sampling capacitance C2 and the 3rd switch K3, described 8th switch
The other end be connected to one end of the 4th sampling capacitance C4, the other end of described 4th sampling capacitance C4 and the second bipolar transistor
The base stage of pipe Q2, colelctor electrode are connected；
When described first switch controlling signal is the first level, and described second switch control signal is second electrical level, institute
State the first switch K1, second switch K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 conducting, described 4th switch K4,
7th switch K7, the 8th switch K8 cut-off, described primary nodal point voltage V1 is by described first resistance R1 and the second resistance R2 dividing potential drop
After branch pressure voltage VA be sampled on the first sampling capacitance C1, described second sampling capacitance C2 and the 3rd sampling capacitance C3 is also
Connection, the voltage difference of described primary nodal point voltage V1 and secondary nodal point voltage V2 be sampled the second sampling capacitance C2, and described
The voltage difference of primary nodal point voltage V1 and secondary nodal point voltage V2 is sampled on the 3rd sampling capacitance C3, when described first switchs
Control signal is second electrical level, when described second switch control signal is the first level, and described first switch K1, second switch
K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 cut-off, described 4th switch K4, the 7th switch K7, the 8th switch K8
Conducting, the branch pressure voltage VA on described first sampling capacitance C1, the voltage difference on the second sampling capacitance C2 and the 3rd sampling capacitance
Voltage difference on C3 is sampled on the 4th sampling capacitance C4, obtains output voltage.
Preferably, described voltage sampling circuit includes: the first switch K1, second switch K2, the 3rd switchs K3, the 4th switch
K4, the 5th switch K5, the first resistance R1, the second resistance R2, the first sampling capacitance C1, the second sampling capacitance C2, the 3rd sampling electricity
Hold C3, the first sampling capacitance C4；
Described first switch K1, second switch K2, the control end of the 3rd switch K3 and the first switch controlling signal are connected,
Described 4th switch K4, the control end of the 5th switch K5 are connected with second switch control signal, described first resistance R1 and the
Two resistance R2 series connection after be connected to the base stage of described first bipolar transistor Q1, colelctor electrode, one end of the first sampling capacitance C1 and
Between primary nodal point, one end of described first switch K1 is connected between described first resistance R1 and the second resistance R2, and described the
The other end of one switch K1 is connected to the other end of described first sampling capacitance C1, and one end the 3rd of described 3rd switch K3 is adopted
After sample electric capacity C3, the negative terminal with the first current source I 1 is connected, and the other end of described 3rd switch K3 is through the second sampling capacitance C2
One end with second switch K2 connects afterwards, and the other end of described second switch K2 is connected with secondary nodal point, described 4th switch
One end of K4 is connected between the first sampling capacitance C1 and first switch K1, and the other end of described 4th switch K4 is connected to second
Between sampling capacitance C2 and second switch K2, one end of described 5th switch K5 is connected to the 3rd switch K3 and the second sampling electricity
Holding between C2, the other end of described 5th switch K5 is connected to one end of the 4th sampling capacitance C4, described 4th sampling capacitance C4
The other end and the base stage of the second bipolar transistor Q2, colelctor electrode be connected；
When described first switch controlling signal is the first level, and described second switch control signal is second electrical level, institute
Stating the first switch K1, second switch K2, the 3rd switch K3 conducting, described 4th switch K4, the 5th switch K5 end, and described first
Node voltage V1 is sampled to the first sampling capacitance by the branch pressure voltage VA after described first resistance R1 and the second resistance R2 dividing potential drop
On C1, described second sampling capacitance C2 and described 3rd sampling capacitance series connection, described primary nodal point voltage V1 and secondary nodal point electricity
A part for the voltage difference of pressure V2 is sampled on the second sampling capacitance C2, described primary nodal point voltage V1 and secondary nodal point voltage
Another part of the voltage difference of V2 is sampled on the 3rd sampling capacitance C3, when described first switch controlling signal is the second electricity
Flat, when described second switch control signal is the first level, described first switch K1, second switch K2, the 3rd switch K3 cut-off,
Described 4th switch K4, the 5th switch K5 conducting, the branch pressure voltage VA on described first sampling capacitance C1, the second sampling capacitance C2
On a part described in voltage difference described in another part on voltage difference and the 3rd sampling capacitance C3 be sampled the 4th sampling electricity
Hold on C4, obtain output voltage.
Preferably, the current value of the described first current source I1 current value equal to described second current source I2.
Preferably, the current value of the described first current source I1 current value more than described second current source I2, and first pair
The emitter area of the gated transistors Q1 area more than described first bipolar transistor Q2.
Preferably, the area of the emitter area of described second bipolar transistor Q2 and described first bipolar transistor Q1 it
Than being (N2-1): 1, wherein, N is progression, and N >=3.
Preferably, downsampling factor K=(the R1+R2)/R2 during voltage of described sampling primary nodal point, wherein, R1 is first
The resistance of resistance R1, R2 is the resistance of the second resistance R2.
The band gap voltage generative circuit that the present invention provides, owing to being provided without operational amplifier, thus eliminates operational amplifier
The impact of produced input offset voltage, improves the precision of output voltage VBG, and owing to being provided without operational amplifier, nothing
The bigger loop compensation circuit of chip area need to be consumed, so having less chip area；And sub-bandgap voltage can be produced, i.e.
Produce the reference voltage of relatively low temperature-compensating；And by regulation dividing ratios, and output voltage VBG can be changed.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, required use in embodiment being described below
Accompanying drawing be briefly described, it should be apparent that, below describe in accompanying drawing be only some embodiments of the present invention, for this
From the point of view of the those of ordinary skill of field, on the premise of not paying creative work, it is also possible to obtain other according to these accompanying drawings
Accompanying drawing.
Fig. 1 is the circuit diagram of band gap voltage generative circuit in prior art；
The circuit diagram of the band gap voltage generative circuit that Fig. 2 provides for the embodiment of the present invention one；
The circuit diagram of the band gap voltage generative circuit that Fig. 3 provides for the embodiment of the present invention two；
The circuit diagram of the band gap voltage generative circuit that Fig. 4 provides for the embodiment of the present invention three；
The circuit diagram of the band gap voltage generative circuit that Fig. 5 provides for the embodiment of the present invention four.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
The a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under not making creative work premise, broadly falls into the scope of protection of the invention.
For ease of the understanding to the embodiment of the present invention, it is further explained with specific embodiment below in conjunction with accompanying drawing
Bright, embodiment is not intended that the restriction to the embodiment of the present invention.
In below example, the first switch controlling signal is CK1, and second switch control signal is CK2, the first switch control
Signal processed be CK1 and second switch control signal be CK2 be not overlap clock, only show significant level with the first decibel meter, with
Two level represent inactive level, and such as, significant level can be high level " 1 ", and inactive level can be low level " 0 ".
Embodiment one
The circuit diagram of the band gap voltage generative circuit that Fig. 2 provides for the embodiment of the present invention one, as in figure 2 it is shown, this band gap electricity
Pressure generative circuit includes: the first switch controlling signal, second switch control signal, biasing circuit 201, the first transistor 202, electricity
Pressure sample circuit 203, transistor seconds 204；
Biasing circuit 201, is connected with power supply, for providing the first bias current for the first transistor, is the second crystal
Pipe 204 provides the second bias current, so that the first transistor 202 and transistor seconds 204 are operated in the range of linearity；In fig. 2,
Eliminate power supply, and represent the output voltage of power supply with VIN；
The emitter stage of the first transistor 202 is connected at primary nodal point with biasing circuit 201, for biasing circuit 201 is
The first transistor 202 provides the first bias current；
The emitter stage of transistor seconds 204 is connected at secondary nodal point with biasing circuit 201, is second for biasing circuit
Transistor provides the second bias current；
Voltage sampling circuit 203, including the first sampling capacitance C1 and the second sampling capacitance C2,
Utilize first sampling capacitance C1 sampling primary nodal point voltage, utilize second sampling capacitance C2 sampling primary nodal point and
The voltage difference of secondary nodal point, is exported based on the voltage on the voltage on the first sampling capacitance C1 and the second sampling capacitance C2
Voltage.
Specifically, biasing circuit 201 includes that the first current source I1 and the second current source I2, the first transistor 202 are specially
First bipolar transistor Q1, transistor seconds 204 is specially the second bipolar transistor Q2；The anode of the first current source I1 is connected to
Power supply, the anode of the second current source I2 is connected to power supply, and the first bipolar transistor Q1 launches and the negative terminal of the first current source I1
Be connected, the colelctor electrode of the first bipolar transistor Q1 be connected with base stage after ground connection, the emitter stage of the second bipolar transistor Q2 and
The negative terminal of the second current source I2 is connected, ground connection after the colelctor electrode of the second bipolar transistor Q2 and base stage connection.
The negative terminal of the first current source I1 and the emitter stage of the first bipolar transistor Q1 are connected at primary nodal point, for first
Current source I1 provides the first bias current for the first bipolar transistor Q1, so that the first bipolar transistor Q1 is operated in linear model
Enclosing, now, primary nodal point voltage is V1, and the negative terminal of the second current source I2 and the emitter stage of the second bipolar transistor Q2 are at second section
Point is connected, and provides the second bias current for the second current source I2 for the second bipolar transistor Q2, so that the second bipolar transistor
Pipe Q2 is operated in the range of linearity, and now, secondary nodal point voltage is V2.
Voltage sampling circuit 203 includes: the first switch K1, second switch K2, the 3rd switchs K3, the 4th switch K4, the 5th
Switch K5, the first resistance R1, the second resistance R2, the first sampling capacitance C1, the second sampling capacitance C2, the 3rd sampling capacitance C3；
First switch K1, second switch K2, the control end of the 3rd switch K3 and the first switch controlling signal are connected, described
4th switch K4, the control end of the 5th switch K5 are connected with second switch control signal, the first resistance R1 and the second resistance R2
It is connected to after series connection between one end and the primary nodal point of the base stage of the first bipolar transistor Q1, colelctor electrode, the first sampling capacitance C1,
One end of first switch K1 is connected between described first resistance R1 and the second resistance R2, and the other end of the first switch K1 is connected to
The other end of described first sampling capacitance C1, one end of described 3rd switch K3 is connected with primary nodal point, described 3rd switch
The other end of K3 and one end of the second sampling capacitance C2 are connected, the other end of described second sampling capacitance C2 and second switch K2
One end be connected, the other end of second switch K2 is connected with secondary nodal point, described 4th switch K4 one end be connected to institute
Stating between the first switch K1 and the first sampling capacitance C1, the other end of described 4th switch K4 is connected to second switch K2 and the 3rd
Between switch K3, one end of the 5th switch K5 is connected between the 3rd switch K3 and the second sampling capacitance C2, the 5th switch K5's
One end of the other end and the 3rd sampling capacitance C3 is connected, the other end of the 3rd sampling capacitance C3 and the second bipolar transistor Q2's
Base stage, colelctor electrode are connected；
When the first switch controlling signal is the first level, and second switch control signal is second electrical level, the first switch K1,
Second switch K2, the 3rd switch K3 conducting, the 4th switch K4, the 5th switch K5 cut-off, primary nodal point voltage V1 is by the first resistance
Branch pressure voltage VA after R1 and the second resistance R2 dividing potential drop is sampled on the first sampling capacitance C1, primary nodal point voltage V1 and second
The voltage difference of node voltage V2 is sampled on the second sampling capacitance C2, when the first switch controlling signal is second electrical level, and second
When switch controlling signal is the first level, first switch K1, second switch K2, the 3rd switch K3 cut-off, the 4th switch K4, the 5th
Switch K5 conducting, the branch pressure voltage VA on the first sampling capacitance C1 and the voltage difference on the second sampling capacitance C2 are sampled the 3rd
On sampling capacitance C3, obtain output voltage VBG.
Further, work process is as follows:
Primary nodal point voltage V1 is equal to the emitter base voltage Vbe1 of the first bipolar transistor Q1, secondary nodal point voltage
V2 is equal to the emitter base voltage Vbe2, the first resistance R1 and the second resistance R2 of the second bipolar transistor Q2 to primary nodal point
Voltage V1 carries out dividing potential drop, and dividing ratios meets VA=V1/K, wherein K=(R1+R2)/R2, and wherein R1 is the resistance value of resistance R1,
R2 is the resistance value of resistance R2, and VA is the magnitude of voltage of divider node, when the first switch controlling signal is high level, and the first switch
K1, second switch K2, the 3rd switch K3 conducting, the 4th switch K4, the 5th switch K5 cut-off, the voltage VA of divider node is sampled
On the first sampling capacitance C1, i.e. VC1=VA=V1/K=Vbe1/K, wherein VC1 is the voltage on electric capacity C1, primary nodal point and
Voltage difference V1-V2 of secondary nodal point is sampled on the second sampling capacitance C2, i.e. VC2=V1-V2=Vbe1-Vbe2=Δ Vbe；
When second switch control signal CK2 is high level and the first switch controlling signal CK1 is low level, first switch K1, second
Switch K2, the 3rd switch K3 cut-off, the 4th switch K4, the 5th switch K5 conducting, now the first sampling capacitance C1 and second sampling
Electric capacity C2 connects, and and the 3rd sampling capacitance C3 parallel connection, the voltage on the first sampling capacitance C1 and the electricity of the second sampling capacitance C2
Laminated is sampled on the 3rd sampling capacitance C3 after adding.Now, the voltage VC3=VC1+VC2=on the 3rd sampling capacitance C3
Vbe1/K+ Δ Vbe, wherein, Vbe1 is negative temperature coefficient voltage, and Δ Vbe is positive temperature coefficient voltage.Therefore, it can by setting
Count suitable K value, it is achieved preferably temperature-compensating.
In a preferred embodiment, the referential data of K is 17.2, but different according to concrete manufacturing process, optimum K value
There are differences.
In another preferred embodiment, the current value of the first current source I1 current value equal to the second current source I2.
In another preferred embodiment, the current value of the first current source I1 current value more than the second current source I2,
And second the emitter area of bipolar transistor Q2 more than the emitter area of the first bipolar transistor Q1.
In another preferred embodiment, the second bipolar transistor Q2 emitter area is sent out with the first bipolar transistor Q1
Emitter-base bandgap grading area ratio is (N2-1) preferably coupling: 1, N is the progression more than or equal to 3, so can be formed when layout design
Effect.Such as N=3, the second bipolar transistor Q2 and the first bipolar transistor Q1 form the array of 3x3, bosom be
First bipolar transistor Q1, around 8 transistors are the second bipolar transistor Q2；As N=5, the second bipolar transistor Q2 with
First bipolar transistor Q1 forms the array of 5x5, bosom for the first bipolar transistor Q1, around 24 transistors are second
Bipolar transistor Q2.Now, because the electric current density of bipolar transistor is proportional to its emitter current, it is inversely proportional to it and launches pole-face
Long-pending, therefore, the ratio of the electric current density of the first bipolar transistor Q1 and the second bipolar transistor Q2 is the biggest, and the magnitude of voltage of Δ Vbe is more
Greatly, i.e. semaphore is the biggest, and it is the least that noise accounts for its ratio, and performance is the most superior.
The embodiment of the present invention is provided without operational amplifier, thus eliminates input offset voltage produced by operational amplifier
Impact, improves the precision of output voltage VBG, and owing to being provided without operational amplifier, it is not necessary to consume the bigger loop of chip area
Compensate circuit, so having less chip area；And sub-bandgap voltage can be produced, i.e. produce the ginseng of relatively low temperature-compensating
Examine voltage；And by regulation dividing ratios, and output voltage VBG can be changed.
Embodiment two
The circuit diagram of the band gap voltage generative circuit that Fig. 3 provides for the embodiment of the present invention two, as it is shown on figure 3, in this enforcement
In example, compare with Fig. 2, add the 3rd resistance R3 and the 4th resistance R4.
3rd resistance R3 and the 4th resistance R4 series connection, one end of the 3rd resistance R3 is connected with secondary nodal point, the 4th resistance
The base stage of one end of R4 and the second bipolar transistor Q2, colelctor electrode, the 3rd sampling capacitance C3 are connected.
When the first resistance R1 and the second resistance R2 resistance are less, the first resistance R1 and the second resistance R2 can shunt current source
The electric current of I1, causes the electric current of the first bipolar transistor Q1 to be affected by resistance change, therefore with the 3rd resistance R3 and the 4th electricity
Resistance R4 provides current compensation, with stabilizing circuit for described first bipolar transistor Q1.
When the first resistance R1 and the second resistance R2 resistance value design bigger time, the first resistance R1 and second can be ignored
The resistance R2 shunting to the first bipolar transistor Q1, now need not the 3rd resistance R3 and the 4th resistance R4 and goes to carry out electric current benefit
Repay, therefore can remove the 3rd resistance R3 and the 4th resistance R4.As in figure 2 it is shown, when removing the 3rd resistance R3 and the 4th resistance R4
Time, save the area of chip further.
Embodiment three
The circuit diagram of the band gap voltage generative circuit that Fig. 4 provides for the embodiment of the present invention three, as shown in Figure 4, in the diagram,
Annexation between biasing circuit 201 and the first transistor 202, transistor seconds 204 is identical with Fig. 2.
The first transistor 202 is specially the first bipolar transistor Q1, and transistor seconds 204 is specially the second bipolar transistor
Q2。
First current source I1 provides the first bias current for the first bipolar transistor Q1, so that the first bipolar transistor Q1 work
Make in the range of linearity, now, produce primary nodal point voltage V1, the second current source I2 and provide second inclined for the second bipolar transistor Q2
Put electric current, so that the second bipolar transistor Q2 is operated in the range of linearity, now, produce secondary nodal point voltage V2.
Voltage sampling circuit 203 includes that the first switch K1, second switch K2, the 3rd switch K3, and the 4th switch K4, the 5th opens
Close K5, the 6th switch K6, the 7th switch K7, the 8th switch K8, the first resistance R1, the second resistance R2, the first sampling capacitance C1, the
Two sampling capacitance C2, the 3rd sampling capacitance C3, the 4th sampling capacitance C4；
First switch K1, second switch K2, the 3rd switch K3, the 5th switch K5, the control end and first of the 6th switch K6
Switch controlling signal CK1 is connected, and the 4th switch K4, the 7th switch K7, the control end of the 8th switch K8 and second switch control
Signal CK2 is connected, and is connected to the base stage of described first bipolar transistor Q1, collection after the first resistance R1 and the second resistance R2 series connection
Electrode, the first sampling capacitance C1 one end and primary nodal point between, first switch K1 one end be connected to described first resistance R1
With second between resistance R2, the other end of the first switch K1 is connected to the other end of described first sampling capacitance C1, the 3rd switch
One end of K3 is connected with primary nodal point, and the described other end of the 3rd switch K3 and one end of the second sampling capacitance C2 are connected,
The described other end of the second sampling capacitance C2 is connected with one end of second switch K2, the other end of described second switch K2 and
Two nodes are connected, and one end of described 4th switch K4 is connected between described first switch K1 and the first sampling capacitance C1, institute
State the 4th switch K4 the other end be connected to second switch K2 and the 3rd switch K3 between, described 5th switch K5 one end and
Primary nodal point, the negative terminal of the first current source I1 are connected, the described 5th switch other end of K5 and one end of the 8th switch K8, the
One end of three sampling capacitance C3 is connected, and the other end of described 3rd sampling capacitance C3 and the 6th switch one end of K6, the 7th opens
The one end closing K7 is connected, and the described other end of the 6th switch K6 and the negative terminal of the second current source I2 are connected, and the described 7th opens
The other end closing K7 is connected between the second sampling capacitance C2 and the 3rd switch K3, and the other end of described 8th switch is connected to the
One end of four sampling capacitance C4, the other end of described 4th sampling capacitance C4 and the base stage of the second bipolar transistor Q2, colelctor electrode
It is connected；
When the first switch controlling signal is the first level, and second switch control signal is second electrical level, the first switch K1,
Second switch K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 conducting, the 4th switch K4, the 7th switch K7, the 8th open
Closing K8 cut-off, primary nodal point voltage V1 is sampled to first by the branch pressure voltage VA after the first resistance R1 and the second resistance R2 dividing potential drop
On sampling capacitance C1, the second sampling capacitance C2 and the 3rd sampling capacitance C3 is in parallel, primary nodal point voltage V1 and secondary nodal point voltage
The voltage difference of V2 be sampled the second sampling capacitance C2, and primary nodal point voltage V1 and the voltage difference quilt of secondary nodal point voltage V2
Sampling on the 3rd sampling capacitance C3, when the first switch controlling signal is second electrical level, second switch control signal is the first electricity
At ordinary times, the first switch K1, second switch K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 cut-off, the 4th switch K4, the
Seven switch K7, the 8th switch K8 conducting, the branch pressure voltage VA on the first sampling capacitance C1, the voltage difference on the second sampling capacitance C2
And the voltage difference that the 3rd on sampling capacitance C3 is sampled on the 4th sampling capacitance C4, obtain output voltage VBG.
Further, work process is as follows:
Primary nodal point voltage V1 is equal to the emitter base voltage Vbe1 of the first bipolar transistor Q1, secondary nodal point voltage
V2 is equal to the emitter base voltage Vbe2, the first resistance R1 and the second resistance R2 of the second bipolar transistor Q2 to primary nodal point
Voltage V1 carries out dividing potential drop, and dividing ratios meets VA=V1/K, wherein K=(R1+R2)/R2, and wherein R1 is the resistance value of resistance R1,
R2 is the resistance value of resistance R2, and VA is the magnitude of voltage of divider node, when the first switch controlling signal is high level, and the first switch
K1, second switch K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 conducting, the 4th switch K4, the 7th switch K7, the
Eight switch K8 cut-offs, the voltage VA of divider node is sampled on the first sampling capacitance C1, i.e. VC1=VA=V1/K=Vbe1/
K, wherein VC1 is the voltage on electric capacity C1, owing to the second sampling capacitance C2 and the 3rd sampling capacitance C3 are in parallel, primary nodal point and the
Voltage difference V1-V2 of two nodes is not only sampled on the second sampling capacitance C2, is also sampled on the 3rd sampling capacitance C3, i.e.
VC2=VC3=V1-V2=Vbe1-Vbe2=Δ Vbe；When second switch control signal CK2 is high level and the first on-off control
When signal CK1 is low level, the first switch K1, second switch K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 cut-off,
4th switch K4, the 7th switch K7, the 8th switch K8 conducting, now, the first sampling capacitance C1, the second sampling capacitance C2, the 3rd
Sampling capacitance C3 connects, and in parallel with the 4th sampling capacitance C4, voltage on the first sampling capacitance C1, the second sampling capacitance C2
It is sampled on the 4th sampling capacitance C4 after voltage superposition on voltage, the 3rd sampling capacitance C3.Now, the 4th sampling capacitance C4
On voltage VC4=VC1+VC2+VC3=2* Δ Vbe+Vbe1/K, wherein, Vbe1 is negative temperature coefficient voltage, and Δ Vbe is just
Temperaturecoefficient voltage.Therefore, it can by designing suitable K value, it is achieved preferably temperature-compensating.
In a preferred embodiment, the referential data of K is 17.2, but different according to concrete manufacturing process, optimum K value
There are differences.
In another preferred embodiment, the current value of the first current source I1 current value equal to the second current source I2.
In another preferred embodiment, the current value of the first current source I1 current value more than the second current source I2,
And second the emitter area of bipolar transistor Q2 more than the emitter area of the first bipolar transistor Q1.
In another preferred embodiment, the second bipolar transistor Q2 emitter area is sent out with the first bipolar transistor Q1
Emitter-base bandgap grading area ratio is (N2-1) preferably coupling: 1, N is the progression more than or equal to 3, so can be formed when layout design
Effect.Such as N=3, the second bipolar transistor Q2 and the first bipolar transistor Q1 form the array of 3x3, bosom be
First bipolar transistor Q1, around 8 transistors are the second bipolar transistor Q2；As N=5, the second bipolar transistor Q2 with
First bipolar transistor Q1 forms the array of 5x5, bosom for the first bipolar transistor Q1, around 24 transistors are the
Two bipolar transistor Q2.Now, because the electric current density of bipolar transistor is proportional to its emitter current, it is inversely proportional to its emitter stage
Area, therefore, the ratio of the electric current density of the first bipolar transistor Q1 and the second bipolar transistor Q2 is the biggest, the magnitude of voltage of Δ Vbe
The biggest, i.e. semaphore is the biggest, and it is the least that noise accounts for its ratio, and performance is the most superior.
The embodiment of the present invention is provided without operational amplifier, thus eliminates input offset voltage produced by operational amplifier
Impact, improves the precision of output voltage VBG, and owing to being provided without operational amplifier, it is not necessary to consume the bigger loop of chip area
Compensate circuit, so having less chip area；And sub-bandgap voltage can be produced, i.e. produce the ginseng of relatively low temperature-compensating
Examine voltage；And by regulation dividing ratios, and output voltage VBG can be changed.
Embodiment four
The circuit diagram of the band gap voltage generative circuit that Fig. 5 provides for the embodiment of the present invention four, as it is shown in figure 5, in Figure 5,
Annexation between biasing circuit 201 and the first transistor 202, transistor seconds 204 is identical with Fig. 2.The first transistor
202 are specially the first bipolar transistor Q1, and transistor seconds 204 is specially the second bipolar transistor Q2.
First current source I1 provides the first bias current for the first bipolar transistor Q1, so that the first bipolar transistor Q1 work
Make in the range of linearity, now, produce primary nodal point voltage V1, the second current source I2 and provide second inclined for the second bipolar transistor Q2
Put electric current, so that the second bipolar transistor Q2 is operated in the range of linearity, now, produce secondary nodal point voltage V2.
Voltage sampling circuit 203 includes: the first switch K1, second switch K2, the 3rd switchs K3, the 4th switch K4, the 5th
Switch K5, the first resistance R1, the second resistance R2, the first sampling capacitance C1, the second sampling capacitance C2, the 3rd sampling capacitance C3, the
One sampling capacitance C4；
First switch K1, second switch K2, the control end of the 3rd switch K3 and the first switch controlling signal are connected, and the 4th
Switch K4, the control end of the 5th switch K5 are connected with second switch control signal, the first resistance R1 and the second resistance R2 series connection
After be connected between one end and the primary nodal point of the base stage of described first bipolar transistor Q1, colelctor electrode, the first sampling capacitance C1,
One end of first switch K1 is connected between the first resistance R1 and the second resistance R2, and the other end of the first switch K1 is connected to the
The other end of one sampling capacitance C1, one end of the 3rd switch K3 is after the 3rd sampling capacitance C3 and the negative terminal phase of the first current source I1
Connecting, the 3rd switchs the other end of K3 one end with second switch K2 after the second sampling capacitance C2 connects, second switch K2's
The other end is connected with secondary nodal point, and one end of the 4th switch K4 is connected between the first sampling capacitance C1 and first switch K1,
The other end of the 4th switch K4 is connected between the second sampling capacitance C2 and second switch K2, and one end of the 5th switch K5 is connected to
Between 3rd switch K3 and the second sampling capacitance C2, the other end of the 5th switch K5 is connected to one end of the 4th sampling capacitance C4,
The other end and the base stage of the second bipolar transistor Q2, the colelctor electrode of the 4th sampling capacitance C4 are connected；
When the first switch controlling signal is the first level, and second switch control signal is second electrical level, the first switch K1,
Second switch K2, the 3rd switch K3 conducting, the 4th switch K4, the 5th switch K5 cut-off, primary nodal point voltage V1 is by the first resistance
Branch pressure voltage VA after R1 and the second resistance R2 dividing potential drop is sampled on the first sampling capacitance C1, the second sampling capacitance C2 and described
3rd sampling capacitance series connection, a part for the voltage difference of described primary nodal point voltage V1 and secondary nodal point voltage V2 is sampled the
On two sampling capacitance C2, another part of the voltage difference of described primary nodal point voltage V1 and secondary nodal point voltage V2 is sampled
On three sampling capacitance C3, when the first switch controlling signal is second electrical level, and second switch control signal is the first level, first
Switch K1, second switch K2, the 3rd switch K3 cut-off, the 4th switch K4, the 5th switch K5 conducting, on the first sampling capacitance C1
Described in voltage difference described in a part on branch pressure voltage VA, the second sampling capacitance C2 and the another part on the 3rd sampling capacitance C3
Voltage difference is sampled on the 4th sampling capacitance C4, obtains output voltage VBG.
Further, work process is as follows:
Primary nodal point voltage V1 is equal to the emitter base voltage Vbe1 of the first bipolar transistor Q1, secondary nodal point voltage
V2 is equal to the emitter base voltage Vbe2, the first resistance R1 and the second resistance R2 of the second bipolar transistor Q2 to primary nodal point
Voltage V1 carries out dividing potential drop, and dividing ratios meets VA=V1/K, wherein K=(R1+R2)/R2, and wherein R1 is the resistance value of resistance R1,
R2 is the resistance value of resistance R2, and VA is the branch pressure voltage value of divider node, when the first switch controlling signal is high level, and first
Switch K1, second switch K2, the 3rd switch K3 conducting, the 4th switch K4, the 5th switch K5 cut-off, the voltage VA of divider node
Being sampled on the first sampling capacitance C1, i.e. VC1=VA=V1/K=Vbe1/K, wherein VC1 is on the first sampling capacitance C1
Voltage, owing to the second sampling capacitance C2 and the 3rd sampling capacitance C3 connects, voltage difference V1-V2 of primary nodal point and secondary nodal point
A part is sampled on the second sampling capacitance C2, and another part of voltage difference V1-V2 of primary nodal point and secondary nodal point is adopted
Sample is on the 3rd sampling capacitance C3, i.e. VC2+VC3=V1-V2=Vbe1-Vbe2=Δ Vbe, wherein VC2 is the second sampling capacitance
Voltage on C2, VC3 is the voltage on the 3rd sampling capacitance C3；When second switch control signal CK2 is that high level and first is opened
Close control signal CK1 when being low level, the first switch K1, second switch K2, the 3rd switch K3 cut-off, the 4th switch K4, the 5th
Switch K5 leads to, now, and the first sampling capacitance C1, the second sampling capacitance C2, and in parallel with the 4th sampling capacitance C4, the first sampling electricity
It is sampled on the 4th sampling capacitance C4 after holding the voltage superposition of the voltage on C1, the second sampling capacitance C2.Now, if designed
The resistance of the second sampling capacitance C2 and the 3rd sampling capacitance C3 is equal, then it is known that the second sampling capacitance C2 and the 3rd samples
During electric capacity C3 series connection, described voltage difference is divided equally, i.e. VC2=VC3=Δ Vbe/2, now, the voltage on the 4th sampling capacitance C4
VC4=VC1+VC2+VC3=1/2* Δ Vbe+Vbe1/K, wherein, Vbe1 is negative temperature coefficient voltage, and Δ Vbe is positive temperature system
Number voltage.Therefore, it can by designing suitable K value, it is achieved preferably temperature-compensating.
In a preferred embodiment, the referential data of K is 17.2, but different according to concrete manufacturing process, optimum K value
There are differences.
In another preferred embodiment, the current value of the first current source I1 current value equal to the second current source I2.
In another preferred embodiment, the current value of the first current source I1 current value more than the second current source I2,
And second the emitter area of bipolar transistor Q2 more than the emitter area of the first bipolar transistor Q1.
In another preferred embodiment, the second bipolar transistor Q2 emitter area is sent out with the first bipolar transistor Q1
Emitter-base bandgap grading area ratio is (N2-1) preferably coupling: 1, N is the progression more than or equal to 3, so can be formed when layout design
Effect.Such as N=3, the second bipolar transistor Q2 and the first bipolar transistor Q1 form the array of 3x3, bosom be
First bipolar transistor Q1, around 8 transistors are the second bipolar transistor Q2；As N=5, the second bipolar transistor Q2 with
First bipolar transistor Q1 forms the array of 5x5, bosom for the first bipolar transistor Q1, around 24 transistors are second
Bipolar transistor Q2.Now, because the electric current density of bipolar transistor is proportional to its emitter current, it is inversely proportional to it and launches pole-face
Long-pending, therefore, the ratio of the electric current density of the first bipolar transistor Q1 and the second bipolar transistor Q2 is the biggest, and the magnitude of voltage of Δ Vbe is more
Greatly, i.e. semaphore is the biggest, and it is the least that noise accounts for its ratio, and performance is the most superior.
The embodiment of the present invention is provided without operational amplifier, thus eliminates input offset voltage produced by operational amplifier
Impact, improves the precision of output voltage VBG, and owing to being provided without operational amplifier, it is not necessary to consume the bigger loop of chip area
Compensate circuit, so having less chip area；And sub-bandgap voltage can be produced, i.e. produce the ginseng of relatively low temperature-compensating
Examine voltage；And by regulation dividing ratios, and output voltage VBG can be changed.Existing band-gap circuit is limited due to self structure,
Typically can only produce output voltage (its exact value and technique, the transmitting pole-face of bipolar transistor of band gap voltage (about 1.25V)
Long-pending relevant), or the integral multiple of band gap voltage.And the band gap voltage generative circuit provided by the application embodiment of the present invention, permissible
Producing the voltage less than band gap voltage, such as 1.25V/K, as K=8.5, output voltage is 0.147V.
It should be noted that in the circuit of Fig. 4 and Fig. 5, when the first resistance R1 and the second resistance R2 resistance are less, the
The electric current of one resistance R1 and the second resistance R2 meeting shunt current source I1, causes the electric current of the first bipolar transistor Q1 to be become by resistance value
The impact changed, therefore the 3rd resistance R3 and the 4th resistance R4 can be added in figures 4 and 5, think that the first bipolar transistor Q1 carries
For current compensation, with stabilizing circuit.
It is understood that in the circuit of Fig. 2-Fig. 5, can be by increasing number of switches and the electricity to Δ Vbe sampling
Hold number, build the reference voltage level of superposition more Δ Vbe, it is possible to build VBG=N* Δ Vbe+Vbe1/K, wherein N
For positive number.
Professional should further appreciate that, each example described in conjunction with the embodiments described herein
Unit and algorithm steps, it is possible to electronic hardware, computer software or the two be implemented in combination in, hard in order to clearly demonstrate
Part and the interchangeability of software, the most generally describe composition and the step of each example according to function.
These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.
Professional and technical personnel can use different methods to realize described function to each specifically should being used for, but this realization
It is not considered that it is beyond the scope of this invention.
Above-described detailed description of the invention, has been carried out the purpose of the present invention, technical scheme and beneficial effect further
Describe in detail, be it should be understood that the detailed description of the invention that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, all within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. done, all should comprise
Within protection scope of the present invention.
Claims (10)
1. a band gap voltage generative circuit, it is characterised in that described band gap voltage generative circuit includes: the first on-off control letter
Number, second switch control signal, biasing circuit, the first transistor, transistor seconds, voltage sampling circuit；
Described biasing circuit, for providing the first bias current for described the first transistor, provides for described transistor seconds
Two bias currents；
Described biasing circuit includes the first current source I1 and the second current source I2, and described the first transistor is the first bipolar transistor
Q1, described transistor seconds is the second bipolar transistor Q2；
The emitter stage of described the first transistor Q1 is connected at primary nodal point with described biasing circuit, for described biasing circuit is
Described the first transistor Q1 provides the first bias current；
Described transistor seconds Q2 is connected at secondary nodal point with described biasing circuit, is described second for described biasing circuit
Transistor Q2 provides the second bias current；
Described voltage sampling circuit, including the first sampling capacitance C1 and the second sampling capacitance C2,
Utilize the voltage of the first sampling capacitance C1 sampling primary nodal point, utilize the second sampling capacitance C2 sampling primary nodal point and second
The voltage difference of node, obtains output electricity based on the voltage on the voltage on the first sampling capacitance C1 and the second sampling capacitance C2
Pressure.
Band gap voltage generative circuit the most according to claim 1, it is characterised in that the anode of described first current source I1 is even
Being connected to power supply, the anode of described second current source I2 is connected to power supply, the emitter stage and first of described first bipolar transistor Q1
The negative terminal of current source I1 is connected, the colelctor electrode of described first bipolar transistor Q1 be connected with base stage after ground connection, described second
The emitter stage of bipolar transistor Q2 and the negative terminal of the second current source I2 are connected, the colelctor electrode of described second bipolar transistor Q2 and
Ground connection after base stage connection.
Band gap voltage generative circuit the most according to claim 1, it is characterised in that described voltage sampling circuit includes: the
One switch K1, second switch K2, the 3rd switchs K3, the 4th switch K4, the 5th switch K5, the first resistance R1, the second resistance R2, the
One sampling capacitance C1, the second sampling capacitance C2, the 3rd sampling capacitance C3；
Described first switch K1, second switch K2, the control end of the 3rd switch K3 and the first switch controlling signal are connected, described
4th switch K4, the control end of the 5th switch K5 are connected with second switch control signal, described first resistance R1 and second electricity
It is connected to the base stage of described first bipolar transistor Q1, colelctor electrode, one end and first of the first sampling capacitance C1 after resistance R2 series connection
Between node, one end of described first switch K1 is connected between described first resistance R1 and the second resistance R2, and described first opens
The other end closing K1 is connected to the other end of described first sampling capacitance C1, one end of described 3rd switch K3 and primary nodal point phase
Connecting, the described other end of the 3rd switch K3 and one end of the second sampling capacitance C2 are connected, described second sampling capacitance C2's
The other end is connected with one end of second switch K2, and the other end of described second switch K2 is connected with secondary nodal point, and described
One end of four switch K4 is connected between described first switch K1 and the first sampling capacitance C1, the other end of described 4th switch K4
Being connected between second switch K2 and the 3rd switch K3, one end of described 5th switch K5 is connected to the 3rd switch K3 and second and adopts
Between sample electric capacity C2, the described other end of the 5th switch K5 and one end of the 3rd sampling capacitance C3 are connected, described 3rd sampling
The other end and the base stage of the second bipolar transistor Q2, the colelctor electrode of electric capacity C3 are connected；
When described first switch controlling signal is the first level, and described second switch control signal is second electrical level, described
One switch K1, second switch K2, the 3rd switch K3 conducting, described 4th switch K4, the 5th switch K5 cut-off, described primary nodal point
Voltage V1 is sampled on the first sampling capacitance C1 by the branch pressure voltage VA after described first resistance R1 and the second resistance R2 dividing potential drop,
The voltage difference of described primary nodal point voltage V1 and secondary nodal point voltage V2 is sampled on the second sampling capacitance C2, when described first
Switch controlling signal is second electrical level, when described second switch control signal is the first level, described first switch K1, second opens
Close K2, the 3rd switch K3 cut-off, described 4th switch K4, the 5th switch K5 conducting, the dividing potential drop on described first sampling capacitance C1
Voltage difference on voltage VA and the second sampling capacitance C2 is sampled on the 3rd sampling capacitance C3, obtains output voltage.
Band gap voltage generative circuit the most according to claim 3, it is characterised in that described voltage sampling circuit includes: the
Three resistance R3, the 4th resistance R4；
Described 3rd resistance R3 and the 4th resistance R4 series connection, one end of described 3rd resistance R3 is connected with secondary nodal point, described
The base stage of one end of the 4th resistance R4 and the second bipolar transistor Q2, colelctor electrode, the 3rd sampling capacitance C3 are connected.
Band gap voltage generative circuit the most according to claim 1, it is characterised in that described voltage sampling circuit includes: the
One switch K1, second switch K2, the 3rd switchs K3, the 4th switch K4, the 5th switch K5, the 6th switch K6, the 7th switch K7, the
Eight switch K8, the first resistance R1, the second resistance R2, the first sampling capacitance C1, the second sampling capacitance C2, the 3rd sampling capacitance C3,
4th sampling capacitance C4；
Described first switch K1, second switch K2, the 3rd switch K3, the 5th switch K5, the control end and first of the 6th switch K6
Switch controlling signal is connected, and described 4th switch K4, the 7th switch K7, the control end of the 8th switch K8 and second switch control
Signal is connected, described first resistance R1 and the second resistance R2 series connection after be connected to described first bipolar transistor Q1 base stage,
Colelctor electrode, the first sampling capacitance C1 one end and primary nodal point between, described first switch K1 one end be connected to described first
Between resistance R1 and the second resistance R2, the other end of described first switch K1 is connected to another of described first sampling capacitance C1
End, one end of described 3rd switch K3 is connected with primary nodal point, the other end of described 3rd switch K3 and the second sampling capacitance
One end of C2 is connected, and the described other end of the second sampling capacitance C2 is connected with one end of second switch K2, and described second opens
The other end closing K2 is connected with secondary nodal point, and one end of described 4th switch K4 is connected to described first switch K1 and first and adopts
Between sample electric capacity C1, the other end of described 4th switch K4 is connected between second switch K2 and the 3rd switch K3, and the described 5th
One end of switch K5 is connected with the negative terminal of primary nodal point, the first current source I1, the other end and the 8th of described 5th switch K5
Switch one end of K8, one end of the 3rd sampling capacitance C3 are connected, the other end of described 3rd sampling capacitance C3 and the 6th switch
One end of K6, one end of the 7th switch K7 are connected, the other end of described 6th switch K6 and the negative terminal phase of the second current source I2
Connecting, the other end of described 7th switch K7 is connected between the second sampling capacitance C2 and the 3rd switch K3, described 8th switch
The other end be connected to one end of the 4th sampling capacitance C4, the other end of described 4th sampling capacitance C4 and the second bipolar transistor
The base stage of Q2, colelctor electrode are connected；
When described first switch controlling signal is the first level, and described second switch control signal is second electrical level, described
One switch K1, second switch K2, the 3rd switch K3, the 5th switch K5, the 6th switch K6 conducting, described 4th switch K4, the 7th
Switch K7, the 8th switch K8 cut-off, described primary nodal point voltage V1 is by after described first resistance R1 and the second resistance R2 dividing potential drop
Branch pressure voltage VA is sampled on the first sampling capacitance C1, and described second sampling capacitance C2 and the 3rd sampling capacitance C3 is in parallel, institute
State primary nodal point voltage V1 and secondary nodal point voltage V2 voltage difference be sampled the second sampling capacitance C2, and described first segment
The voltage difference of point voltage V1 and secondary nodal point voltage V2 is sampled on the 3rd sampling capacitance C3, when described first on-off control letter
Number be second electrical level, when described second switch control signal is the first level, described first switch K1, second switch K2, the 3rd
Switch K3, the 5th switch K5, the 6th switch K6 cut-off, described 4th switch K4, the 7th switch K7, the 8th switch K8 conducting, institute
State the voltage difference on the branch pressure voltage VA on the first sampling capacitance C1, the second sampling capacitance C2 and the electricity on the 3rd sampling capacitance C3
Pressure reduction is sampled on the 4th sampling capacitance C4, obtains output voltage.
Band gap voltage generative circuit the most according to claim 1, it is characterised in that described voltage sampling circuit includes: the
One switch K1, second switch K2, the 3rd switchs K3, the 4th switch K4, the 5th switch K5, the first resistance R1, the second resistance R2, the
One sampling capacitance C1, the second sampling capacitance C2, the 3rd sampling capacitance C3, the first sampling capacitance C4；
Described first switch K1, second switch K2, the control end of the 3rd switch K3 and the first switch controlling signal are connected, described
4th switch K4, the control end of the 5th switch K5 are connected with second switch control signal, described first resistance R1 and second electricity
It is connected to the base stage of described first bipolar transistor Q1, colelctor electrode, one end and first of the first sampling capacitance C1 after resistance R2 series connection
Between node, one end of described first switch K1 is connected between described first resistance R1 and the second resistance R2, and described first opens
The other end closing K1 is connected to the other end of described first sampling capacitance C1, one end the 3rd sampling electricity of described 3rd switch K3
Hold after C3 and be connected with the negative terminal of the first current source I1, the other end of described 3rd switch K3 after the second sampling capacitance C2 with the
One end of two switch K2 connects, and the other end of described second switch K2 is connected with secondary nodal point, the one of described 4th switch K4
End is connected between the first sampling capacitance C1 and first switch K1, and the other end of described 4th switch K4 is connected to the second sampling electricity
Hold between C2 and second switch K2, one end of described 5th switch K5 be connected to the 3rd switch K3 and the second sampling capacitance C2 it
Between, the other end of described 5th switch K5 is connected to one end of the 4th sampling capacitance C4, another of described 4th sampling capacitance C4
End is connected with base stage, the colelctor electrode of the second bipolar transistor Q2；
When described first switch controlling signal is the first level, and described second switch control signal is second electrical level, described
One switch K1, second switch K2, the 3rd switch K3 conducting, described 4th switch K4, the 5th switch K5 cut-off, described primary nodal point
Voltage V1 is sampled on the first sampling capacitance C1 by the branch pressure voltage VA after described first resistance R1 and the second resistance R2 dividing potential drop,
Described second sampling capacitance C2 and described 3rd sampling capacitance series connection, described primary nodal point voltage V1's and secondary nodal point voltage V2
A part for voltage difference is sampled on the second sampling capacitance C2, described primary nodal point voltage V1 and the electricity of secondary nodal point voltage V2
Another part of pressure reduction is sampled on the 3rd sampling capacitance C3, when described first switch controlling signal is second electrical level, described
When second switch control signal is the first level, described first switch K1, second switch K2, the 3rd switch K3 cut-off, described the
Four switch K4, the 5th switch K5 conducting, on branch pressure voltage VA, the second sampling capacitance C2 on described first sampling capacitance C1
Voltage difference described in another part in the described voltage difference of part and the 3rd sampling capacitance C3 is sampled on the 4th sampling capacitance C4,
Obtain output voltage.
Band gap voltage generative circuit the most according to claim 1, it is characterised in that the current value of described first current source I1
Current value equal to described second current source I2.
Band gap voltage generative circuit the most according to claim 1, it is characterised in that the current value of described first current source I1
More than the current value of described second current source I2, and the emitter area of the first bipolar transistor Q1 is more than described first bipolar crystalline substance
The area of body pipe Q2.
Band gap voltage generative circuit the most according to claim 1, it is characterised in that described second bipolar transistor Q2 sends out
Emitter-base bandgap grading area is (N2-1) with the area ratio of described first bipolar transistor Q1: 1, and wherein, N is progression, and N >=3.
10. according to the band gap voltage generative circuit described in claim 1, it is characterised in that the electricity of described sampling primary nodal point
Downsampling factor K=(R1+R2)/R2 during pressure, wherein, R1 is the resistance of the first resistance R1, and R2 is the resistance of the second resistance R2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN105159391B (en) * | 2015-10-22 | 2018-01-19 | 杭州士兰微电子股份有限公司 | A kind of current source and the oscillating circuit using the current source |
| CN107390756B (en) * | 2016-05-16 | 2018-12-14 | 瑞昱半导体股份有限公司 | Reference voltage buffer circuit |
| CN107817860B (en) * | 2016-09-14 | 2020-01-03 | 中科芯云微电子科技有限公司 | Low-voltage bandgap reference circuit and voltage generating circuit |
| CN110045778B (en) * | 2018-01-16 | 2020-07-31 | 智原科技股份有限公司 | Voltage generating device and calibration method thereof |
| CN111064453B (en) * | 2019-12-13 | 2023-07-04 | 南京中感微电子有限公司 | Voltage comparator |
| CN113203494A (en) * | 2020-02-01 | 2021-08-03 | 瑞昱半导体股份有限公司 | Temperature sensing circuit |
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| JP5251541B2 (en) * | 2009-01-26 | 2013-07-31 | 富士通セミコンダクター株式会社 | Constant voltage generator and regulator circuit |
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| US5352972A (en) * | 1991-04-12 | 1994-10-04 | Sgs-Thomson Microelectronics, S.R.L. | Sampled band-gap voltage reference circuit |
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