CN104701168A - Forming method of fin field-effect transistor - Google Patents
Forming method of fin field-effect transistor Download PDFInfo
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- CN104701168A CN104701168A CN201310655009.1A CN201310655009A CN104701168A CN 104701168 A CN104701168 A CN 104701168A CN 201310655009 A CN201310655009 A CN 201310655009A CN 104701168 A CN104701168 A CN 104701168A
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- 238000000034 method Methods 0.000 title claims abstract description 96
- 230000005669 field effect Effects 0.000 title claims abstract description 47
- 230000004888 barrier function Effects 0.000 claims abstract description 112
- 239000004065 semiconductor Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 150000002500 ions Chemical class 0.000 claims description 98
- 238000005468 ion implantation Methods 0.000 claims description 64
- 239000011248 coating agent Substances 0.000 claims description 54
- 238000000576 coating method Methods 0.000 claims description 54
- 230000015572 biosynthetic process Effects 0.000 claims description 50
- 230000008569 process Effects 0.000 claims description 49
- 239000003989 dielectric material Substances 0.000 claims description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 33
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000005137 deposition process Methods 0.000 claims description 7
- 238000009499 grossing Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 5
- 230000004913 activation Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 8
- 230000008901 benefit Effects 0.000 abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract 2
- 150000004706 metal oxides Chemical class 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 194
- 238000009792 diffusion process Methods 0.000 description 15
- 230000007547 defect Effects 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 230000002829 reductive effect Effects 0.000 description 6
- 230000000873 masking effect Effects 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000036961 partial effect Effects 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- -1 P ion Chemical class 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
- H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners
Abstract
A forming method of a fin field-effect transistor includes: providing a semiconductor substrate comprising an NMOS (N-channel metal oxide semiconductor) area and a PMOS (P-channel metal oxide semiconductor) area; etching the semiconductor substrate to form a first fin portion in the NMOS area and a second fin portion in the PMOS area; forming a dielectric layer on the surface of the first and second fin portions, with the surface of the dielectric layer being flush with the top of the first and second fin portions; subjecting the second fin portion to second ion implanting to form a second through barrier layer in the second fin portion; subjecting the first fin portion to first ion implanting to form a first through barrier layer in the first fin portion; removing part, of certain thickness, of the dielectric layer so that the surface of the dielectric layer is flush with the surface of the first and second through barrier layers or lower than the first and second through barrier layers. The forming method has the advantages that breakthrough between a source and a drain can be avoided and the performance of the fin field-effect transistor is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of fin formula field effect transistor.
Background technology
Along with the development of semiconductor process techniques, process node reduces gradually, and rear grid (gate-last) technique is widely applied, and to obtain desirable threshold voltage, improves device performance.But when the characteristic size of device declines further, even if grid technique after adopting, the structure of conventional metal-oxide-semiconductor field effect transistor also cannot meet the demand to device performance, and fin formula field effect transistor (Fin FET) obtains as a kind of multi-gate device and pays close attention to widely.
Fin formula field effect transistor is a kind of common multi-gate device, and Fig. 1 shows the perspective view of a kind of fin formula field effect transistor of prior art.
As shown in Figure 1, comprising: Semiconductor substrate 10, described Semiconductor substrate 10 is formed with the fin 11 of protrusion, fin 11 generally obtains after etching Semiconductor substrate 10; Dielectric layer 12, covers a part for the surface of described Semiconductor substrate 10 and the sidewall of fin 11; Grid structure 13, across on described fin 11, covers atop part and the sidewall of described fin 11, and grid structure 13 comprises gate dielectric layer (not shown) and is positioned at the gate electrode (not shown) on gate dielectric layer.For fin formula field effect transistor, the part that the top of fin 11 and the sidewall of both sides contact with grid structure 13 all becomes channel region, namely has multiple grid, is conducive to increasing drive current, improves device performance.
Often there will be the phenomenon of Punchthrough between the source electrode of the fin formula field effect transistor that prior art is formed and drain electrode, affect the performance of fin formula field effect transistor.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of fin formula field effect transistor, avoids occurring Punchthrough between the source electrode of fin formula field effect transistor and drain electrode.
For solving the problem, the invention provides a kind of formation method of fin formula field effect transistor, comprising: provide Semiconductor substrate, described Semiconductor substrate comprises NMOS area and PMOS area; Etch described Semiconductor substrate, form the first fin in NMOS area, form the second fin in PMOS area; Dielectric layer is formed on the surface of described Semiconductor substrate, the first fin and the second fin, described dielectric layer comprises the resilient coating on the surface being positioned at Semiconductor substrate, the first fin and the second fin and is positioned at the layer of dielectric material of described buffer-layer surface, and the surface of described dielectric layer flushes with the top of the first fin and the second fin; Second ion implantation is carried out to described second fin, in described second fin, forms the second break-through barrier layer; First ion implantation is carried out to described first fin, in described first fin, forms the first break-through barrier layer; Remove the dielectric layer of segment thickness, the surface of described dielectric layer is flushed with the surface on the first break-through barrier layer, the second break-through barrier layer or lower than the surface on described first break-through barrier layer, the second break-through barrier layer.
Optionally, the temperature of described first ion implantation and the second ion implantation is 300 DEG C ~ 400 DEG C.
Optionally, the ionic type of described second ion implantation is N-type ion, and Implantation Energy is 20KeV ~ 60KeV, and in the described second break-through barrier layer of formation, the doping content of described N-type ion is 1E12atom/cm
3~ 5E13atom/cm
3.
Optionally, the ion of described second ion implantation is P ion.
Optionally, the ion of described second ion implantation also comprises F ion.
Optionally, the ionic type of described first ion implantation is P type ion, and Implantation Energy is 20KeV ~ 60KeV, and in the described first break-through barrier layer of formation, the doping content of described P type ion is 1E12atom/cm
3~ 5E13atom/cm
3.
Optionally, the ion of described first ion implantation is B ion.
Optionally, the ion of described first ion implantation also comprises C ion.
Optionally, the temperature of heat-treating described dielectric layer is 500 DEG C ~ 1500 DEG C.
Optionally, described dielectric layer comprises the resilient coating being positioned at described Semiconductor substrate, the first fin and the second fin portion surface and the layer of dielectric material being positioned at described buffer-layer surface.
Optionally, the material of described resilient coating is silicon oxynitride or silica.
Optionally, the formation method of described resilient coating is thermal oxidation technology or atom layer deposition process.
Optionally, described first fin and the second fin top has mask layer.
Optionally, the material of described mask layer is silicon nitride.
Optionally, after removing the dielectric layer of segment thickness, described mask layer is removed.
Optionally, also comprise: after the good described first break-through barrier layer of formation and the second break-through barrier layer, carry out the Doped ions in the thermal anneal process described first break-through barrier layer of activation and the second break-through barrier layer.
Optionally, the temperature of described annealing in process is 500 DEG C ~ 1000 DEG C.
Optionally, also comprise: after removing the dielectric layer of segment thickness, surface smoothing process and fillet process are carried out to part first fin do not covered by dielectric layer and the second fin.
Optionally, the method for the first fin of described exposure and the second fin being carried out to surface smoothing process and fillet process comprises: carry out oxidation processes at described the first fin of not exposed by the part that dielectric layer covers and the second fin portion surface, form oxide layer; Wet-etching technology is adopted to remove described oxide layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
Technical scheme of the present invention, form the first fin and the second fin on the semiconductor substrate, and after described first fin, the second fin and semiconductor substrate surface form dielectric layer, second ion implantation is carried out to described second fin, form the second break-through barrier layer, the first ion implantation is carried out to the first fin, form the first break-through barrier layer.In the present embodiment, described first break-through barrier layer and the second break-through barrier layer is formed again after described first fin and the second fin portion surface form described resilient coating and layer of dielectric material, the quality of the resilient coating of formation can be improved on the one hand, improve the diffusion barrier effect to the Doped ions in the first break-through barrier layer and the second break-through barrier layer in subsequent technique of described resilient coating; On the other hand, the Doped ions in described first break-through barrier layer and the second break-through barrier layer does not need to be subject to forming the heat treatment process in described resilient coating and layer of dielectric material process, thus can reduce the diffusion of Doped ions.
Further, described first ion implantation and the second ion implantation are at high temperature carried out, the temperature of described injection is 300 DEG C ~ 400 DEG C, under described hot conditions, carry out the first ion implantation and the second ion implantation, the damage that described first ion implantation and the second ion implantation cause described first fin and the second fin can be reduced.
The ion of described first ion implantation can also comprise C ion, and described C ion can adsorb the defect in the first fin; The ion of the second ion implantation can also comprise F ion, and described F ion can substitute in described second fin due to defective locations that ion implantation causes; And the diffusion of described Doped ions mainly relies on the defect in described first fin and the second fin, described, B ion and F ion can stop Doped ions in described first break-through barrier layer and the second break-through barrier layer to outdiffusion, thus can guarantee that the Doped ions distribution in described first break-through layer and the second break-through barrier layer is comparatively concentrated.
Accompanying drawing explanation
Fig. 1 is the structural representation of the fin formula field effect transistor of prior art of the present invention;
Fig. 2 to Figure 10 is the structural representation of the forming process of the fin formula field effect transistor of embodiments of the invention.
Embodiment
As described in the background art, easily there is Punchthrough phenomenon in the fin formula field effect transistor that prior art is formed, affects the performance of fin formula field effect transistor.
Formed in the embodiment of fin formula field effect transistor at one, after ion implantation formation break-through barrier layer is carried out to Semiconductor substrate, etch described Semiconductor substrate, form fin, make, in described fin, there is break-through barrier layer, the punch through voltage between source electrode and drain electrode can be improved.
But research finds, the Doped ions in described break-through barrier layer to outdiffusion, finally can make the ion doping concentration in described break-through barrier layer reduce, makes to decline to the blocking effect of Punchthrough in the process forming fin formula field effect transistor.And this mainly due to, being formed in the processing step after described fin, need the heat treatment process of carrying out repeatedly, described heat treatment process can improve the diffusion rate of Doped ions, causes Doped ions in described break-through barrier layer to outdiffusion.
Propose a kind of formation method of fin formula field effect transistor in embodiments of the invention, the Doped ions in the break-through barrier layer that can avoid the formation of, to outdiffusion, improves the blocking effect of described break-through barrier layer for Punchthrough.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 2, provide Semiconductor substrate 100, described Semiconductor substrate comprises NMOS area and PMOS area.
Described Semiconductor substrate 100 can be silicon or silicon-on-insulator (SOI), and described Semiconductor substrate 100 also can be germanium, germanium silicon, GaAs or germanium on insulator, and the material of Semiconductor substrate 100 described in this enforcement is body silicon.Adopt body silicon substrate can reduce the cost forming fin formula field effect transistor as Semiconductor substrate 100, and compatible with the manufacture craft of existing planar transistor.
In the NMOS area of described Semiconductor substrate 100, be formed with P trap, in PMOS area, be formed with N trap.
In other embodiments of the invention, also described Semiconductor substrate 100 adjusting thresholds is injected, to regulate the threshold voltage of the transistor that the NMOS area of formation and PMOS area are formed.And described Semiconductor substrate 100 is annealed, to activate the Doped ions in described Semiconductor substrate 100.
Please refer to Fig. 3, form Patterned masking layer 200 on described Semiconductor substrate 100 surface.
The material of described Patterned masking layer 200 can be the single layer structure of silica, silicon nitride, also can be the stacked structure of silica and silicon nitride.In the present embodiment, described Patterned masking layer 200 is the stacked structure of oxide-nitride-oxide, comprising: be positioned at first silicon oxide layer 201 on Semiconductor substrate 100 surface, be positioned at the silicon nitride layer 202 on described first silicon oxide layer 201 surface and be positioned at second silicon oxide layer 203 on described silicon nitride layer 202 surface.
Described Patterned masking layer 200 defines position and the size of follow-up first fin that will be formed and the second fin, as the mask layer of Semiconductor substrate described in subsequent etching 100.
Please refer to Fig. 4, with described Patterned masking layer 200 for mask, etch described Semiconductor substrate 100, form the first fin 110 in described NMOS area, form the second fin 120 in described PMOS area.
Adopt dry etch process, etch described Semiconductor substrate 100.In the present embodiment, the etching gas that described dry etch process adopts is HBr and Cl
2mist as etching gas, O
2as buffer gas, wherein the flow of HBr is 50sccm ~ 1000sccm, Cl
2flow be 50sccm ~ 1000sccm, O
2flow be 5sccm ~ 20sccm, pressure is 5mTorr ~ 50mTorr, and power is 400W ~ 750W, O
2gas flow be 5sccm ~ 20sccm, temperature is 40 DEG C ~ 80 DEG C, and bias voltage is 100V ~ 250V.
In the present embodiment, adopt above-mentioned technique to etch Semiconductor substrate 100 and form the first fin 110 respectively on an nmos area, PMOS area is formed the second fin 120, the quantity of described first fin 110 and the second fin 120 is two, in other embodiments of the invention, described first fin 110 and the second fin 120 can also be one or more.
The sidewall slope of described first fin 110 and the second fin 120, the top width of the first fin 110 and the second fin 120 is less than the bottom width of described first fin 110 and the second fin 120.In the present embodiment, the formed sharp angle of the sidewall of described first fin 110 and the second fin 120 and Semiconductor substrate 100 surface is 70 ° ~ 95 °.
In the present embodiment, described first fin 110 of formation and the height of the second fin 120 are 60nm ~ 200nm, and the top width of described first fin 110 and the second fin 120 is 10nm ~ 50nm.
Please refer to Fig. 5, form resilient coating 301 on the surface of described Semiconductor substrate 100 and the first fin 101, second fin 102.
The material of described resilient coating 301 is silicon oxynitride or silica, and the thickness of described resilient coating 301 is 1nm ~ 5nm.The damage that can repair described resilient coating 301 described first fin 110 and the second fin 120 sidewall surfaces cause due to etching technics, and, described resilient coating 301 can also, as diffusion impervious layer, stop the follow-up Doped ions injected in described first fin 110 and the second fin 120 to outdiffusion.
The formation method of described resilient coating 301 can be thermal oxidation technology or atom layer deposition process.In the present embodiment, the method forming described resilient coating 301 is atom layer deposition process, the material of described resilient coating 301 is silica, and described resilient coating 301 covers Semiconductor substrate 100 surface, the first fin 110 and the sidewall surfaces of the second fin 120 and the surface of mask layer 200.Adopt atom layer deposition process can form the thickness resilient coating 301 less compared with defect.
In other embodiments of the invention, also can pass through thermal oxidation technology, form resilient coating 301 in the sidewall surfaces of described Semiconductor substrate 100 surface and the first fin 110 and the second fin 120, the material of described resilient coating is silica.
In other embodiments of the invention, described resilient coating 301 can also be adopt thermal oxidation technology after Semiconductor substrate 100 and the first fin 110, second fin 120 surface form silica, silicon nitride layer is formed again at described silicon oxide surface, described resilient coating 301 is the stacked structure of silica and silicon nitride, can improve the diffusion barrier effect of described resilient coating further.
Please refer to Fig. 6, form layer of dielectric material 302 on described resilient coating 301 surface.
The material of described layer of dielectric material 302 can be the insulating dielectric materials such as silica, silicon oxynitride, silicon oxide carbide.In the present embodiment, the material of the described medium bed of material 302 is silica.
In the present embodiment, described layer of dielectric material 302 can adopt high density plasma CVD technique (HDP) to be formed.The groove of described high density plasma CVD technique to larger depth-to-width ratio has higher filling quality.
The method forming described layer of dielectric material 302 comprises: at described resilient coating 301 surface deposition dielectric material, and described dielectric material covers Semiconductor substrate 100 and described first fin 110 and the second fin 120, mask layer 200; Using the silicon nitride layer 202 in described mask layer 200 as polish stop layer, adopt chemical mechanical milling tech to carry out planarization to described dielectric material, form layer of dielectric material 302, the surface of described layer of dielectric material 302 is flushed with the surface of silicon nitride layer 202.
Described layer of dielectric material 302 and resilient coating 301 are as the dielectric layer on Semiconductor substrate 100 surface, described dielectric layer is as the isolation structure between the grid structure of the fin formula field effect transistor of follow-up formation and Semiconductor substrate 100, and the isolation structure between adjacent first fin 110 and the second fin 120.
Because described layer of dielectric material 302 adopts high density plasma CVD technique (HDP) to be formed, due to the effect of plasma in deposition process, more defect can be formed in described layer of dielectric material, so need to heat-treat described layer of dielectric material 302, to eliminate the defect in described layer of dielectric material 302.Described heat treated temperature can be 500 DEG C ~ 1500 DEG C.
Please refer to Fig. 7, the NMOS area of described Semiconductor substrate 100 is formed the first mask layer 401, with described first mask layer 401 for mask, the second ion implantation is carried out to the second fin 120 in described PMOS area, in described second fin 120, form the second break-through barrier layer 502.
Concrete, the ion of described second ion implantation is N-type ion, such as: P ion, As ion or Sb ion etc., the Implantation Energy of described N-type ion is 20KeV ~ 60KeV, and in the described second break-through barrier layer 502 of formation, the doping content of described N-type ion is 1E12atom/cm
3~ 5E13atom/cm
3.Described second break-through barrier layer 502 can form PN junction with the follow-up source electrode formed in described second fin 120 with draining, thus forms reverse isolation between described source electrode and drain electrode, improves the punch through voltage between described source electrode and drain electrode.
The ion of described second ion implantation can also comprise F ion, described F ion can substitute in described second fin 120 due to defective locations that ion implantation causes, and the diffusion of described Doped ions mainly relies on the defect in described second fin 120, described, F ion can stop Doped ions in described second break-through barrier layer 502 to outdiffusion, thus can guarantee that the Doped ions distribution on described second break-through barrier layer 502 is comparatively concentrated.The doping content of described F ion is 1E12atom/cm
3~ 5E14atom/cm
3.
Further, the sidewall surfaces of described second fin 120 is formed with resilient coating 301, and described resilient coating 301 can also stop that the Doped ions in described second break-through barrier layer is outwards diffused in layer of dielectric material 302 by the sidewall of the second fin 120.
In other embodiments of the invention, described second ion implantation is at high temperature carried out, and the temperature of described second ion implantation is 300 DEG C ~ 400 DEG C, under described hot conditions, carry out the second ion implantation, described second ion implantation can be reduced damage is caused to described second fin 120.
In the process of described second ion implantation; described second fin 120 top has the first silicon oxide layer 201 and silicon nitride layer 202 as protective layer; the top of described second ion implantation to the second fin 120 is avoided to avoid causing damage; affect the interface quality between the grid structure of follow-up formation on described second fin 120 and the second fin 120, thus improve the performance of the fin formula field effect transistor formed.
Please refer to Fig. 8, the PMOS area of described Semiconductor substrate 100 is formed the second mask layer 402, with described second mask layer 402 for mask, the first ion implantation is carried out to the first fin 110 in described PMOS area, in described first fin 110, form the first break-through barrier layer 501.
Concrete, the ion of described first ion implantation is P type ion, such as: B ion, Ga ion or In ion etc., the Implantation Energy of described P type ion is 20KeV ~ 60KeV, and in the described first break-through barrier layer 501 of formation, the doping content of described P type ion is 1E12atom/cm
3~ 5E13atom/cm
3.Described first break-through barrier layer 501 can form PN junction with the follow-up source electrode formed in described first fin 110 with draining, thus forms reverse isolation between described source electrode and drain electrode, improves the punch through voltage between described source electrode and drain electrode.The position on described first break-through barrier layer 501 is identical or close with the position on the second break-through barrier layer.
The ion of described first ion implantation can also comprise C ion, described C ion can adsorb in described first fin 110 due to defect that ion implantation causes, the discrete defect in described first fin 110 is made to form cluster, thus the diffusion rate of the Doped ions in described first break-through barrier layer 501 can be reduced, avoid described Doped ions to outdiffusion, thus can guarantee that the Doped ions distribution on described first break-through barrier layer 501 is comparatively concentrated.The doping content of described C ion is 1E12atom/cm
3~ 5E14atom/cm
3.
Further, the sidewall surfaces of described first fin 110 is formed with resilient coating 301, and described resilient coating 301 can also stop that the Doped ions in described first break-through barrier layer 501 is outwards diffused in layer of dielectric material 302 by the sidewall of the first fin 121.
In other embodiments of the invention, described first ion implantation is at high temperature carried out, and the temperature of described first ion implantation is 300 DEG C ~ 400 DEG C, under described hot conditions, carry out the first ion implantation, described first ion implantation can be reduced damage is caused to described first fin 110.
In the process of described first ion implantation; described first fin 110 top has the first silicon oxide layer 201 and silicon nitride layer 202 as protective layer; the top of described first ion implantation to the first fin 110 is avoided to avoid causing damage; affect the interface quality between the grid structure of follow-up formation on described first fin 110 and the first fin 110, thus improve the performance of the fin formula field effect transistor formed.
After the good described first break-through barrier layer 501 of formation and the second break-through barrier layer 502, carry out thermal anneal process to activate the Doped ions in described first break-through barrier layer and the second break-through barrier layer, the temperature of described annealing in process is 500 DEG C ~ 1000 DEG C, and described annealing process can be furnace anneal, rapid thermal annealing or spike annealing process.
In the present embodiment, after described first fin 110 and the second fin 120 surface form described resilient coating 301 and layer of dielectric material 302, form described first break-through barrier layer 501 and the second break-through barrier layer 502 again, the heat treatment process that described first break-through barrier layer 501 and the second break-through barrier layer 502 are subject to can be reduced.
Because described resilient coating 301 is formed by thermal oxidation or atom layer deposition process, technological temperature is higher, if before described resilient coating 301 is formed, just in described first fin and the second fin, carry out ion implantation, form described first break-through barrier layer and the second break-through barrier layer, so in the process forming described resilient coating 301, Doped ions in described first break-through barrier layer and the second break-through barrier layer will in the forming process of resilient coating 301, outwards diffuse in resilient coating 301 and other materials layer and make to there is more defect in described resilient coating 301, reduce the diffusion barrier effect to the first break-through barrier layer and the second break-through barrier layer in subsequent process of described resilient coating 301, in follow-up formation layer of dielectric material 302 process, also to heat-treat to remove the defect in described layer of dielectric material 302 to described layer of dielectric material 302, because the diffusion barrier effect of resilient coating 301 declines, can promote further that Doped ions in the first break-through barrier layer and the second break-through barrier layer is to outdiffusion.
And in embodiments of the invention, after the described resilient coating 301 of formation and layer of dielectric material 302, form the first break-through barrier layer 501 and the second break-through barrier layer 502 again, the quality of the resilient coating 301 of formation can be improved on the one hand, improve the diffusion barrier effect to the Doped ions in the first break-through barrier layer 501 and the second break-through barrier layer 502 in subsequent technique of described resilient coating 301; On the other hand, the Doped ions in described first break-through barrier layer 501 and the second break-through barrier layer 502 does not need to be subject to forming the heat treatment process in described resilient coating and layer of dielectric material process, thus can reduce the diffusion of Doped ions.
Please refer to Fig. 9, remove the layer of dielectric material 302(of segment thickness and please refer to Fig. 8) and portion of buffer layer 301(please refer to Fig. 8), the surface of described layer of dielectric material 302 is flushed or a little less than the surface on described first break-through barrier layer 502, break-through barrier layer 501, second with the surface on the first break-through barrier layer 502, break-through barrier layer 501, second.
Wet-etching technology or wet-etching technology can be adopted to remove layer of dielectric material 302 and the portion of buffer layer 301 of described segment thickness.
In one embodiment of the invention, can using described first fin 110 and the silicon oxide layer 201 at the second fin 120 top and the silicon nitride layer 202 on surface thereof as mask, adopt dry etch process to etch described layer of dielectric material 302 and resilient coating 301, then remove the silicon nitride layer 202 at described silicon oxide layer 201 and top thereof.
Concrete, in the present embodiment, adopt wet-etching technology, with layer of dielectric material 302 described in HF solution etches and resilient coating 301, the surface of remaining layer of dielectric material 302a and resilient coating 301a is flushed or a little less than the surface on described first break-through barrier layer 502, break-through barrier layer 501, second with the surface on the first break-through barrier layer 502, break-through barrier layer 501, second.Adopt wet-etching technology that dry etch process can be avoided to cause damage to the first fin 110 and the second fin 120 surface.
After the layer of dielectric material 302 removing described segment thickness and portion of buffer layer 301, expose the first fin 110 and the second fin 120 of Partial Height, the first fin 110 of the follow-up Partial Height in described exposure and the second fin 120 surface form grid structure and are positioned at the first fin 110 of described grid structure both sides and the source electrode of the second fin 120 and drain electrode.Described first break-through barrier layer 501 is positioned at the bottom of the first fin 110 of the Partial Height of exposure, described second break-through barrier layer 502 is positioned at the bottom of the second fin 120 of the Partial Height of exposure, thus described first break-through barrier layer 501 is connected with the position of the follow-up source electrode that formed in the first fin 110 and drain electrode, thus PN junction can be formed with described source electrode and drain electrode, as the isolation structure between described source electrode, drain electrode; Equally, described second break-through barrier layer 502 also can as the isolation structure between the source electrode formed in the second fin 120 and drain electrode.
Please refer to Figure 10, the silica removing described first fin 110 and the second fin 120 top once 201 and silicon nitride layer 202 after, surface smoothing process and fillet process are carried out to part first fin 110 do not covered by layer of dielectric material 302 and the second fin 120.
Concrete, the method of the first fin 110 of described exposure and the second fin 120 being carried out to surface smoothing process and fillet process can comprise: carry out oxidation processes at described the first fin of not exposed by the part that dielectric layer covers and the second fin portion surface, form oxide layer; Wet-etching technology is adopted to remove described oxide layer.The technique of the first fin of described exposure and the second fin portion surface being carried out to oxidation processes can be thermal oxidation or steam oxidation technique; The etching solution that described wet-etching technology adopts is HF solution.
After described first fin 110 and the second fin 120 surface are oxidized, the drift angle that can make described first fin 110 and the second fin 120 is arc-shaped, thus the corner position place electric field line density of described first fin 110 and the second fin 120 is excessive after avoiding the formation of transistor occurs point discharge phenomenon, thus the stability of the fin formula field effect transistor of formation can be improved.And, in removal oxide layer after being oxidized described first fin 110 and the second fin 120 surface, the damage that described first fin 110 and the second fin 120 surface are subject in etching process can be removed, it is the surface more smooth of described first fin 110 and the second fin 120, improve the follow-up interface quality forming grid structure on described first fin 110 and the second fin 120, reduce the problems such as electric leakage of the grid, improve the performance of the fin formula field effect transistor formed further.
Follow-uply first grid structure be can form in the first fin 110 surface after described smoothing processing and corners process, and in the first fin of described first grid structure both sides, the first source electrode and the first drain electrode formed; Form second grid structure on described second fin 120 surface, and in the second fin of described second grid structure both sides, form the second source electrode and the second drain electrode; Described first grid structure and second grid structure can be formed simultaneously.
In sum, in embodiments of the invention, described Semiconductor substrate 100 is formed the first fin 110 and the second fin 120, and after described first fin 110, second fin 110 and Semiconductor substrate 100 surface form dielectric layer, second ion implantation is carried out to described second fin 120, form the second break-through barrier layer 502, the first ion implantation is carried out to the first fin 110, form the first break-through barrier layer 501.In the present embodiment, described first break-through barrier layer 501 and the second break-through barrier layer 502 is formed again after described first fin 110 and the second fin 120 surface form described resilient coating 301 and layer of dielectric material 302, the quality of the resilient coating 301 of formation can be improved on the one hand, improve the diffusion barrier effect to the Doped ions in the first break-through barrier layer 501 and the second break-through barrier layer 502 in subsequent technique of described resilient coating 301; On the other hand, the Doped ions in described first break-through barrier layer 501 and the second break-through barrier layer 502 does not need to be subject to forming the heat treatment process in described resilient coating 301 and layer of dielectric material 302 process, thus can reduce the diffusion of Doped ions.
Further, described first ion implantation and the second ion implantation are at high temperature carried out, the temperature of described injection is 300 DEG C ~ 400 DEG C, under described hot conditions, carry out the first ion implantation and the second ion implantation, the damage that described first ion implantation and the second ion implantation cause described first fin 110 and the second fin 120 can be reduced.
The ion of described first ion implantation can also comprise C ion, and described C ion can adsorb the defect in the first fin; The ion of the second ion implantation can also comprise F ion, and described F ion can substitute in described second fin due to defective locations that ion implantation causes; And the diffusion of described Doped ions mainly relies on the defect in described first fin 110 and the second fin 120, described, B ion and F ion can stop Doped ions in described first break-through barrier layer 501 and the second break-through barrier layer 502 to outdiffusion, thus can guarantee that the Doped ions distribution in described first break-through barrier layer 501 and the second break-through barrier layer 502 is comparatively concentrated.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (19)
1. a formation method for fin formula field effect transistor, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises NMOS area and PMOS area;
Etch described Semiconductor substrate, form the first fin in NMOS area, form the second fin in PMOS area;
Dielectric layer is formed on the surface of described Semiconductor substrate, the first fin and the second fin, described dielectric layer comprises the resilient coating on the surface being positioned at Semiconductor substrate, the first fin and the second fin and is positioned at the layer of dielectric material of described buffer-layer surface, and the surface of described dielectric layer flushes with the top of the first fin and the second fin;
Second ion implantation is carried out to described second fin, in described second fin, forms the second break-through barrier layer;
First ion implantation is carried out to described first fin, in described first fin, forms the first break-through barrier layer;
Remove the dielectric layer of segment thickness, the surface of described dielectric layer is flushed with the surface on the first break-through barrier layer, the second break-through barrier layer or lower than the surface on described first break-through barrier layer, the second break-through barrier layer.
2. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, the temperature of described first ion implantation and the second ion implantation is 300 DEG C ~ 400 DEG C.
3. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, the ionic type of described second ion implantation is N-type ion, and in the described second break-through barrier layer of formation, the doping content of described N-type ion is 1E12atom/cm
3~ 5E15atom/cm
3.
4. the formation method of fin formula field effect transistor according to claim 3, is characterized in that, the ion of described second ion implantation is P ion.
5. the formation method of fin formula field effect transistor according to claim 3, is characterized in that, the ion of described second ion implantation also comprises F ion.
6. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, the ionic type of described first ion implantation is P type ion, and in the described first break-through barrier layer of formation, the doping content of described P type ion is 1E12atom/cm
3~ 5E15atom/cm
3.
7. the formation method of fin formula field effect transistor according to claim 6, is characterized in that, the ion of described first ion implantation is B ion.
8. the formation method of fin formula field effect transistor according to claim 6, is characterized in that, the ion of described first ion implantation also comprises C ion.
9. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, the temperature of heat-treating described dielectric layer is 500 DEG C ~ 1500 DEG C.
10. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, described dielectric layer comprises the resilient coating being positioned at described Semiconductor substrate, the first fin and the second fin portion surface and the layer of dielectric material being positioned at described buffer-layer surface.
The formation method of 11. fin formula field effect transistors according to claim 10, is characterized in that, the material of described resilient coating is silicon oxynitride or silica.
The formation method of 12. fin formula field effect transistors according to claim 10, is characterized in that, the formation method of described resilient coating is thermal oxidation technology or atom layer deposition process.
The formation method of 13. fin formula field effect transistors according to claim 1, is characterized in that, described first fin and the second fin top have mask layer.
The formation method of 14. fin formula field effect transistors according to claim 13, is characterized in that, the material of described mask layer is silicon nitride.
The formation method of 15. fin formula field effect transistors according to claim 13, is characterized in that, after removing the dielectric layer of segment thickness, removes described mask layer.
The formation method of 16. fin formula field effect transistors according to claim 1, it is characterized in that, also comprise: after the good described first break-through barrier layer of formation and the second break-through barrier layer, carry out the Doped ions in the thermal anneal process described first break-through barrier layer of activation and the second break-through barrier layer.
The formation method of 17. fin formula field effect transistors according to claim 1, is characterized in that, the temperature of described annealing in process is 500 DEG C ~ 1000 DEG C.
The formation method of 18. fin formula field effect transistors according to claim 1, is characterized in that, also comprise: after removing the dielectric layer of segment thickness, carry out surface smoothing process and fillet process to part first fin do not covered by dielectric layer and the second fin.
The formation method of 19. fin formula field effect transistors according to claim 18, it is characterized in that, the method of the first fin of described exposure and the second fin being carried out to surface smoothing process and fillet process comprises: carry out oxidation processes at described the first fin of not exposed by the part that dielectric layer covers and the second fin portion surface, form oxide layer; Wet-etching technology is adopted to remove described oxide layer.
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