CN104779285A - FINFET (Fin Field Effect Transistor) semiconductor device and manufacturing method thereof - Google Patents

FINFET (Fin Field Effect Transistor) semiconductor device and manufacturing method thereof Download PDF

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CN104779285A
CN104779285A CN201410011019.6A CN201410011019A CN104779285A CN 104779285 A CN104779285 A CN 104779285A CN 201410011019 A CN201410011019 A CN 201410011019A CN 104779285 A CN104779285 A CN 104779285A
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fin
layer
finfet
region
stack
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CN104779285B (en
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赵猛
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts

Abstract

The invention mainly relates to a FINFET (Fin Field Effect Transistor) device, and particularly relates to a FINFET semiconductor device with stacked-type fins and a manufacturing method thereof, so as to enhance gate control and current driving abilities. The FINFET semiconductor device comprises a substrate, the stacked fins located on the substrate and gate structures surrounding two sides and above the stacked-type fins, wherein the stacked fins comprise a hourglass lower fin and a trapezoidal or square upper fin located above the lower fin.

Description

FINFET semiconductor device and preparation method thereof
Technical field
The present invention relates generally to FINFET semiconductor device, or rather, relates to a kind of FINFET semiconductor device with stack fin and preparation method thereof, controls and current driving ability to strengthen grid.
Background technology
Maintain low cost along with semiconductor device and there is the demand of higher competitiveness performance, in device the density of transistor unit increasing always and the overall dimensions of device but reduction, for mos field effect transistor (MOSFET), along with reducing of overall device size, some less desirable negative effects are also following, for example when raceway groove narrows down to certain value (such as lower than 100nm), distance between source area and drain region is corresponding shortening also, very easily bring short-channel effect, grid is cut down the control ability of raceway groove, the difficulty of grid pinch off raceway groove increases, negative sub-threshold leakage phenomenon also more easily produces.Based on the defect that the transistor of conventional planar is intrinsic, fin-shaped field effect transistor (Fin Field Effect Transistor, FinFET) is extensively adopted by industry and overcomes an aforementioned difficult problem.Normally all form grid structure at the top of fin and both sides, improve grid control ability.
When semiconductor industry think 22nm or following technology node send out drive on boldly time, a challenge is how FinFET has less size and the drive current of Geng Gao, especially desirable to provide having the FinFET being subject to stress factors impact, such as suitable employing stress material draws stress in raceway groove to strengthen the mobility of charge carrier to lure.But existing FinFET manufacturing capacity obviously cannot meet such technical requirement.The detailed description follow-up by the present invention and appended claim, in conjunction with the graphic and prior art that the present invention is adjoint, the characteristic sum scheme that the present invention discloses will become clear.
Summary of the invention
In one embodiment, FinFET semiconductor device, comprising: a substrate and the stack fin being positioned at substrate; Be centered around the grid structure of stack fin both sides and top; Wherein said stack fin comprises a hourglass-shaped bottom fin and is positioned at the top fin of the trapezoidal shape on the fin of bottom.
Above-mentioned FinFET semiconductor device, be Si material one of in both described upper and lower fins, another one is SiGe material.
Above-mentioned FinFET semiconductor device, described substrate comprises a base substrate and is positioned at the buried insulator layer on base substrate, and described stack fin is arranged on above buried insulator layer.
Above-mentioned FinFET semiconductor device, be positioned at the stack fin of grid structure both sides, its both sides and top are provided with source/drain epitaxial region.
Above-mentioned FinFET semiconductor device, the source/drain epitaxial region of N-type FinFET comprises the SiC epitaxial region of elongation strain, and the source/drain epitaxial region of P type FinFET comprises the SiGe epitaxial region of compression strain.
In another embodiment of the invention, FinFET semiconductor device, comprising: a substrate and the stack fin being positioned at substrate; Be centered around the grid structure of stack fin both sides and top; Wherein said stack fin comprises a hourglass-shaped bottom fin and is positioned at the top fin of the square shape on the fin of bottom.
In the preparation method of a kind of FinFET semiconductor device of the present invention, comprise the following steps: the substrate that comprises first, second semiconductor layer is provided; Etch the first semiconductor layer and form top fin; Etch region that the second semiconductor layer do not cover by top fin to form the hour-glass in shape bottom fin below the fin of top; Formed to be centered around and comprise top, the stack fin both sides of bottom fin and the grid structure of top.
Above-mentioned method, is formed in the step of top fin, on the first semiconductor layer square one-tenth one hard mask layer this hard mask layer of patterning; The region utilizing hard mask layer dry etching first semiconductor layer with opening figure to expose, forms the groove that the degree of depth in the first semiconductor layer is less than the first semiconductor layer original thickness; Utilize hard mask layer along described groove with anisotropic wet etch first semiconductor layer, thus form up-narrow and down-wide trapezoidal shape top fin.
Above-mentioned method, is formed in the step of bottom fin, carries out anisotropic wet etching to the region that the second semiconductor layer exposes, and the width forming top and bottom is greater than the hourglass-shaped bottom fin of pars intermedia width.
Above-mentioned method, is formed in the step of bottom fin, first utilizes hard mask layer dry etching second semiconductor layer, form the bottom fin with vertical sidewall pattern; Then carry out anisotropic wet etching to the sidewall that bottom fin exposes, the width forming top and bottom is greater than the hourglass-shaped bottom fin of pars intermedia width.
Said method, is formed in the step of top fin, utilizes hard mask layer dry etching first semiconductor layer, thus forms the top fin with vertical sidewall pattern; The inwall of the opening then in hard mask layer, the sidewall of top fin and covering one sacrifice side wall layer on the end face of hard mask layer; Eat-back sacrifice side wall layer and form the sacrifice side wall covered on the sidewall of opening inwall and top fin; Sacrifice side wall and hard mask layer is utilized to etch formation bottom, the region fin of the second semiconductor layer exposure.
Above-mentioned method, is formed in the step of bottom fin, carries out anisotropic wet etching to the region that the second semiconductor layer exposes, and the width forming top and bottom is greater than the hourglass-shaped bottom fin of pars intermedia width.
Above-mentioned method, is formed in the step of bottom fin, first utilizes hard mask layer and sacrifices side wall dry etching second semiconductor layer, form the bottom fin with vertical sidewall pattern; Then carry out anisotropic wet etching to the sidewall that bottom fin exposes, the width forming top and bottom is greater than the hourglass-shaped bottom fin of pars intermedia width.
Above-mentioned method, after forming grid structure, is that autoregistration mask injects light dope source/drain region at the upper surface of top fin with grid structure; And then on the sidewall of grid structure, form side wall, and implant source electrode/drain electrode doped area in the stack fin of grid structure both sides.
Above-mentioned method, is formed after grid structure, the both sides of the stack fin in grid structure both sides and above optionally epitaxial growth source/drain epitaxial region.Above-mentioned method, N-type FinFET epitaxially grown source/drain epitaxial region comprise the SiC epitaxial region of elongation strain, P type FinFET epitaxially grown source/drain epitaxial region comprise the SiGe epitaxial region of compression strain.
Accompanying drawing explanation
Read following detailed description also with reference to after the following drawings, Characteristics and advantages of the present invention will be apparent:
Fig. 1 shows the top epitaxial layer and bottom epitaxial layer that arrange in base substrate.
Fig. 2 ~ 5 show the flow chart that etching top epitaxial layer forms the top fin of inverted trapezoidal.
Fig. 6 A ~ 6B is that etching bottom epitaxial loayer is to prepare the schematic diagram of hourglass-shaped bottom fin.
Fig. 7 is the birds-eye view of stack fin comprising top, bottom fin.
Fig. 8 is the flow chart preparing gate insulator and grid material on stack fin and buried insulator layer.
Fig. 9 is the schematic flow sheet that grid structure prepared by patterned grid insulating layer and grid material.
Figure 10 is the schematic diagram forming side wall in the both sides of grid structure.
Figure 11 is the schematic diagram of selective epitaxial growth source/drain epitaxial region.
Figure 12 A shows etching top epitaxial layer and forms the method with the top fin of vertical sidewall.
Figure 12 B ~ 12C prepares the method for sacrificing side wall.
Figure 12 D ~ 12F sacrifices side wall and hard mask layer to carry out etching bottom epitaxial loayer as mask and form bottom fin.
Figure 12 G is the schematic flow sheet that grid structure prepared by patterned grid insulating layer and grid material.
Figure 12 H is the schematic diagram of selective epitaxial growth source/drain epitaxial region.
Embodiment
Fig. 1 illustrates a typical silicon-on-insulator (Silicon-On-Insulator, SOI) wafer, buried insulator layer 102 is provided with above a base substrate 101, a such as buried oxide layer, and also there is successively from the bottom to top one deck bottom epitaxial layer 103 and one deck top epitaxial layer 104 of formation above buried insulator layer 102, epitaxial loayer 104,103 is corresponding to the first semiconductor layer of in buried insulator layer 102 and second semiconductor layer respectively.Exemplarily, in some optional execution modes, such as, bottom epitaxial layer 103 is Si material epitaxial loayers, and top epitaxial layer 104 can be GeSi material, or bottom epitaxial layer 103 is GeSi material epitaxial loayers, and top epitaxial layer 104 can be Si material etc.In fig. 2, a preparation hard mask layer 105 in advance, cover above top epitaxial layer 104, wherein hard mask layer 105 can be single layer structure, and such as typical SiN etc., also can be the lamination layer structures containing multilayer.Must it is emphasised that, wafer here not necessarily is SOI wafer, in other execution modes, SOI wafer can also by not containing any buried insulator layer pure silicon substrate substitute.
As shown in figs. 34, utilize conventional photoetching process, patterned hard mask layer 105 forms opening figure wherein, the opening 105a such as etched in hard mask layer 105.And then utilize hard mask layer 105 as an etch mask, dry etching is carried out to the region that the top epitaxial layer 104 below it exposes, form groove 104a, notice that this etching terminates in top epitaxial layer 104 and do not have etching to run through its whole thickness, so the degree of depth of groove 104a is less than the original thickness of top epitaxial layer 104.Then continue to utilize hard mask layer 105 as etch mask, anisotropic wet etch technique is implemented along groove 104a, etching top epitaxial layer 104 is exposed to the region in groove 104a, due to the existence of groove 104a and the anisotropic etch of follow-up execution, along groove 104a by top epitaxial layer 104 etching run through after, just can define the top fin 104' of multiple strip, it is rendered as up-narrow and down-wide trapezoidal shape structure substantially.Multiple top fin 104' is arranged in parallel to each other, adjacent upper fin 104' is separated and disconnects by the etching groove running through top epitaxial layer 104 thickness between the fin 104' of top, notice that the sidewall of top fin 104' now has the pattern on inclined plane, to be up-narrow and down-wide be the vertical section of top fin 104' because etch step defines undercutting below hard mask layer 105, by the respective a part of region of the corner part compared with top of fin 104' both sides, top to having removed.General Requirements, when etching top epitaxial layer 104, the material of bottom epitaxial layer 103 can resist the etching technics performed top epitaxial layer 104, and not by the impact of this etch step.
Fig. 6 A ~ 6B is the schematic diagram of further etching bottom epitaxial loayer 103, now hard mask layer 105 together with the fin 104' of top as etch mask, the region that bottom epitaxial layer 103 is exposed is etched away, and to form final vertical section be hourglass-shaped bottom fin 103'.In fig. 6, the vertical sidewall of bottom fin 103' is first first formed via isotropic etching bottom epitaxial layer 103, such as dry etching, then anisotropic etching is adopted, etch on the vertical sidewall of bottom fin 103' as utilized wet etching and form groove recessed to the inside, the existence of groove causes the sidewall of bottom fin 103' have opposed vertical direction and be rendered as the upper side wall 103'a on inclined plane and the lower wall 103'b on inclined plane.Set the narrowest compared with pars intermedia of hourglass-shaped bottom fin 103', then in the vertical direction, pars intermedia is continuous progressively to increase the mode of width and top and bottom respectively up and down.Upper side wall 103'a, lower wall 103'b are <110> crystal face or <111> crystal face, can determine according to the crystal orientation <100> crystal face of bottom epitaxial layer 103 end face, the <100> crystal face of upper side wall 103'a, lower wall 103'b, can determine according to the crystal orientation <110> crystal face of bottom epitaxial layer 103 end face.In this step, the impact that buried insulator layer 102 is not etched, and after the top fin 104' forming trapezoidal shape and hourglass-shaped bottom fin 103', also need hard mask layer 105 corrosion to peel off.
In other embodiment, using hard mask layer 105 and top fin 104' as mask, do not adopt dry etching and directly adopt anisotropic wet etching to etch the region that bottom epitaxial layer 103 exposes, do not form the vertical sidewall of the transition of bottom fin 103', but the inclined plane directly formed on sidewall and upper side wall 103'a and lower wall 103'b, such sidewall can be referred to as again Σ shape sidewall, is namely directly performed the step of Fig. 6 B by the step of Fig. 5.Thus bottom epitaxial layer 103 nationality defines the bottom fin 103' of multiple strip by etching, they are separated and disconnect by the etching groove running through whole bottom epitaxial layer 103 thickness between adjacent lower fin 103', these bottoms fin 103' general parallel orientation spread configuration to each other.When etching bottom epitaxial loayer 103, the material of top epitaxial layer 104 can resist the etching technics performed bottom epitaxial layer 103, and not by the impact of this etch step.
The birds-eye view of vertical section figure and Fig. 7 of Fig. 6 B well illustrates many stack fins 150 arranged that are arranged parallel to each other.Stack fin 150 comprises bottom fin 103' and is stacked on the top fin 104' directly over the fin 103' of bottom, fin 104', 103' are corresponding to first fin and second fin respectively, and these stack fins 150 are all positioned at above buried insulator layer 102.In the FinFET of known technology, fin ray is all generally mono-material, and to be common in sectional elevation be in the structure of rectangle, and the stack fin 150 of Fig. 7 of the present invention is composite bed, the material of different layers can also be different, this is to considering that the effect that the useful stress engineering of raceway groove displays relative to known technology is that milli is unsuspecting, and subsequent content is introduced in detail by continuing.
In fig. 8, continue to cover one deck gate insulator 106 at the top of each stack fin 150 and both sides, such as in an oxidizing environment thermal oxidation stack fin 150 and generate oxide, the classification of oxide depends on the material of top epitaxial layer 104 and bottom epitaxial layer 103, as silicon dioxide or germanium dioxide etc.Gate insulator 106 can also be the silica, silicon nitride etc. of Direct precipitation, or for example contour dielectric constant insulation thing of HfSiO, and gate insulator 106 also covers buried insulator layer 102 simultaneously and is not stacked on the region that formula fin 150 covers.In fig. 8, thereafter also need again in gate insulator 106 disposed thereon one deck gate material layers 107, gate material layers 107 is electric conducting material, typically comprise for example polysilicon, one or more layers metal material, or their combination etc., consider the gap width between adjacent stacks formula fin 150 along with device size reduce also be tending towards reducing, so gate material layers 107 is wanted in the flawless gap be filled between adjacent stacks formula fin 150, such as there is no cavity, just must manage the high-aspect-ratio reducing gap, the height of bottom fin 103' and top fin 104' can be adjusted in the present invention, we generally set the thickness of bottom epitaxial layer 103 and top epitaxial layer 104 between 6nm ~ 20nm.
In fig .9, with the gate mask etching grid material layer 107 do not illustrated and gate insulator 106, form the grid structure 160 being centered around each stack fin 150 both sides and top, grid structure 160 comprises the gate insulation layer 106' come via gate insulator 106 patterning, with the grid 107' comprised via gate material layers 107 patterning, grid 107' is superimposed upon above gate insulation layer 106'.In certain embodiments, the length bearing of trend of the grid structure 160 of strip is orthogonal to the length direction of each stack fin 150.Now the channel region of FinFET to comprise in every bar stack fin 150 coated and around the part of living by grid structure 160, opposite planar type MOSFET, three sides of the channel region of FinFET are subject to the control of grid structure 160, enhance the ability of drive current undoubtedly.Especially, according to the invention spirit of the application, on the one hand, the groove be inwardly recessed that the sidewall of bottom fin 103' etches, be equivalent to the area of this fin both sides sidewall can be made to be increased, on the other hand, in the trapezium structure of top fin 104', although make the top surface area of top fin 104' slightly reduce, the area that the area that its both sides sidewall increases reduces considerably beyond end face.Take this to increase in stack fin 150 effective channel width of channel region of enveloping by grid structure 160, do not increasing under transistor unit size condition, relate to Current Control this factor of channel width-over-length ratio be improved significantly, this is that those skilled in the art find pleasure in and see that it becomes.
In some embodiments, can after formation grid mechanism 160, implement light dope source/drain region (Lightly dopeddrain, LDD) operation, without the need to providing extra ion implantation mask, can directly utilize grid structure 160 for autoregistration mask and top fin 104' upper surface inject light dope source/drain region (not illustrating), in order to form light dope source/drain region and the relatively light alloy of doping content is implanted to the upper surface of the top fin 104' being arranged in grid mechanism 160 both sides, the better implantation arsenic ion of N raceway groove FinFET, the better boron implant ion of P raceway groove FinFET.Afterwards, side wall 108 is formed again on the sidewall of grid structure 160 both sides, as shown in Figure 10, the step forming side wall 108 first can deposit side wall cover layer to cover on the exposed region of grid structure 160, stack fin 150 and buried insulator layer 102, then eat-backs side wall cover layer to be fallen by unwanted region etch and only to retain the side wall 108 on grid structure 160 sidewall.Finally, the exposed stack fin 150a out being arranged in grid structure 160 side is also needed to inject heavily doped source doping region, inject heavily doped drain doping region with in the exposed stack fin 150b out of grid structure 160 opposite side, their doping content is more much bigger than LDD district.
In the execution mode of Figure 10, the also optionally epitaxial growth for example source electrode epitaxial region 109a and drain epitaxial district 109b in grid structure 160 both sides, noticing that this epitaxial step is not that arbitrary region above buried insulator layer 102 all grown epitaxial region, is only optionally start growing epitaxial district 109a, 109b on stack fin 150a, 150b of grid structure 160 both sides.See Figure 10 ~ 11, the source electrode epitaxial region 109a grown being positioned at grid structure 160 side is centered around both sides and the top of the stack fin 150a being positioned at this homonymy of grid structure 160, and the drain epitaxial district 109b grown being positioned at the relative opposite side of grid structure 160 is then centered around both sides and the top of each stack fin 150b being positioned at grid structure 160 opposite side.Optional but in the execution mode be not restricted at some, the FinFET of N-type raceway groove epitaxially grown source/drain epitaxial region 109a, 109b comprise the SiC epitaxial region of tool elongation strain ability, the FinFET of P type raceway groove epitaxially grown source/drain epitaxial region 109a, 109b comprise the SiGe epitaxial region of tool compression strain, change the mobility of charge carrier.
The method flow of Figure 12 A ~ 12H is a kind of embodiment replacing trapezoidal top fin with the top fin of rectangle.In fig. 12, utilize conventional photoetching process, patterned hard mask layer 105 forms opening figure wherein, such as, etch the opening 105a in hard mask layer 105, and then utilize hard mask layer 105 as an etch mask, the top epitaxial layer 104 below it is etched.Dry etching top epitaxial layer 104, thus the region that top epitaxial layer 104 is exposed in opening 105a will be etched away, top epitaxial layer 104 defines the top fin 104' of multiple strip, their general parallel orientation arrangements to each other, they are separated and disconnect by the etching groove running through top epitaxial layer 104 between adjacent upper fin 104', and attention top fin 104' now has the sidewall profile of less perpendicular.When etching top epitaxial layer 104, the material of bottom epitaxial layer 103 can resist the etching technics performed top epitaxial layer 104, and not by the impact of this etch step.Then deposit one deck and sacrifice side wall layer 110, as shown in Figure 2 B, side wall layer 110 is typical in silicon dioxide or silicon nitride etc., now sacrificing side wall layer 110 covers on the end face of hard mask layer 105, with be attached on the inwall of opening 105a, on the sidewall being also attached to top fin 104' and cover bottom epitaxial layer 103 and not covered by top fin 104' and on exposed upper surface, isotropism returns etches sacrificial side wall layer 110 afterwards, sacrifice side wall layer 110 etching covered on the end face of hard mask layer 105 and on the end face of bottom epitaxial layer 103 is removed, as indicated in fig. 12 c.Sacrifice side wall layer 110 and only retain formed sacrifice side wall 110' after etching, on its inwall being attached to opening 105a and on the sidewall of top fin 104'.As shown in Figure 12 D ~ 12E, utilize and sacrifice side wall 110', top fin 104' and hard mask layer 105 as mask, etching bottom epitaxial loayer 103 by the region that top fin 104' or sacrifice side wall 110' covers and exposes, does not form bottom fin 103'.
In one embodiment, bottom fin 103' can first form its vertical sidewall via isotropic etching bottom epitaxial layer 103, as Figure 12 D, then anisotropic etching is adopted, on the vertical sidewall of bottom fin 103', etching forms groove recessed to the inside, as Figure 12 E, the existence of groove causes the sidewall of bottom fin 103' have opposed vertical direction and be rendered as the upper side wall 103'a on inclined plane and the lower wall 103'b on inclined plane.In this step, the impact that buried insulator layer 102 is not etched, and after formation rectangular-shaped top fin 104' and hourglass-shaped bottom fin 103', need hard mask layer 105 and sacrifice side wall 110' to peel off to remove, as shown in Figure 12 F.In other embodiment, using hard mask layer 105, top fin 104' and sacrifice side wall 110' as mask, do not adopt dry etching and directly adopt anisotropic wet etching to etch the region that bottom epitaxial layer 103 exposes, do not form the vertical sidewall of the transition of bottom fin 103', but the inclined plane directly formed on sidewall and upper side wall 103'a and lower wall 103'b, such sidewall can be referred to as again Σ shape sidewall.Thus bottom epitaxial layer 103 nationality defines the bottom fin 103' of multiple strip by etching, they are separated and disconnect by the etching groove running through whole bottom epitaxial layer 103 thickness between adjacent lower fin 103', these bottoms fin 103' general parallel orientation spread configuration to each other.When etching bottom epitaxial loayer 103, whether the material of top epitaxial layer 104 can resist the etching technics performed bottom epitaxial layer 103 becomes and recedes into the background, because it is subject to hard mask layer 105 and sacrifices the protection of side wall 110' always.
The method step of Figure 12 G ~ 12H is basic substantially identical with the step of Fig. 8 ~ 11, therefore repeats no more.But it should be noted that, with the difference that Fig. 8 ~ 11 are maximum be, in the FinFET of Figure 12 G ~ 12H, the vertical section of top fin 104' has been no longer up-narrow and down-wide trapezoidal, its section is but equal square of about one width, and stack fin 150 now comprises a hourglass-shaped bottom fin 103' and be positioned at the top fin 104' of the square shape on the fin 103' of bottom.Be easy to learn from the step of Figure 12 A ~ 12F; the sidewall profile that top fin 104' has a less perpendicular is subject to the protection of sacrificing side wall 110' in subsequent step always; its sidewall can't be corroded out Σ connected in star, so the square structure of top fin 104' is kept.
In some embodiments, the corrosive liquid of alkalescence is used to etch the sidewall forming the reeded Σ shape of band, such as, preparing bottom fin 103' and top fin 104' Σ shape sidewall separately in the present invention, typically can adopting as contained Tetramethylammonium hydroxide (TMAH), or NH 4oH, or NaOH, or KOH, or the corrosive liquid etc. of ethylene diamine pyrocatechol (Ethylenediaminepyrocatechol, EDP).
Above, by illustrating and accompanying drawing, give the exemplary embodiments of the ad hoc structure of embodiment, foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.

Claims (16)

1. a FinFET semiconductor device, is characterized in that, comprising:
One substrate and the stack fin being positioned at substrate;
Be centered around the grid structure of stack fin both sides and top;
Wherein said stack fin comprises a hourglass-shaped bottom fin and is positioned at the top fin of the trapezoidal shape on the fin of bottom.
2. FinFET semiconductor device as claimed in claim 1, is characterized in that, be Si material one of in both described upper and lower fins, another one is SiGe material.
3. FinFET semiconductor device as claimed in claim 1, is characterized in that, described substrate comprises a base substrate and is positioned at the buried insulator layer on base substrate, and described stack fin is arranged on above buried insulator layer.
4. FinFET semiconductor device as claimed in claim 1, it is characterized in that, be positioned at the stack fin of grid structure both sides, its both sides and top are provided with source/drain epitaxial region.
5. FinFET semiconductor device as claimed in claim 4, it is characterized in that, the source/drain epitaxial region of N-type FinFET comprises the SiC epitaxial region of elongation strain, and the source/drain epitaxial region of P type FinFET comprises the SiGe epitaxial region of compression strain.
6. a FinFET semiconductor device, is characterized in that, comprising:
One substrate and the stack fin being positioned at substrate;
Be centered around the grid structure of stack fin both sides and top;
Wherein said stack fin comprises a hourglass-shaped bottom fin and is positioned at the top fin of the square shape on the fin of bottom.
7. a preparation method for FinFET semiconductor device, is characterized in that, comprises the following steps:
The substrate that one comprises first, second semiconductor layer is provided;
Etch the first semiconductor layer and form top fin;
Etch region that the second semiconductor layer do not cover by top fin to form the hour-glass in shape bottom fin below the fin of top;
Formed to be centered around and comprise top, the stack fin both sides of bottom fin and the grid structure of top.
8. method as claimed in claim 7, is characterized in that, is formed in the step of top fin, on the first semiconductor layer square one-tenth one hard mask layer this hard mask layer of patterning;
The region utilizing hard mask layer dry etching first semiconductor layer with opening figure to expose, forms the groove that the degree of depth in the first semiconductor layer is less than the first semiconductor layer original thickness;
Utilize hard mask layer along described groove with anisotropic wet etch first semiconductor layer, thus form up-narrow and down-wide trapezoidal shape top fin.
9. method as claimed in claim 8, is characterized in that, is formed in the step of bottom fin, carries out anisotropic wet etching to the region that the second semiconductor layer exposes, and the width forming top and bottom is greater than the hourglass-shaped bottom fin of pars intermedia width.
10. method as claimed in claim 8, is characterized in that, is formed in the step of bottom fin, first utilizes hard mask layer dry etching second semiconductor layer, form the bottom fin with vertical sidewall pattern;
Then carry out anisotropic wet etching to the sidewall that bottom fin exposes, the width forming top and bottom is greater than the hourglass-shaped bottom fin of pars intermedia width.
11. methods as claimed in claim 7, is characterized in that, are formed in the step of top fin, utilize hard mask layer dry etching first semiconductor layer, thus form the top fin with vertical sidewall pattern;
The inwall of the opening then in hard mask layer, the sidewall of top fin and covering one sacrifice side wall layer on the end face of hard mask layer;
Eat-back sacrifice side wall layer and form the sacrifice side wall covered on the sidewall of opening inwall and top fin;
Utilize sacrifice side wall and hard mask layer to etch the region of the second semiconductor layer exposure, form bottom fin.
12. methods as claimed in claim 11, is characterized in that, are formed in the step of bottom fin, carry out anisotropic wet etching to the region that the second semiconductor layer exposes, and the width forming top and bottom is greater than the hourglass-shaped bottom fin of pars intermedia width.
13. methods as claimed in claim 11, is characterized in that, are formed in the step of bottom fin, first utilize hard mask layer and sacrifice side wall dry etching second semiconductor layer, form the bottom fin with vertical sidewall pattern;
Then carry out anisotropic wet etching to the sidewall that bottom fin exposes, the width forming top and bottom is greater than the hourglass-shaped bottom fin of pars intermedia width.
14. methods as claimed in claim 7, is characterized in that, after forming grid structure, are that autoregistration mask injects light dope source/drain region at the upper surface of top fin with grid structure; And
Then on the sidewall of grid structure, form side wall, and implant source electrode/drain electrode doped area in the stack fin of grid structure both sides.
15. methods as claimed in claim 7, is characterized in that, are formed after grid structure, the both sides of the stack fin in grid structure both sides and above optionally epitaxial growth source/drain epitaxial region.
16. methods as claimed in claim 15, is characterized in that, N-type FinFET epitaxially grown source/drain epitaxial region comprise the SiC epitaxial region of elongation strain, P type FinFET epitaxially grown source/drain epitaxial region comprise the SiGe epitaxial region of compression strain.
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