CN104867902A - Electronic module having two conductive structures - Google Patents

Electronic module having two conductive structures Download PDF

Info

Publication number
CN104867902A
CN104867902A CN201510066983.3A CN201510066983A CN104867902A CN 104867902 A CN104867902 A CN 104867902A CN 201510066983 A CN201510066983 A CN 201510066983A CN 104867902 A CN104867902 A CN 104867902A
Authority
CN
China
Prior art keywords
energy
conduct electricity
circuit board
electronic
conductive structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510066983.3A
Other languages
Chinese (zh)
Inventor
托马斯·比格尔
马蒂亚斯·布鲁梅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of CN104867902A publication Critical patent/CN104867902A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B33—ADDITIVE MANUFACTURING TECHNOLOGY
    • B33Y—ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3-D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3-D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
    • B33Y80/00—Products made by additive manufacturing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24105—Connecting bonding areas at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/245—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
    • H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/24998—Reinforcing structures, e.g. ramp-like support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/828—Bonding techniques
    • H01L2224/8284—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83048—Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1136—Conversion of insulating material into conductive material, e.g. by pyrolysis
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

Abstract

The present invention relates to an electronic module having two conductive structures. A method for manufacturing the electronic moduel (1) comprises at least the following steps: providing a circuit board (3) which is provided with a first conductive structure (5), installing at least one electronic element (6) to the first conductive structure (5), and producing with pure addictives an insulation structure and a second conductive structure (11) on the electronic element (6). The electronic module (1) has a circuit board (2) which is provided with a first conductive structure (5,5a,5b), at least an electronic element (6) which is arranged on the first conductive structure (5a) and an insulation structure and a second conductive structure (11) which are arranged on the electronic element (6), wherein the second conductive structure (11) is formed by means of full attached materials. In particular, the electronic module herein is applicable to a power electronic module.

Description

There is the electronic module of two energy conductive structures
Technical field
The present invention relates to a kind of method for the manufacture of electronic module, it at least has following steps: provide the circuit board being provided with the first energy conductive structure, at least one electronic component is installed on the first energy conductive structure, and the second energy conductive structure is set in the above.The present invention also relates to a kind of electronic module, its have be provided with first can conductive structure circuit board, at least one be arranged in first can electronic component on conductive structure and disposed thereon second can conductive structure.Especially, the present invention can be applied on power electronics modules.
Background technology
At present, the typical construction technology of the power component as IGBT based in dielectric base (forming primarily of pottery) and structurized, the circuit that conducts electricity that be made up ofs the wire (such as so-called cementing line) between circuit or the Connection Element with linear formula.There is known the ceramic wafer of the conducting wire bedding that a kind of utilization is made up of copper, so-called DCB (" Direct Copper Bonded (direct copper bonding) " especially, also referred to as DCB, " Direct Bonded Copper (direct copper) ") circuit board.This circuit board is usually also referred to as " substrate ", is such as called as " DCB substrate ".
New development in power electronics modules field can realize the structure possibility of the low inductance of higher reliability and improvement by the structural form of plane, for minimizing power loss and for realizing higher switching frequency.Additionally, eliminate the link position reducing useful life, it produces in troublesome continuous process, such as bonding.Example for planar configuration form is " SiPLIT " technology of Semikron company " SKiN " technology or Siemens company.The feature of SKiN technology is to substitute cementing line by flexibility, structurized film, and this film flatly sinters on DCB circuit board, and described circuit board has the power electronic element of fixed thereon.In SiPLIT technology, being routed on first not structurized film of plane realizes, and this film plays dielectric effect simultaneously.Galvanically realize structuring subsequently and contacting.The latter is produced by the opening removed by laser ablation in film before.
The constructing technology of two planes is common, that is, the wiring layer above must manufacturing with the electroplating process of Expenses Cost before arranging it or when manufacturing module.In SKiN technology, this independently occurs on flexible film with printed-board technology with actual modular manufacture.In SiPLIT technology, galvanically construct in multiple process steps, until reach final copper thickness.
In addition, in the constructing technology of plane, process contains in addition deletes the combination with adding procedure when connecting.When SKiN technology, flexible film such as must before setting etch structures, and then in multistage sintering process, be connected to each other to a module together with all parts (such as cooling body, splicing ear, DCB substrate, flexible printed circuit board).When SiPLIT technology, the film before arranged metallizes and structuring and galvanically constructing with final copper layer thickness in multiple different process.
In order to make module and control circuit board connect, to make power signal and control signal coupling and decoupling, there is different solutions, such as by means of using via element is welded, soldering or sintering be until the spring contact of press-in pin.
Summary of the invention
The object of the invention is to, overcome the shortcoming of prior art at least in part, and propose a kind of feasible scheme of the wiring for manufacturing electronic module simplifiedly especially.Especially, this object has manufactured upper wiring layer simplifiedly.
The feature of this object according to independent claims realizes.Especially, preferred embodiment can be drawn by dependent claims.
This object is realized by a kind of method for the manufacture of electronic module, it at least has following steps: (i) provides the circuit board being provided with the first energy conductive structure, (ii) at least one electronic component is installed on the first energy conductive structure, and (iii) manufactures second energy conductive structure in pure interpolation ground in the above.
First structure or line construction can correspond to lower wiring layer.First structure or line construction can corresponding to upper wiring layers.
The advantage that the method has it is possible to cancel for can conductive structure structuring and the process of metallized Expenses Cost and time by second.Also the additional continuous process for the manufacture of the syndeton for connecting control circuit board need not be considered.In unique process, all required layers can be produced, for dimensionally not deleting with almost arbitrary layer thickness constructing module or the process of ablation or material denudation.The known problem of usual method can be avoided targetedly, such as with the thickness of insulating layer of minimizing when the accessible layer thickness restriction of conductive layer structure or structure or edge bedding.
Especially, the circuit board being provided with the first structure can have ceramic bases, particularly ceramic wafer.Bedding ceramic bases can be carried out by conductive structure with first in side or in both sides.Especially, first can be made up of copper by conductive structure.Especially, ceramic bases can be provided with (particularly not structurized) metal level of whole on side, such as on " downside or dorsal part ", and on opposite side (" upside or front side "), be provided with first can conductive structure.The metal level of whole can be such as made up of copper, and wherein, circuit board can be such as DCB circuit board.But the metal level of whole also can be such as made up of aluminium, wherein, circuit board can be such as IMS (" Insulated Metal Substrate (insulated metal substrate) ") circuit board.But, at random can select the material of substrate in principle and be arranged on this at least one (structurized and not structurized) layer that can conduct electricity suprabasil.Therefore, the base material of polyimides as flexible circuit board can also be applied.
Can such as carry out at least one electronic component being arranged on the first energy conductive structure by means of automatic assembling machine in step (ii).Especially, at least one electronic component can comprise at least one power component, particularly at least one power semiconductor.At least one power component such as can have at least one IGBT, at least one power MOSFET, at least one power diode, at least one thyristor, at least one bidirectional thyristor etc.The circuit board being provided with at least one electronic component also can be called as " circuit board of assembling " below.Circuit board can assemble in side or in both sides.
Especially, manufacture second structure (it is particularly useful as upper wiring layer) in step (iii) comprising: the second structure only produces on the circuit board assembled according to step (i) and (ii), and not manufacture in advance as up to now such as in SKiN technology, and connect and be fixed on the circuit board of assembling subsequently.
Especially, pure interpolation ground manufacture the second structure in step (iii) comprises and does not need to carry out the ablation of high cost or the process steps of material denudation.Especially, the process steps of ablation or material denudation is interpreted as such process steps, that is, continue the material volume retained remove other situations in this process steps under.Especially, do not occur under the process steps of ablation or material denudation for the cleaning course removing the material that non-continuous retains in other situations, and can apply in the method.Cleaning course such as can comprise cleaning and/or compressed air purifying, such as to remove powder.
Add manufacture also can be called as interpolation make or produce make.
Electronic module also can be called as power electronics modules.This power electronics modules is usually to the electronic module being different from inactivity element in its detailing requiments significantly.
A design is, can carry out arranging insulating barrier before conductive structure in manufacture second.Which suppress the formation of parasitic leakage electric current, improve and puncture fail safe and/or even prevent short circuit in the conceived case.Especially, second can manufacture on the insulating layer at least in part by conductive structure.Such as, second can manufacture on the insulating layer outside contact position by conductive structure.
A design is also had to be, pure interpolation ground in step (iii) manufactures the second structure and comprises: (iiia) arranges the heat activated layer of energy, it is electric insulation in the state do not heated, and be to continue conduction after heating, and (iiib) heat activated layer of heating energy partly.Therefore, it is possible in a particularly simple way, by energy abundance and localized heating enough hot thus produces on the position that will there is conductive region second energy conductive structure.Enough do not heating the position of the heat activated layer of this energy, it keeps electric insulation.
Such as can have plastic basic unit (Kunststoff-Matrix) by heat activated layer, metallic particles is dissolved in this plastic basic unit as filler.If for the material volume of this layer carries enough energy, removes so there or get rid of plastics, and metallic particles is combined with one another to the volume of conduction.
The heat activated layer of energy can arrange at least partly and heat on the insulating layer and/or partly.
Thus, a design is, carries out the heat activated layer of heating energy partly by means of at least one laser beam.This advantage drawn it is possible at an easy rate, exactly and introduce enough for generation of the energy of electrical conductance with high structural resolution.
Can produce in a different manner in principle by heat activated layer.It such as can produce by settling film.Also have a kind of design to be, arrange and impress or spraying plating comprising of the heat activated layer of this energy.Impress and such as can carry out by means of one or more scraper plate and/or roller.Therefore, the advantage of acquisition is, can heat activated layer when also can being seamlessly arranged in edge or terraced portion etc. without when additional expense.Identical advantage also can by realizing by means of casting, particularly arranging of injection moulding of injection.
An improvement project is, the second structure in step (iii) is manufactured by so-called laser sintered or laser fusion.In laser sintered, metal dust is sintered together by means of laser beam and other radiation medium.Especially, can apply so-called optionally laser sintered (SLS).This powder can have adhesive, and it such as also can be applied as sintering adjuvant, such as, for simplifying liquid-phase sintering.Also directly metal dust may be used when not adding adhesive.At this, metal dust can fully be melted.For this reason, such as CW laser can be used.This method variant also can be called as optionally laser fusion (SLM).Plastic/metal particle composites already described above also can be used as raw material that are laser sintered and/or laser fusion.
Also the radiation of other types can be used in principle, such as the electronics etc. of electron radiation sintering.
Another design is, add ground arrange the second structure comprise arrange and activation the second structure at least one part form can be energy activated medium.Especially, the medium if possible activated is arranged on a flat surface, and this can draw and very simply manufacture the second mechanism.Medium that can be energy activated can such as be arranged with the form of reaction film (such as the NanoFoil of Indium Corporation company).If reaction nanometer film is activated by energy input (such as radio, sufficiently high voltage, flame, microwave, laser beam etc.) on a position, so expand thermal response from this position by nanometer film, thus this nanometer film is molten into the second structure in its basic unit.When such as reaction film has the multiple stack be made up of the aluminium lamination replaced and nickel dam, the second structure manufactured thus is made up of aluminium nickel mixture, particularly alloy especially.
An improvement project is, is arranged on the circuit board of assembling by electric insulation layer in step (iii) before arranging the second structure.Arrange electric insulation layer like this, namely this electric insulation layer at least has the portion of leaving a blank on such as upper/lower positions, the circuit board namely assembled should on this position with the second structure electrical contact.Especially, the portion of leaving a blank can be positioned in the first structure and on the contact area being positioned at electronic component or join domain.Therefore, it is possible to realize can many-sided especially design ground and relative to assembling circuit board electricity manufacture the second structure safely.
In addition, a design is, the second structure manufactures at least one contact element, such as contact plug with adding.Contact element such as can cause the connection of control circuit board.Especially, the manufacture of at least one contact element can be carried out in identical process steps, in this process steps, also can manufacture the second structure.Especially, this also realizes thus, and namely at least one contact element and the second structural integrity ground designs or integrated, integrally the part of the second structure.Alternatively, contact element can be manufactured dividually, and such as be arranged in the second structure by means of connecting media, such as reaction film that can be energy activated subsequently
Alternatively, can set up this contacting by means of pressureless sintering or by means of the cream of argentiferous, this cream sinters (such as in so-called " sintering pressing process ") at pressure with when adding heat simultaneously.The latter can directly realize in the assembling process of element.
In addition, a design is, carries out arranging the second structure with adding by means of so-called 3D printer.This can realize very simply manufacturing.Especially, such as the circuit board of assembling can be incorporated in 3D printer for this reason, and run 3D printer by means of manufacture successively especially subsequently, for manufacture second structure.
An improvement project is, also can by means of the selectable insulating barrier of 3D printer setup.
In addition, a design is, is installed in the first electric structure by least one electronic component by means of connecting media, such as reaction film (such as the NanoFoil of Indium Corporation company) that can be energy activated.Therefore the installation be dirt cheap is obtained.In addition, can via can conductive layer, such as Alpha Cookson company Argomax directly under the effect of heat and pressure at assembling element time realize this contacting.
This object is also realized by a kind of electronic module, and it manufactures by means of aforesaid method.
This object is also realized by a kind of electronic module, its have be provided with first can conductive structure circuit board, be arranged in first can at least one electronic component on conductive structure and disposed thereon second can conductive structure, wherein, by means of add or produce material flows method produce the second structure.
Accompanying drawing explanation
Schematically illustrating of the embodiment elaborated in conjunction with following connection with figures, illustrates above-mentioned characteristic of the present invention, the mode of feature and advantage and realization and method.At this, for simple and clear object, element that is identical or phase same-action marks with identical label.
Fig. 1 illustrates the cross section according to electronic module of the present invention.
Embodiment
Fig. 1 illustrates electronic module 1, following this electronic module of manufacture: first provide DCB circuit board 2, it has the ceramic bases 3 of the sheet with front side 3a and rear side 3b.Rear side 3b carrys out bedding with the not structurized metal level 4 be made up of aluminium or copper.Front side 3a carrys out bedding with the first structure 5, and this first structure has many layer-shaped area (such as circuit) 5a and 5b be such as made up of copper.That is, the first structure 5 be can conduct electricity and be downside routing planes.
Power component 6, such as IGBT are arranged on the first structure 5, i.e. zone 5a.Power component 6 can downside ground or at upside contacting, wherein, on the downside of it this reaction film 7 form that (such as by means of laser beam) is activated by means of before can be energy activated connecting media connect and and then install.Reaction film 7 is such as the film of the NanoFoil type of Indium Corporation company.Alternatively, can set up this contacting with pressureless sintering process or by means of the cream of special argentiferous, this cream sinters (such as in so-called " sintering pressing process ") at pressure with when adding heat simultaneously.The latter can directly realize being assemblied in by power component 6 in the process on DCB circuit board 2, such as on 5a or 5b of region or in ceramic bases 3.
In another step, on the upside of circuit board 2 to 7 that electric insulation layer 9 is arranged on foregoing assembling or the subregion of front side 8, namely at least between 5a and 5b of region until the upside of power component 6 or front side 10.
In step below, in the part of the upside of the structure 2 to 9 manufactured up to now, (" in the above ") pure interpolation ground manufactures the second energy conductive structure 11, exactly, at least manufacture between second area 5b and the region of the upside of power component 6 or the energy electrical contact of front side 10.At this, first second can be arranged with the form of energy heat activated adhesive layer by conductive structure 11, and exactly, as plastic/metal stratum granulosum, it has the plastic basic unit with being wherein distributed with metallic particles.Such as impress by (such as by means of at least one scraper plate and/or at least one roller), arranged by spraying plating etc.Plastic/metal stratum granulosum is electric insulation in the state that (enough) does not heat, and is to continue conduction after heating.In a subsequent step, heating of plastic/metal particle layer partly, exactly, in an illustrated embodiment, carries out in the rail road at least between second area 5b and the front side of power component 6.Such as carry out the heating of local by means of laser beam at this.Thus, based on fusing and/or the sintering of metallic particles, manufacture the electric lead between second area 5b and the front side 10 of power component 6 or printed conductor, it is at least a part for the second structure 11.Second structure 11 also can be counted as wiring layer.
In the second structure 11, manufacture contact element 12, such as contact plug, contact zones or contact spring etc. with adding on the top of second area 5b.At this, contact element 12 is as the part of the not separated manufacture of the one of the second structure 11.Alternatively, contact element 12 also can manufacture dividually, and is fixed on subsequently in the second structure 11.
Especially, several or all structures 9,11,12 be arranged on the printed conductor 2 to 7 of assembling can be added ground by means of 3D printer or manufacture with producing.
In step below, the cover layer 13 of insulation is still selectively set, but this cover layer covers contact element 12 by halves.
Although set forth in detail in detail by shown embodiment and describe the present invention, the present invention is not limited to disclosed example, and other variant can be derived by professional, and this does not depart from protection scope of the present invention.
In general, as long as no being limited by term " just what a " clearly, such as, then " one ", " one " etc. are interpreted as odd number or plural number, are particularly interpreted as the meaning of " at least one " or " one or more ".
As long as no limiting clearly, numeral illustrates and also can comprise the numeral that provides exactly and comprise the common margin of tolerance.

Claims (11)

1., for the manufacture of a method for electronic module (1), at least there are following steps:
The circuit board (3) being provided with the first structure (5) that can conduct electricity is provided,
Be installed to by least one electronic component (6) in described the first structure (5) that can conduct electricity, wherein, described at least one electronic component (6) is power component, and
Described first structure that can conduct electricity manufactures to pure interpolation the second structure (11) that can conduct electricity.
2. method according to claim 1, wherein, arrange insulating barrier (9) before manufacturing described the second structure (11) that can conduct electricity.
3. according to method in any one of the preceding claims wherein, wherein, arrange described second structure (11) with adding to comprise:
Arrange the heat activated layer of energy, the heat activated layer of described energy is electric insulation in the state do not heated, and can conduct electricity lastingly after heating, and
Heat the heat activated layer of described energy partly.
4. method according to claim 3, wherein, heats the heat activated layer of described energy partly by means of at least one laser beam.
5. the method according to any one of Claims 2 or 3, wherein, arranges the heat activated layer of described energy and comprises and impressing or spraying plating.
6. method according to claim 1, wherein, adds ground and arranges described second structure (11) and comprise setting and activate the energy activated connecting media of the energy of form at least partially of described second structure.
7. according to method in any one of the preceding claims wherein, wherein, manufacture at least one contact element (12) on the upper ground that adds of described second structure (11).
8. according to method in any one of the preceding claims wherein, wherein, arrange described second structure (11) with at least adding to carry out by means of 3D printer.
9. according to method in any one of the preceding claims wherein, wherein, by means of carrying out at least one electronic component (6) being installed on described first structure (5,5a) of electricity by energy activated connecting media.
10. an electronic module (1), comprises
Be provided with the circuit board (2) of the first structure (5,5a, 5b) that can conduct electricity,
At least one is arranged in the electronic component (6) in described the first structure (5a) that can conduct electricity, and wherein, at least one electronic component (6) is power component, and
Be arranged on described the first structural the second structure (11) that can conduct electricity that can conduct electricity,
Wherein,
Material flows method by means of pure interpolation generates described second structure (11).
11. electronic modules according to claim 9 (1), wherein, described the second structure (11) that can conduct electricity is at least partially disposed on insulating barrier (9).
CN201510066983.3A 2014-02-25 2015-02-09 Electronic module having two conductive structures Pending CN104867902A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102014203309.8A DE102014203309A1 (en) 2014-02-25 2014-02-25 Electronic module with two electrically conductive structures
DE102014203309.8 2014-02-25

Publications (1)

Publication Number Publication Date
CN104867902A true CN104867902A (en) 2015-08-26

Family

ID=53782415

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510066983.3A Pending CN104867902A (en) 2014-02-25 2015-02-09 Electronic module having two conductive structures

Country Status (2)

Country Link
CN (1) CN104867902A (en)
DE (1) DE102014203309A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110024112A (en) * 2016-09-30 2019-07-16 西门子股份公司 Power module and method for manufacturing power module

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3151641A1 (en) * 2015-09-30 2017-04-05 Siemens Aktiengesellschaft Method and device for wiring a technical system and technical system
EP3261119A1 (en) * 2016-06-21 2017-12-27 Infineon Technologies AG Power semiconductor module components and additive manufacturing thereof
EP3288349A1 (en) 2016-08-25 2018-02-28 Siemens Aktiengesellschaft Power module, module assembly and method for producing a power module
DE102016222909A1 (en) * 2016-11-21 2018-05-24 Robert Bosch Gmbh Heat sink for cooling a power module and method for producing a heat sink
EP3326986B1 (en) * 2016-11-28 2020-11-25 Infineon Technologies AG Process for the manufacture of a metal-ceramic substrate
US20180153951A1 (en) 2016-12-05 2018-06-07 Mead Johnson Nutrition Company Methods for Inducing Adipocyte Browning, Improving Metabolic Flexibility, and Reducing Detrimental White Adipocyte Tissue Deposition and Dysfunction
FR3061989B1 (en) 2017-01-18 2020-02-14 Safran METHOD FOR MANUFACTURING AN ELECTRONIC POWER MODULE BY ADDITIVE MANUFACTURE, SUBSTRATE AND RELATED MODULE
US20180184550A1 (en) * 2016-12-28 2018-06-28 Microsoft Technology Licensing, Llc Metal additive structures on printed circuit boards
DE102017217406A1 (en) * 2017-09-29 2019-04-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Component and method for its production
EP3852132A1 (en) 2020-01-20 2021-07-21 Infineon Technologies Austria AG Additive manufacturing of a frontside or backside interconnect of a semiconductor die
US11557706B2 (en) 2020-09-30 2023-01-17 Ford Global Technologies, Llc Additive manufacturing of electrical circuits

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1272892A (en) * 1997-06-06 2000-11-08 格哈德·瑙恩多夫 Conductor track structures arranged on nonconductive material, espectially fine conductor track structure, and method for producing the same
US20060103005A1 (en) * 2002-06-20 2006-05-18 Jurgen Schulz-Harder Metal-ceramic substrate for electric circuits or modules, method for producing one such substrate and module comprising one such substrate
CN101436556A (en) * 2007-11-16 2009-05-20 塞米克朗电子有限及两合公司 Method for producing a semiconductor component
CN101801674A (en) * 2007-05-18 2010-08-11 应用纳米技术控股股份有限公司 metallic ink
CN102903681A (en) * 2011-07-29 2013-01-30 英飞凌科技股份有限公司 Flexible connection of substrate in power semiconductor module

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2002356780A1 (en) * 2002-01-14 2003-07-24 Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. System for the manufacture of electric and integrated circuits
US20120178189A1 (en) * 2011-01-06 2012-07-12 Reber Douglas M Method for forming an over pad metalization (opm) on a bond pad

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1272892A (en) * 1997-06-06 2000-11-08 格哈德·瑙恩多夫 Conductor track structures arranged on nonconductive material, espectially fine conductor track structure, and method for producing the same
US20060103005A1 (en) * 2002-06-20 2006-05-18 Jurgen Schulz-Harder Metal-ceramic substrate for electric circuits or modules, method for producing one such substrate and module comprising one such substrate
CN101801674A (en) * 2007-05-18 2010-08-11 应用纳米技术控股股份有限公司 metallic ink
CN101436556A (en) * 2007-11-16 2009-05-20 塞米克朗电子有限及两合公司 Method for producing a semiconductor component
CN102903681A (en) * 2011-07-29 2013-01-30 英飞凌科技股份有限公司 Flexible connection of substrate in power semiconductor module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110024112A (en) * 2016-09-30 2019-07-16 西门子股份公司 Power module and method for manufacturing power module

Also Published As

Publication number Publication date
DE102014203309A1 (en) 2015-08-27

Similar Documents

Publication Publication Date Title
CN104867902A (en) Electronic module having two conductive structures
US11810887B2 (en) Double-sided cooling type power module and manufacturing method therefor
TWI738948B (en) Power module comprising a housing configured in tiers
JP6358129B2 (en) Power converter
CN104637832B (en) Semiconductor device and its manufacturing method
US20210143103A1 (en) Power module and method for manufacturing power module
CN110268520B (en) Method for integrating power chips and forming bus bars of heat sink
US10727173B2 (en) Power module and power conversion system including same
US9871025B2 (en) Commutation cell
CN101937909B (en) An electrical module
CN110235529B (en) Circuit board arrangement with an electrical component and a heat sink
CN103428992A (en) Circuit board, electronic module, lighting device and method for manufacturing circuit board
CN104867863B (en) The manufacture of electronic module
CN109155298A (en) The method of power module and manufacture power module
CN107924892A (en) Circuit carrier includes the power electronic arrangement of circuit carrier
CN108353508A (en) The manufacturing method of substrate and substrate
JP5275859B2 (en) Electronic substrate
CN109716877B (en) Electronic assembly
JP2010199505A (en) Electronic circuit device
JP5884611B2 (en) Electronic equipment
JP2020502824A (en) Power switching module, converter integrating power switching module, and manufacturing method
CN104867903B (en) Electronic module
CN106031307A (en) Method for producing a power printed circuit and power printed circuit obtained by this method
CN110383473B (en) Power electronic circuit equipped with a bus bar forming a heat sink and integration method
US11515804B2 (en) Electrical power circuit for an electrical power converter

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
EXSB Decision made by sipo to initiate substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20150826

RJ01 Rejection of invention patent application after publication