CN1050698C - 球网格阵列型半导体器件 - Google Patents
球网格阵列型半导体器件 Download PDFInfo
- Publication number
- CN1050698C CN1050698C CN96110497A CN96110497A CN1050698C CN 1050698 C CN1050698 C CN 1050698C CN 96110497 A CN96110497 A CN 96110497A CN 96110497 A CN96110497 A CN 96110497A CN 1050698 C CN1050698 C CN 1050698C
- Authority
- CN
- China
- Prior art keywords
- semiconductor element
- ball
- array
- grid
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
一种球网格阵列型半导体器件具有上部信号互连图形(1a)、置于绝缘基片(7)上表面上的半导体元件安装垫片(4)、和从垫片(4)向基片(7)的四个角的延伸图形(5)。由通孔(2)将上部信号互连图形(1a)连接到基片(7)下表面上的下部信号互连图形(1b)。半导体元件(10)安装在垫片(4)上,并具有由细金属丝(11)连接到上部信号互连图形(1a)的电极(3)。半导体元件(10)由模塑树脂层(9)封装。焊料球(3)熔到基片(7)的下表面,并连接到下部信号互连图形(1b)上。
Description
本发明涉及一种球网格阵列型半导体器件。
随着集成半导体元件集成度的提高,安装半导体元件的集成电路封装具有越来越多的管脚。有一种增加了管脚数量的常规QFP(扁平封装)已准备将外部的引线与引线间距或间隔由0.65mm减小至0.5mm或0.4mm。由于所设置的管脚的阵列和外部封装的外形将具有沿封装外部周边设置的外引线阵列的QFP限制在最多400只管脚,而为了适应高集成构造和半导体元件多功能的需要对有500至1000只管脚的半导体元件封装的需要已日益增长。
近年来,为迎合多管脚应用的趋向已提出一种集成电路封装型,即外引线排列于一个平面内的球网格阵列型(BAG)。
附图1是表示具有这种球网格阵列型封装的常规半导体器件的剖面图。如图1所示,玻璃环氧树脂基片7支撑位于上表面上的上部信号互连图形1a和半导体器件安装垫片4,还反撑位于下表面上的下部信号互连图形1b。上下信号互连图形1a和1b通过通孔2互连。在下部信号互连图形1b中存在用作外引线的焊料球3电极的网状图形。除连接区外上部信号互连图形1a皆为焊料阻挡层6所覆盖。
用安装件(未示出)将半导体元件10安装在半导体元件安装垫片4上。半导体元件10具有由细金属丝11将之连接到上部信号互连图形的电极。按传递模塑工艺由模塑树脂层9封装半导体元件10和金属丝11。
关于上述球网格阵列型封装,玻璃环氧树脂基片7的整个下表面可用作连接外电路的区域。因此,这种球网格阵列型封装能够具有比常规QFP更多的管脚,而不会减小外部引线间距。
球网格阵列型封装易于沿玻璃环氧树脂基片和模塑树脂层间界面吸潮。因此,在将这种球网格阵列型封装安装到电路基片上时,由于它被加热使所吸湿气蒸发,于是玻璃环氧树脂基片和模塑树脂趋于相互脱离。因此,在将这种球网格阵列型封装安装在电路基片上的之前,必需烘烤该球网格阵列型封装以除去其内部所吸湿气。另外在烘烤工艺后,必须在给定的时间周期内完成球网格阵列型封装的安装。这就给安装球网格阵列型封装的工艺管理造成一定困难。
另一个缺点是玻璃环氧树脂基片的导热性低,致使球网格阵列型封装的热阻比已广泛用作多管脚封装的常规倒置腔陶瓷管脚网格阵列型(PGA)封装的热阻要高,所以可安装的半导体元件的数量受功耗的限制。
因此本发明的一个目的是提供一种有球网格阵列型封装的半导体器件,不用或用相对简单的烘烤工艺便能将它装在电路基片上,烘烤工艺向来为器件安装前必需的工艺。
本发明的另一目的是提供一种有球网格阵列型封装的半导体器件,为了能将大电流要求的的半导体器件安装在该球网格阵列型封装上,增加该封装的热辐射能力。
为实现上述目的,提供一种有球网格阵列型封装的半导体器件,它包括:在其上表面上有半导体元件安装垫片的绝缘基片;安装在半导体元件安装垫片上并有多个电极的的半导体元件;置于绝缘基片上表面上并由细金属丝使之与半导体元件电极连接的上部信号互连图形;置于与上表面相反的绝缘基片下表面上的下部信号互连图形;置于下表面上并借助限定在绝缘基片中的通孔与上部信号互连图形连接的下部信号互连图形;连接到下部信号互连图形的多个球电极;封装半导体元件的模塑树脂层;及置于上表面上并由半导体元件安装垫片延伸到模塑树脂层之外的多个延伸图形。
从下面根据说明发明实施例的附图的描述可明显看出本发明的上述和其它目的、特征和优点。
图1是有这种球网格阵列型封装的常规半导体器件的剖面图;
图2是用于本发明的具有球网格阵列型封装的半导体器件实施例的布线基片的平面图;
图3是沿图2中的线III-III的剖面图;
图4是本发明的有球网格阵列型封装的半导体器件第二实施例的平面图;
图5是沿图4中的线V-V线的剖面图;
图6是沿图4中的线VI-VI线的剖面图。
如图2所示,布线基片包括在其上表面中心区域有以铜箔图形形式存在的方形半导体元件安装垫片4的方形玻璃环氧树脂基片7,垫片4等于或大于要待安装于其上的半导体元件的尺寸。置于玻璃环氧树脂基片7的上表面上以铜箔图形形式存在的四个延伸图形5分别从半导体元件安装垫片4的四个角沿对角线向外延伸至玻璃环氧树脂基片7的四个角。
置于玻璃环氧树脂基片7的上表面上以铜箔图形形式存在的上部信号互连图形1a从环绕半导体元件安装垫片4的区域向外沿径向延伸至玻璃环氧树脂基片7的外围边缘。如图3所示,限制在玻璃环氧树脂基片7中的通孔把上部信号互连图形1a连接到置于玻璃环氧树脂基片7下表面上以铜箔图形形式存在的下部信号互连图形1b和在玻璃环氧树脂基片7中的内部信号互连图形1c上。除连接区外,上下部信号互连图形1a、1b皆为焊接阻挡层6所覆盖。这里不再说明覆盖下部信号互连图形1b的焊接阻挡层6。不同于信号互连图形,每个延伸图形5由金属镀敷并不为任何焊接阻挡层6所覆盖。
按下列步骤制造如图4所示的半导体器件:用一安装件(未示出)在如图2和3所示的布线基片的半导体元件安装垫片4上安装半导体元件10;然后用如金线之类的细金属丝11把半导体元件10的电极与上部信号互连图形1a的各接线端相互连接;此后用由传递模塑工艺形成的模塑树脂层9封装半导体元件10和细金属丝11;最后将焊料球3熔化到包括位于玻璃环氧树脂基片7的下表面的下部信号互连图形1b的焊点上。
在如此制造的半导体器件中,与半导体元件安装垫片4连接的延伸图形5用来将由半导体元件10产生的热量散发到球网格阵列型封装的外部。由此,防止将由半导体元件10产生的热量限于球网格阵列型封装内。镀敷在延伸图形5上的金层8与模塑树脂层9的粘合相对弱。当半导体器件安装在电路基片上时,金层8与模塑树脂层9用作从封装内排放湿气的通道。由此防止当半导体器件安装到电路基片上时玻璃环氧树脂基片7和模塑树脂层9相互脱离。任何向来为安装半导体器件前对球网格阵列型封装必需的烘烤工艺可以省去。另外,球网格阵列型封装也可用比常规烘烤工艺简单的烘烤工艺进行烘烤。
在上述实施例中,四个延伸图形5从半导体元件安装垫片4的铜箔延伸到玻璃环氧树脂基片7的四个角。但这种结构不是必需的,在延伸图形5延伸至模塑树脂层9外的情况下,延伸图形5的形状和数目可改变。镀敷在延伸图形5上的金层8可以由与模塑树脂层9粘合相对弱的各种其它金属覆盖层来代替。
如上所述,由于本发明的球网格阵列型封装有从半导体元件安装垫片延伸至模塑树脂层外的延伸图形,球网格阵列型封装的热辐射能力增强。球网格阵列型封装还有从封装内部排防湿气的通道,以防止当半导体器件安装到电路基片上时玻璃环氧树脂基片和模塑树脂层相互脱离。因为延伸图形被与模塑树脂层粘合相对弱的层所覆盖,所以可有效防止玻璃环氧树脂基片和模塑树脂层相互脱离。
尽管在上述描述中公开了本发明的特征和优点,但应当理解到,该公开只是说明性的,在所附权利要求书的范围内可以对各部件的设置作出各种变化。
Claims (6)
1.一种球网格阵列型的半导体器件包括:
在其上表面上具有半导体元件安装垫片(4)的绝缘基片(7);
安装在所说半导体元件安装垫片(4)上并有多个电极(3)的的半导体元件(10);
置于绝缘基片(7)所说上表面上并由细金属丝(11)使之与所说半导体元件(10)的电极(3)连接的上部信号互连图形(1a);
置于与所说上表面相反的绝缘基片下表面上的下部信号互连图形(1b);
置于下表面上并借助限定在所说绝缘基片(7)中的通孔与所说上部信号互连图形(1a)连接的下部信号互连图形(1b);
连接到所说下部信号互连图形(1b)的多个球电极;
封装所说半导体元件(10)的模塑树脂层(9);
其特征在于:
置于所说上表面上并由所说半导体元件安装垫片(4)延伸到所说模塑树脂层(9)之外的多个延伸图形(5)。
2.一种根据权利要求1的球网格阵列型半导体器件,其特征在于:所说绝缘基片(7)包括玻璃环氧树脂基片;所说上部信号互连图形(1a)、所说下部信号互连图形(1b)、所说半导体元件安装垫片(4)和所说延伸图形(5)的每一个皆包含铜箔图形。
3.一种根据权利要求1的球网格阵列型半导体器件,其特征在于:每个所说延伸图形(5)皆被与所说模塑树脂层(9)相对弱粘合的金属层所覆盖。
4.一种根据权利要求3的球网格阵列型半导体器件,其特征在于:所说金属层包括所镀敷的金层(8)。
5.一种根据权利要求1的球网格阵列型半导体器件,其特征在于:所说上部信号互连图形(1a)由焊料阻挡层(6)所覆盖,所说半导体元件安装垫片(4)的所说延伸图形(5)没有所说焊料阻挡层(6)。
6.一种根据权利要求1的球网格阵列型半导体器件,其特征在于:所说延伸图形(5)从所说半导体元件安装垫片(4)的各个角向所说绝缘基片(7)的各角延伸。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP192671/95 | 1995-07-06 | ||
JP7192671A JP2814955B2 (ja) | 1995-07-06 | 1995-07-06 | Bga型半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1149201A CN1149201A (zh) | 1997-05-07 |
CN1050698C true CN1050698C (zh) | 2000-03-22 |
Family
ID=16295114
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN96110497A Expired - Fee Related CN1050698C (zh) | 1995-07-06 | 1996-07-06 | 球网格阵列型半导体器件 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5693980A (zh) |
JP (1) | JP2814955B2 (zh) |
CN (1) | CN1050698C (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6777965B1 (en) | 1998-07-28 | 2004-08-17 | Micron Technology, Inc. | Interposer for electrically coupling a semiconductive device to an electrical apparatus |
JP2000323623A (ja) | 1999-05-13 | 2000-11-24 | Mitsubishi Electric Corp | 半導体装置 |
US6261869B1 (en) * | 1999-07-30 | 2001-07-17 | Hewlett-Packard Company | Hybrid BGA and QFP chip package assembly and process for same |
JP3668066B2 (ja) * | 1999-09-01 | 2005-07-06 | 富士通株式会社 | 半導体パッケージ用プリント配線板およびその製造方法 |
JP2003046034A (ja) * | 2001-07-31 | 2003-02-14 | Nec Kagobutsu Device Kk | 樹脂封止型半導体装置 |
CA2358419C (en) * | 2001-10-05 | 2006-06-13 | Jung-Tsung Wei | Vibration sensor device |
US20060220191A1 (en) * | 2005-04-01 | 2006-10-05 | Honeywell International Inc. | Electronic package with a stepped-pitch leadframe |
JP5159229B2 (ja) * | 2007-09-27 | 2013-03-06 | 京セラ株式会社 | 配線基板の製造方法 |
JP5591594B2 (ja) * | 2009-07-13 | 2014-09-17 | ローム株式会社 | 半導体デバイス |
JP6437012B2 (ja) | 2014-11-27 | 2018-12-12 | 国立研究開発法人産業技術総合研究所 | 表面実装型パッケージおよびその製造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US513521A (en) * | 1894-01-30 | Marshall mcdonald |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS646038U (zh) * | 1987-06-30 | 1989-01-13 | ||
JPH06236944A (ja) * | 1993-02-09 | 1994-08-23 | Sony Corp | 半導体実装における放熱装置 |
US5572405A (en) * | 1995-06-07 | 1996-11-05 | International Business Machines Corporation (Ibm) | Thermally enhanced ball grid array package |
-
1995
- 1995-07-06 JP JP7192671A patent/JP2814955B2/ja not_active Expired - Fee Related
-
1996
- 1996-06-18 US US08/665,536 patent/US5693980A/en not_active Expired - Fee Related
- 1996-07-06 CN CN96110497A patent/CN1050698C/zh not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US513521A (en) * | 1894-01-30 | Marshall mcdonald |
Also Published As
Publication number | Publication date |
---|---|
US5693980A (en) | 1997-12-02 |
JP2814955B2 (ja) | 1998-10-27 |
CN1149201A (zh) | 1997-05-07 |
JPH0922961A (ja) | 1997-01-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5434750A (en) | Partially-molded, PCB chip carrier package for certain non-square die shapes | |
EP0554893B1 (en) | Partially-molded, PCB chip carrier package and method of forming same | |
US5065281A (en) | Molded integrated circuit package incorporating heat sink | |
US5646828A (en) | Thin packaging of multi-chip modules with enhanced thermal/power management | |
US6876069B2 (en) | Ground plane for exposed package | |
US5615089A (en) | BGA semiconductor device including a plurality of semiconductor chips located on upper and lower surfaces of a first substrate | |
US5705851A (en) | Thermal ball lead integrated package | |
US20020096767A1 (en) | Cavity down ball grid array package with EMI shielding and reduced thermal resistance | |
US5598321A (en) | Ball grid array with heat sink | |
US6781222B2 (en) | Semiconductor package having vertically mounted passive devices under a chip and a fabricating method thereof | |
JP2000228460A (ja) | ポリマースタッドグリッドアレイのための基板の製造のための方法 | |
CN1050698C (zh) | 球网格阵列型半导体器件 | |
CN112103196B (zh) | 电磁屏蔽模组结构和电磁屏蔽模组结构的制备方法 | |
US6137170A (en) | Mount for semiconductor device | |
US6414386B1 (en) | Method to reduce number of wire-bond loop heights versus the total quantity of power and signal rings | |
CN112103282B (zh) | 系统封装结构和系统封装结构的制备方法 | |
CN219873519U (zh) | 一种改善镀层分层的引线框架及半导体器件 | |
CN212257384U (zh) | 一种引线框架及fc-qfn封装体 | |
CN212570994U (zh) | 一种led显示模组及具有其的显示屏单元板和显示屏 | |
CN214176035U (zh) | 半导体封装结构 | |
KR100206977B1 (ko) | 직립형 볼 그리드 어레이 패키지 | |
KR100215119B1 (ko) | 알루미늄 박판을 이용한 csp 패키지 제조방법 | |
KR100235498B1 (ko) | 반도체 패키지 | |
KR19990056764A (ko) | 볼 그리드 어레이 패키지 | |
KR0145769B1 (ko) | 반도체 패키지 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: NEC ELECTRONICS TAIWAN LTD. Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD. Effective date: 20030404 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20030404 Address after: Kawasaki, Kanagawa, Japan Patentee after: NEC Corp. Address before: Tokyo, Japan Patentee before: NEC Corp. |
|
C19 | Lapse of patent right due to non-payment of the annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |