CN1050929C - 利用沟槽平面化方法在绝缘体上键合亚微米硅 - Google Patents
利用沟槽平面化方法在绝缘体上键合亚微米硅 Download PDFInfo
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Abstract
利用沟槽腐蚀方法和氮化硅层20,为硅岛18提供可控厚度和抛光停止层,在绝缘衬底8上面键合硅,提供具有均匀厚度的硅岛18。
Description
本发明涉及在绝缘体上键合硅(SOI)的工艺和器件,更具体地说是涉及SOI衬底器件,以及用以提供均匀SOI衬底的方法和技术。
在制造微电子电路方面,硅片已是制造固态器件的主要材料。然而,在超大规模集成(VLSI)器件方面,其它材料正在代替硅。两种重要材料是在绝缘体上键合的硅(在二氧化硅上键合硅)和象砷化镓那样的化合物半导体材料。选择这种材料是因为它们固有的高速度和优化的电路参数。例如,在通信系统中常常使用SOI器件,因为它们的电阻不能暴露于有害的辐射之中。
一种SOI技术是在薄片的氧化区域上面产生硅岛。把薄片形成图形产生氧化的台面。在氧化图形的上面生长多晶硅,然后在它的背面研磨该薄片直到氧化层。于是,最后的薄片可认为是在由多晶硅支持的二氧化硅层上形成半导体级硅的图形。采用该技术的一个问题是各硅岛的厚度有很大的差别,因为难于把薄片研磨到适合微电路的精确层厚。
另一种现有技术依靠把氧直接注入到硅片的表面,以便产生掩埋的氧化层(SIMOX)。然而,这种技术引起硅层不可接受的损伤,该损伤不能通过退火和再结晶被充分地消除。此外,氧化层太薄不能提供可靠的绝缘。
第3种技术依靠衬底上晶体的再生长。此时,氧化硅衬底,并使氧化层形成图形,然后再把它的一部分除掉。将多晶硅淀积到氧化物凹槽中,再结晶,使其形成多晶硅。该技术的一个问题是结晶多晶硅的晶粒间界干扰岛中结的电气完整性。
还有一种提供SOI片的技术,它依靠片子的键合技术。按照这种技术,器件片或支撑片被氧化,使其表面之一被覆二氧化硅。然后把这两种片子放在一起在炉中以充分高的温度加热,结果在器件片和支撑片之间产生氧化键合层。然后适当地减少器件片的厚度,直到足够薄的层以便适于高速的微电路。例如,大约625微米厚的原始器件片,被减薄到2或3微米加或减1到3微米。
而且,和上述SOI键合技术一样,器件片的最终厚度,对于通常制造技术,是非常不均匀。结果,某些器件可能是象1微米那样薄而另一些器件可能象5微米那样厚。由于器件厚度的这些差别,把其布图到衬底上的最后获得的微电路的性能,按照不可接受的厚度差别大小,将会有不同的变化。由于芯片太厚或者太薄,由这种片制成的最终器件,不可能实现按设计这种器件的技术规范。
按照本发明,在绝缘体上键合硅的工艺包括下述步骤,提供具有上表面和下表面的支撑片的衬底,以及提供具有上表面和下表面的器件片;所述的器件片的所述下表面对置于所述支撑片的上表面,一个氧化层配置在支撑片和器件片之间,把每一片相对的表面键合起来,在器件片的上表面形成很多器件区,以限定由器件之间露出的氧化层相互隔开的多个器件区;用具有预定厚度的连续不间断的抛光停止层覆盖器件区和露出的氧化层;把覆盖器件区的连续不间断的抛光停止层平面化,使器件区平面化到氧化层上面抛光停止层的厚度。
本工艺的优点在于,它可在绝缘体片上形成的硅和在绝缘芯片上形成的硅是均匀而一致的。所以,本发明提供包括相当厚和均匀单晶硅层的SOI片和芯片。利用支撑片,一般为硅,和器件片,一般为单晶硅,的工艺,提供上述制品。片子之一具有氧化了的表面。把氧化了的表面放在另一片的表面上。把两片加热以便使两片之间的氧化物把硅的器件片键合到支撑片上。利用常规技术把两片中的器件面减薄,使其厚度比最终要求的厚度稍微厚一些。下一步骤,把器件片形成图形、以便限定很多器件区域。在形成图形期间,从器件片的部分除掉硅,以便露出中间的氧化层。接着,在剩下硅和氧化层的整个表面上,均匀地淀积抛光停止层。应该知道,硅和抛光停止区会在氧化层上面延伸,而在氧化层上面仅仅存在抛光停止层。然后使器件片表面平面化,除掉抛光停止区和硅区,使器件片表面减薄到相应于抛光停止层厚度的均匀厚度。结果,最终的衬底将包括由抛光停止层隔开的单晶硅区。在适当厚的均匀氧化层上设置抛光停止层和硅层,氧化层本身由硅支撑片支撑。
通常,把硅器件片氧化键合到硅支撑片上。在氧化键合后,研磨器件片,以便在氧化层上面提供硅层。该研磨一般把硅器件片从大约600微米减薄到几微米。利用研磨和抛光机实现上述的研磨和抛光。
合成衬底有一个支撑片,一个厚度均匀的氧化层和可调厚度的硅器件层。于是把硅器件层形成图形,再用沟槽腐蚀方法把它进行腐蚀。在这种方法,用抗蚀剂图形掩蔽硅器件层,以便覆盖某些部分和露出另一部分。采用适当的腐蚀剂除掉硅层的露出的部分,然后,剥离掉剩下的抗蚀剂掩蔽层。然后使上表面刻成图形的氧化层上的硅淀积抛光停止层,典型地是氮化硅。然后化学地和机械地抛光氮化硅表面,以便充分地除掉硅,使剩下硅的厚度减薄到氮化硅的厚度。在本发明的最佳实施例中,设置在氧化层上的氮化硅层作为化学机械减薄操作的抛光停止层。
下面借助实施例,参考下列附图叙述本发明。
图1是薄片的部分剖面图。
图2是具有氧化层的薄片的部分剖面图。
图3是氧化键合到支撑片上的器件片的部分剖面图。
图4是按尺寸要求减薄器件片后图3薄片的部分剖面图。
图5是把器件层刻成图形后衬底的部分剖面图。
图6是淀积了均匀保护层的器件层的部分剖面图。
图7是平面化SOI片的部分剖面图。
图1表示一个单晶硅器件片14。该工艺中的初始步骤是在器件片14的一个表面上提供一个适当厚度的均匀氧化层12。通过在1150℃的蒸气环境经6小时的预定时间进行热氧化提供氧化表面12,以便在薄片14上提供大约1.8微米厚的氧化层。薄片14本身近似650微米厚。
下一步骤,把具有氧化层12的薄片14热键合到支撑片10上。支撑片10可以由硅制成,但是不需要器件级硅。通过把两片放在炉中,使之经受约1150℃,6小时,把片子14氧化键合到支撑片10上。以后,用研磨抛光机16,把硅片14的厚度减薄到如图4所示的薄层18。硅层18随衬底直径而变化。研磨和抛光机16只能使薄片14去掉硅到一定的厚度范围和允许一定程度的公差。例如,可以把层18减薄到几微米,但是从薄片一边到另一边的厚度本身可以变化几微米。
下一步骤,利用适合的可选择性除掉的抗蚀材料,使层18形成图形,以便提供掩蔽的表面图形和没有掩蔽的表面图形。利用适当的技术,例如氯气腐蚀掉没掩蔽的部分。结果,提供如图5所示的衬底。剩余硅层18的区域呈现为高于氧化层12的突出部分。突出部分18的高度从一个到另一个突出部分不断地变化。
参看图6,工艺中的下一步骤,包括淀积适当的抛光停止材料20,例如氮化硅。利用适当的众所周知的现有技术淀积氮化硅,以便提供均匀遍及衬底8表面的层20。应当注意,升高的硅部分18之间的凹陷处层20的厚度,通常实际上是平的和具有预定的厚度。然后,该氮化硅层20经受由适合的抛光机22进行化学和机械抛光加工。
淀积氮化硅层20约5000A°的厚度。该厚度对于最终薄片将成为一种可控制的厚度。在化学机械平面化步骤中,衬底20受到两种连续的抛光加工。第1种抛光加工本质上偏重于机械抛光(高压抛光)。所以,使用以工业用二氧化硅为基的磨料抛光浆,按体积经稀释为2∶1。超高压(大约23-27p.s.i)和磨料浆的结合提供了迅速磨掉氮化物和硅的抬高区域的方法。而且,在最初抛光时期,抛光填料是坚硬的,有利于磨掉氮化物层20。在预定时间后,减小机器的压力到大约5-10p.s.i,使抛光特性机械方面较少化学方面较多,因此,改善氮化物停上层和露出硅层之间的选择性。利用这种工艺,把硅层18减薄到位于氧化层12上面的氮化硅层一样的厚度。在减薄的后期,氮化硅层位于硅岛18之间和氧化层12的上面,实际上起到使第2次抛光加工的抛光停止作用。
上述工艺的结果,可能在绝缘体8上面获得具有独特特征的硅。该特征包括一厚度较厚,即比1微米厚的均匀氧化层,而最终的硅层相当的薄,即5000A°厚的数量级,而且均匀,即加或减200A°。在绝缘体上形成这种薄而均匀的硅层是非常希望的且体现本发明的重要技术优点。结果,本发明克服了现有技术的硅厚度易变的问题,又能制造出更一致的产品。对于支撑片,可以采用各种材料,只要它们能可靠的氧化键合到器件片14上。此外,不同的抛光停止层、腐蚀剂和浆料可以互相替换。
采用沟槽工艺和氮化硅层20,为硅岛18提供可控厚度和抛光停止层,在绝缘衬底8上形成的硅提供均匀厚度的硅岛18。
Claims (5)
1、一种在绝缘衬底上形成硅的方法,包括以下步骤:
提供支撑片和器件衬底,该支撑片有上表面和下表面,而器件片具有上表面和下表面,所述器件片的下表面相对地设置在所述支撑片的上面,一层氧化层设置在支撑片和器件片之间,将每片的相对表面粘接到各器件的相对表面上;
在器件片的上表面上形成多个不同厚度的多个器件区以限定随着竖起的侧壁的多个器件区,所述多个器件区是相互隔开的,而各个器件区有一个与氧化层接触的下表面,一个与氧化层隔开的上表面,一个由下表面延伸到上表面的竖起的侧壁,以及在器件区之间露出的部分的氧化层,且所述的上表面是至少两个器件区的厚度;
用有厚度的共形的连续不间断的氮化硅抛光停止层覆盖器件区和露出的氧化层,其中在露出的氧化层上的氮化硅停止抛光层厚度与抛光层的厚度一致;
在形成图形或移去氮化硅停止抛光层之前,以下述步骤进行平面化,所述步骤,基本上是抛光所述的连续不间断的抛光层和所述器件区至氧化层上的抛光层厚度;
其中所述的平面化步骤,基本上由以下步骤组成:在第一压力下除去器件区上的氮化硅停止抛光层,并除去器件区的侧壁上的抛光层,接着在小于第一压力的第二压力下抛光以减小器件区之间的厚度至器件之间的氮化硅停止抛光层的厚度、其中器件衬底厚度是减小到1至3微米小之间;所说抛光步骤包括在第一抛光压力下涂敷稀浆,接着,在第二抛光压力下涂敷稀浆。
2、根据权利要求1的方法,其中用于覆盖器件区和露出氧化层的氮化硅层是沉积的。
3、根据权利要求1的方法,其中,器件区是用化学和机械的方法除掉连续的不间断的氮化硅抛光停止层和部分的器件区,使器件区的厚度减薄到等于氮化硅抛光停止层的厚度而将器件区平面化的。
4、根据权利要求1的方法,其中沉积在器件区的氮化硅停止抛光层和覆盖的器件区是只用抛光除掉的。
5、根据权利要求1的方法,其中连续不间断的氮化硅停止抛光层是5000埃。
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Application Number | Priority Date | Filing Date | Title |
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US08/108,358 US5585661A (en) | 1993-08-18 | 1993-08-18 | Sub-micron bonded SOI by trench planarization |
US108,358 | 1993-08-18 |
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CN1115495A CN1115495A (zh) | 1996-01-24 |
CN1050929C true CN1050929C (zh) | 2000-03-29 |
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US (1) | US5585661A (zh) |
EP (1) | EP0639858A3 (zh) |
JP (1) | JPH07153725A (zh) |
KR (1) | KR950007015A (zh) |
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JPH07111962B2 (ja) * | 1992-11-27 | 1995-11-29 | 日本電気株式会社 | 選択平坦化ポリッシング方法 |
US6979632B1 (en) * | 1995-07-13 | 2005-12-27 | Semiconductor Energy Laboratory Co., Ltd. | Fabrication method for thin-film semiconductor |
KR100209365B1 (ko) * | 1995-11-01 | 1999-07-15 | 김영환 | 에스.오.아이 반도체 웨이퍼의 제조방법 |
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FR2812451B1 (fr) * | 2000-07-28 | 2003-01-10 | St Microelectronics Sa | Procede de fabrication d'un ensemble silicium sur isolant a ilots minces semi-conducteurs entoures d'un materiau isolant |
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US5071792A (en) * | 1990-11-05 | 1991-12-10 | Harris Corporation | Process for forming extremely thin integrated circuit dice |
JP2831745B2 (ja) * | 1989-10-31 | 1998-12-02 | 富士通株式会社 | 半導体装置及びその製造方法 |
US5091331A (en) * | 1990-04-16 | 1992-02-25 | Harris Corporation | Ultra-thin circuit fabrication by controlled wafer debonding |
JP2833305B2 (ja) * | 1991-12-05 | 1998-12-09 | 富士通株式会社 | 半導体基板の製造方法 |
US5262346A (en) * | 1992-12-16 | 1993-11-16 | International Business Machines Corporation | Nitride polish stop for forming SOI wafers |
US5264395A (en) * | 1992-12-16 | 1993-11-23 | International Business Machines Corporation | Thin SOI layer for fully depleted field effect transistors |
US5356513A (en) * | 1993-04-22 | 1994-10-18 | International Business Machines Corporation | Polishstop planarization method and structure |
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1993
- 1993-08-18 US US08/108,358 patent/US5585661A/en not_active Expired - Lifetime
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1994
- 1994-08-15 CA CA002130149A patent/CA2130149A1/en not_active Abandoned
- 1994-08-17 CN CN94115417A patent/CN1050929C/zh not_active Expired - Fee Related
- 1994-08-18 JP JP6194072A patent/JPH07153725A/ja active Pending
- 1994-08-18 KR KR1019940020414A patent/KR950007015A/ko active IP Right Grant
- 1994-08-18 EP EP94306088A patent/EP0639858A3/en not_active Withdrawn
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JPH01136328A (ja) * | 1987-11-20 | 1989-05-29 | Sony Corp | 半導体基板の製造方法 |
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JPH07153725A (ja) | 1995-06-16 |
CN1115495A (zh) | 1996-01-24 |
US5585661A (en) | 1996-12-17 |
EP0639858A2 (en) | 1995-02-22 |
CA2130149A1 (en) | 1995-02-19 |
KR950007015A (ko) | 1995-03-21 |
EP0639858A3 (en) | 1996-10-09 |
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