CN105159383A - Low dropout regulator with high power supply rejection ratio - Google Patents

Abstract

The invention belongs to the technical field of electronic circuits, and particularly to a low dropout regulator with a high power supply rejection ratio. A circuit provided by the invention can raise the stability of a loop by adopting a RC compensation method; at the same time raise the power supply rejection ratio of a regulator by introducing a high pass filter circuit, mainly utilizing the principle of negative feedback, introducing a feedforward path (the high pass filter circuit) between the power supply and a grid of a power tube, applying an output voltage of the circuit to the grid of the power tube so as to keep the voltage of the grid source of the power tube to be approximately constant, make the dropout of a small signal of a grid source of the power tube MP light greater than zero, and raise the power supply rejection of the whole circuit. The low dropout regulator with the high power supply rejection ratio can effectively raise the power supply rejection in the middle frequency range of LDR, and compensate in a chip at the same to make the chip easily integrated. The low dropout regulator with the high power supply rejection ratio is particularly suitable for a low-voltage stabilizing circuit.

Description

A kind of low pressure difference linear voltage regulator with high PSRR characteristic

Technical field

The invention belongs to electronic circuit technology field, relate to a kind of low pressure difference linear voltage regulator with high PSRR characteristic specifically.

Background technology

Low pressure difference linear voltage regulator (LowDropoutVoltageRegulator, LDR) as a part indispensable in present generation power supplies managing chip, its feature is the frequent switch motion not having BUCK in circuit working engineering, so the noise of LDR is very little; And the output voltage ripple of low pressure difference linear voltage regulator is little, circuit structure is simple, components and parts used are less, integrated rear chip area is little.The technical indicator of LDR mainly comprises: the response of pressure reduction, line regulation, load regulation, load current step and Power Supply Rejection Ratio (PowerSupplyRejectionRatio, PSRR) etc.

Fig. 1 is traditional LDR structural drawing.By error amplifier A ₁, PMOS P1, NMOS tube N1, power tube MP, resistance R1, R2, RL and electric capacity CP formed.Wherein error amplifier A ₁amplify the difference of reference voltage and output voltage, finally feed back to NMOS tube N1, thus the grid voltage of regulating power pipe, and then control the size to electric capacity CP discharge and recharge, reach the object of regulated output voltage.Power Supply Rejection Ratio is as a parameter of low pressure difference linearity voltage stabilizing, and it directly translates into the sensitivity of output voltage to power supply.

Mainly there are two shortcomings in this structure: the first, and this circuit adopts large electric capacity, is unfavorable for integrated.Along with the fast development of modern microelectronic technology, emerging in multitude of the integrated and SOC (system on a chip) (SystemOnChip, SOC) of chips get, this requires that chip is easy to integrated with the demand meeting social development.The second, Power Supply Rejection Ratio is lower.Such as, the LDR powered to radio circuit for some just needs very high power supply rejection ratio characteristics at medium-high frequency place, and this just requires that we improve the PSRR of medium-high frequency further.

Because LDR traditional at present adopts the method for off-chip compensation, the location comparison of its dominant pole is low, therefore there is circuit in the poor problem of the power supply rejection characteristic at high frequency place.

Summary of the invention

To be solved by this invention, be exactly for the problems referred to above, propose a kind of low pressure difference linear voltage regulator with high PSRR characteristic.

For achieving the above object, the present invention adopts following technical scheme:

Technical scheme of the present invention, a kind of low pressure difference linear voltage regulator with high PSRR characteristic, as shown in Figure 2, comprises high-pass filtering circuit, RC compensating circuit and output-stage circuit; Described high-pass filtering circuit is by the 5th PMOS P5, the 6th PMOS P6, the 7th PMOS P7, the second resistance R2, the 3rd resistance R3, the second electric capacity C2 and current source I ₁form; The source electrode of described 7th PMOS P7 connects power supply, its grid and drain interconnection, and its grid is by connecing the grid of the 6th PMOS P6 after the second resistance R2, excess current source I is connected in its drain electrode ₁rear ground connection; Current source I ₁in parallel with the 3rd resistance R3; The tie point of the second resistance R2 and the 6th PMOS P6 grid is by ground connection after the second electric capacity C2; The source electrode of the 6th PMOS P6 connects power supply, and its drain electrode connects the source electrode of the 5th PMOS P5; 5th PMOS P5 misses ground;

Described RC compensating circuit is by error amplifier A ₁, the first resistance R1 and the first electric capacity C1 forms; Error amplifier A ₁the grid of output termination the 5th PMOS P5, its positive input is successively by connecing the grid of the 5th PMOS P5 after the first resistance R1 and the first electric capacity C1, its negative input connects reference voltage;

Described output-stage circuit is made up of power tube PMOS MP, the 3rd resistance C3 and the 4th resistance R4; The grid of power P OMS pipe MP connects the tie point of the 6th PMOS P6 drain electrode and the 5th PMOS P5 source electrode, and its source electrode connects power supply, and its drain electrode meets error amplifier A ₁positive input; Power tube PMOS MP drain electrode and error amplifier A ₁the tie point of positive input is by ground connection after the 3rd electric capacity C3; 3rd electric capacity C3 and the 4th resistance R4 is in parallel.

Further, described error amplifier A ₁be made up of the first PMOS P1, the second PMOS P2, the 3rd PMOS P3, the 4th PMOS P4, the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4 and the 5th NMOS tube N5; The grid of the 3rd NMOS tube N3 is error amplifier A ₁positive input, its source electrode connects the drain electrode of the 5th NMOS tube N5 and the source electrode of the 4th NMOS tube N4, and its drain electrode connects the source electrode of the second PMOS P2 and the drain electrode of the 4th PMOS P4; The grid of the 4th NMOS tube N4 is error amplifier A ₁negative input, its drain electrode connects the drain electrode of the 3rd PMOS P3 and the source electrode of the first PMOS P1; The grid of the 5th NMOS tube N5 is error amplifier A ₁output terminal, its source ground; The source electrode of the 3rd PMOS P3 connects power supply, and its grid connects the grid of the 4th PMOS P4; The source electrode of the 4th PMOS P4 connects power supply; The grid of the first PMOS P1 connects the grid of the second PMOS P2, and its drain electrode connects the drain electrode of the first NMOS tube N1; The drain electrode of the second PMOS P2 connects the drain electrode of the second NMOS tube N2; The grid of the second NMOS tube N2 and drain interconnection, its grid connects the grid of the first NMOS tube N1, its source ground; The source ground of the first NMOS tube N1.

Beneficial effect of the present invention is, effectively can improve the power supply rejection ability of LDR Mid Frequency, adopts the method compensated in sheet simultaneously, chip is easier to integrated.

Accompanying drawing explanation

Fig. 1 is traditional LDR basic structure schematic diagram;

Fig. 2 is the structural representation of LDR of the present invention;

Fig. 3 is error amplifier A of the present invention ₁schematic diagram;

Fig. 4 is the contrast schematic diagram not having high-pass filtering circuit He have high-pass filtering circuit circuit.

Embodiment

A kind of low pressure difference linear voltage regulator with high PSRR characteristic of the present invention, as shown in Figure 2, comprises high-pass filtering circuit, RC compensating circuit and output-stage circuit; Described high-pass filtering circuit is by the 5th PMOS P5, the 6th PMOS P6, the 7th PMOS P7, the second resistance R2, the 3rd resistance R3, the second electric capacity C2 and current source I ₁form; The source electrode of described 7th PMOS P7 connects power supply, its grid and drain interconnection, and its grid is by connecing the grid of the 6th PMOS P6 after the second resistance R2, excess current source I is connected in its drain electrode ₁rear ground connection; Current source I ₁in parallel with the 3rd resistance R3; The tie point of the second resistance R2 and the 6th PMOS P6 grid is by ground connection after the second electric capacity C2; The source electrode of the 6th PMOS P6 connects power supply, and its drain electrode connects the source electrode of the 5th PMOS P5; 5th PMOS P5 misses ground;

Described RC compensating circuit is by error amplifier A ₁, the first resistance R1 and the first electric capacity C1 forms; Error amplifier A ₁the grid of output termination the 5th PMOS P5, its positive input is successively by connecing the grid of the 5th PMOS P5 after the first resistance R1 and the first electric capacity C1, its negative input connects reference voltage;

Described output-stage circuit is made up of power tube PMOS MP, the 3rd resistance C3 and the 4th resistance R4; The grid of power P OMS pipe MP connects the tie point of the 6th PMOS P6 drain electrode and the 5th PMOS P5 source electrode, and its source electrode connects power supply, and its drain electrode meets error amplifier A ₁positive input; Power tube PMOS MP drain electrode and error amplifier A ₁the tie point of positive input is by ground connection after the 3rd electric capacity C3; 3rd electric capacity C3 and the 4th resistance R4 is in parallel.

As shown in Figure 3, described error amplifier A ₁be made up of the first PMOS P1, the second PMOS P2, the 3rd PMOS P3, the 4th PMOS P4, the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4 and the 5th NMOS tube N5; The grid of the 3rd NMOS tube N3 is error amplifier A ₁positive input, its source electrode connects the drain electrode of the 5th NMOS tube N5 and the source electrode of the 4th NMOS tube N4, and its drain electrode connects the source electrode of the second PMOS P2 and the drain electrode of the 4th PMOS P4; The grid of the 4th NMOS tube N4 is error amplifier A ₁negative input, its drain electrode connects the drain electrode of the 3rd PMOS P3 and the source electrode of the first PMOS P1; The grid of the 5th NMOS tube N5 is error amplifier A ₁output terminal, its source ground; The source electrode of the 3rd PMOS P3 connects power supply, and its grid connects the grid of the 4th PMOS P4; The source electrode of the 4th PMOS P4 connects power supply; The grid of the first PMOS P1 connects the grid of the second PMOS P2, and its drain electrode connects the drain electrode of the first NMOS tube N1; The drain electrode of the second PMOS P2 connects the drain electrode of the second NMOS tube N2; The grid of the second NMOS tube N2 and drain interconnection, its grid connects the grid of the first NMOS tube N1, its source ground; The source ground of the first NMOS tube N1.

Principle of work of the present invention is: error amplifier A ₁amplify the difference of reference voltage and output voltage, feed back to PMOS MP by the source follower of PMOS P5, P6 composition, thus the grid voltage of regulating power pipe, reach the object of regulated output voltage.In order to improve the Power Supply Rejection Ratio of LDR, introduce high-pass filtering circuit, thus improve the Power Supply Rejection Ratio in wherein high-frequency range.

For convenience of description, at this to hereinafter the unknown parameter of appearance and symbol being specified as follows:

Adopt gmNi and rNi to represent mutual conductance and the output resistance of NMOS tube Ni respectively, wherein i is the numbering of NMOS tube; Adopt gmPj and rPj to represent mutual conductance and the output resistance of PMOS Pj respectively, wherein j is the numbering of PMOS; Adopt Ak (s) to represent the transition function of operational amplifier, wherein k is the numbering of operational amplifier;

As shown in Figure 1, the Power Supply Rejection Ratio formula of traditional LDR can obtain the following derivation of small-signal relational expression do of circuit according to Kirchhoff's law:

$\frac{v_G}{r_{N1}}-A_0\left(s\right)g_{mN1}{v}_{fb}=(\frac{1}{r_{P1}}+g_{mP1})(v_{dd}-v_G)---\left(1\right)$

$g_{MP}(v_{dd}-v_G)=\frac{v_{out}}{Z_{out}}---\left(2\right)$

$v_{fb}=\frac{R_2}{R_1+R_2}{v}_{out}---\left(3\right)$

Wherein: vG is the grid voltage of power tube MP; Vdd is the small signal of power supply; Vfb is sampled voltage; Zout is output node equiva lent impedance, g _mPit is the mutual conductance of power tube MP; Vout is output voltage, R1 and R2 is divider resistance.

According to definition and formula (1) ~ (3) of Power Supply Rejection Ratio PSRR:

$PSRR=\frac{g_{MP}{z}_{out}}{g_{mP1}{r}_{N1}}\frac{1}{1+\frac{R_2}{R_1+R_2}{A}_0\left(s\right)\frac{g_{mN1}}{g_{mP1}}{g}_{MP}{Z}_{out}}---\left(4\right)$

Wherein: the equiva lent impedance at output node place r _lit is pull-up resistor; S is the angular frequency under complex frequency domain; c _pit is load capacitance; R ₁and R ₂it is divider resistance; g _mPand r _dsfor power tube MP mutual conductance and output resistance.

The influence factor of Power Supply Rejection Ratio very clearly can be understood, convenient like this design from formula (4).To derive below the correlation properties of Power Supply Rejection Ratio PSRR of the present invention.

As shown in Figure 2, in low differential voltage linear voltage stabilizer circuit of the present invention, if the voltage of node is respectively v ₁, v ₂, v ₃, v ₄, obtaining small-signal formula is:

$\frac{v_{out}{A}_0\left(s\right)-v_1}{R_A}+(v_{out}-v_1)\frac{{\mathrm{sC}}_1}{1+{\mathrm{sR}}_1{C}_1}=0---\left(5\right)$

$g_{mp5}(v_2-v_1)+\frac{v_2}{r_{p5}}+\frac{v_2-vdd}{r_{p6}}+g_{mp6}(v_4-vdd)+(v_2-vdd){\mathrm{sC}}_{gs}+(v_2-v_{out}){\mathrm{sC}}_{gd}=0---\left(6\right)$

$g_{mp7}(v_3-vdd)+\frac{v_3}{R_3}=\frac{v_4-v_3}{R_2}---\left(7\right)$

$\frac{v_4-v_3}{R_2}+v_4{\mathrm{sC}}_2=0---\left(8\right)$

$g_{MP}(v_2-vdd)+\frac{v_{out}}{R_4}+\frac{v_{out}-vdd}{r_{MP}}+v_{out}{\mathrm{sC}}_4+(v_{out}-v_1)\frac{{\mathrm{sC}}_1}{1+{\mathrm{sR}}_1{C}_1}=(v_2-v_{out}){\mathrm{sC}}_{gd}---\left(9\right)$

Wherein: vdd is power supply small signal; Vout is output voltage; c ₁it is building-out capacitor; g _mPand r _mPmutual conductance and the output resistance of power tube MP respectively; S is the angular frequency under complex frequency domain; C _gdit is the stray capacitance between power tube MP grid and drain electrode; C _gsit is the stray capacitance between power tube MP grid and source electrode; A ₁s () is error amplifier A ₁transition function; R _aerror amplifier A ₁the output resistance R of equivalence ₄it is pull-up resistor; C ₄it is load capacitance.

The Power Supply Rejection Ratio being obtained LDR of the present invention by formula (5) ~ (9) is:

$PSRR=\frac{1}{A_1\left(s\right)}\frac{1+\frac{C_2{R}_2(g_{m5}-g_{m6})+C_1(R_1+R_A)g_{m5}}{g_{m5}}s+\frac{C_1{C}_2(g_{m5}-g_{m6})(R_1+R_A)R_2}{g_{m5}}{s}^2}{1+(C_2{R}_2+C_1{R}_1)s+\frac{C_1{R}_1(C_2{R}_2{g}_{MP}-C_{gd})}{g_{MP}}{s}^2-\frac{C_2{C}_1{C}_{gd}{R}_1{R}_2}{g_{MP}}{s}^3}---\left(10\right)$

As shown in Figure 4, simulation result display of the present invention: in circuit, output capacitance is 50pF, much smaller relative to the electric capacity of 4.7 μ F used by general off-chip compensation, be easier to integrated like this, and total quiescent current is 24.2 μ A, reaches object of the present invention.As shown in Figure 4, it is the simulation result of OCL output capacitance-less type high mains rejection ratio low dropout voltage voltage stabilizer under different loading conditions, can find out within the scope of medium-high frequency 10K-10MHz from simulation result, Power Supply Rejection Ratio obtains good improvement, can about 36.9dB be improved at 1MHz place, improve the PSRR of medium-high frequency.

Claims (2)

1. there is a low pressure difference linear voltage regulator for high PSRR characteristic, comprise high-pass filtering circuit, RC compensating circuit and output-stage circuit; Described high-pass filtering circuit is by the 5th PMOS P5, the 6th PMOS P6, the 7th PMOS P7, the second resistance R2, the 3rd resistance R3, the second electric capacity C2 and current source I ₁form; The source electrode of described 7th PMOS P7 connects power supply, its grid and drain interconnection, and its grid is by connecing the grid of the 6th PMOS P6 after the second resistance R2, excess current source I is connected in its drain electrode ₁rear ground connection; Current source I ₁in parallel with the 3rd resistance R3; The tie point of the second resistance R2 and the 6th PMOS P6 grid is by ground connection after the second electric capacity C2; The source electrode of the 6th PMOS P6 connects power supply, and its drain electrode connects the source electrode of the 5th PMOS P5; 5th PMOS P5 misses ground;

Described RC compensating circuit is by error amplifier A ₁, the first resistance R1 and the first electric capacity C1 forms; Error amplifier A ₁the grid of output termination the 5th PMOS P5, its positive input is successively by connecing the grid of the 5th PMOS P5 after the first resistance R1 and the first electric capacity C1, its negative input connects reference voltage;

Described output-stage circuit is made up of power tube PMOS MP, the 3rd resistance C3 and the 4th resistance R4; The grid of power P OMS pipe MP connects the tie point of the 6th PMOS P6 drain electrode and the 5th PMOS P5 source electrode, and its source electrode connects power supply, and its drain electrode meets error amplifier A ₁positive input; Power tube PMOS MP drain electrode and error amplifier A ₁the tie point of positive input is by ground connection after the 3rd electric capacity C3; 3rd electric capacity C3 and the 4th resistance R4 is in parallel.

2. a kind of low pressure difference linear voltage regulator with high PSRR characteristic according to claim 1, is characterized in that, described error amplifier A ₁be made up of the first PMOS P1, the second PMOS P2, the 3rd PMOS P3, the 4th PMOS P4, the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4 and the 5th NMOS tube N5; The grid of the 3rd NMOS tube N3 is error amplifier A ₁positive input, its source electrode connects the drain electrode of the 5th NMOS tube N5 and the source electrode of the 4th NMOS tube N4, and its drain electrode connects the source electrode of the second PMOS P2 and the drain electrode of the 4th PMOS P4; The grid of the 4th NMOS tube N4 is error amplifier A ₁negative input, its drain electrode connects the drain electrode of the 3rd PMOS P3 and the source electrode of the first PMOS P1; The grid of the 5th NMOS tube N5 is error amplifier A ₁output terminal, its source ground; The source electrode of the 3rd PMOS P3 connects power supply, and its grid connects the grid of the 4th PMOS P4; The source electrode of the 4th PMOS P4 connects power supply; The grid of the first PMOS P1 connects the grid of the second PMOS P2, and its drain electrode connects the drain electrode of the first NMOS tube N1; The drain electrode of the second PMOS P2 connects the drain electrode of the second NMOS tube N2; The grid of the second NMOS tube N2 and drain interconnection, its grid connects the grid of the first NMOS tube N1, its source ground; The source ground of the first NMOS tube N1.