CN105226026A - A kind of method making semiconductor device - Google Patents
A kind of method making semiconductor device Download PDFInfo
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- CN105226026A CN105226026A CN201410276467.9A CN201410276467A CN105226026A CN 105226026 A CN105226026 A CN 105226026A CN 201410276467 A CN201410276467 A CN 201410276467A CN 105226026 A CN105226026 A CN 105226026A
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Abstract
The invention discloses a kind of method making semiconductor device, comprise: Semiconductor substrate is provided, be formed with multiple gate stack structure on the semiconductor substrate, and the source region formed in described Semiconductor substrate between described multiple gate stack structure and drain region; Form metal level on the semiconductor substrate, to fill the gap between described multiple gate stack structure; Perform flatening process, flush to make the top of described metal level and described gate stack structure; Return etching removal part and be positioned at described metal level on described drain region, to expose described Semiconductor substrate; Form dielectric layer on the semiconductor substrate, to cover the described Semiconductor substrate exposed; Wherein, be positioned at remaining described metal level on described drain region and form the drain contact be isolated from each other.Can, according to the compatibility that manufacture method of the present invention be good with silicification technics, finally improve ETOX? the overall performance of NOR type flash memories and yields.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of method making semiconductor device.
Background technology
Memory, for storing a large amount of digital information, shows recently according to investigations, and worldwide, memory chip approximately account for 30% of semiconductor transaction.For many years, the progress of technology and the market demand have expedited the emergence of more and more highdensity all kinds memory, as RAM (random asccess memory), SRAM (static random access memory), DRAM (dynamic random access memory) and FRAM (ferroelectric memory) etc.Wherein, flash memories and FLASH, even if still can retention tab internal information after power supply is closed owing to having; At memory electric erasable and can not need special high voltage during overprogram; And the feature such as cost is low, density is large, become the main flow of non-volatile semiconductor storage technology.The performance of its uniqueness makes it apply to every field widely, comprise embedded system, as PC and equipment, telecommunications switch, cell phone, network interconnection apparatus, network interconnection, instrument and meter and automobile device, also comprise emerging voice, image, data storage series products simultaneously.
Along with the development of ETOX (ElectronTunnelingOxide: electron tunneling oxide) or/no type flash memory (NORFlash) memory technology, for more advanced technology node, the interlayer dielectric layer filling capacity improved between gate stack structure becomes the significant challenge faced at present.Cavity in interlayer dielectric layer can cause the bridge joint between drain contact, therefore must adopt the method with high filling capacity at present, and such as, FCVD method performs the filling of interlayer dielectric layer.
Therefore, a kind of method of making semiconductor device is newly badly in need of, to solve the problem.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of method making semiconductor device, comprise: Semiconductor substrate is provided, be formed with multiple gate stack structure on the semiconductor substrate, and the source region formed in described Semiconductor substrate between described multiple gate stack structure and drain region; Form metal level on the semiconductor substrate, to fill the gap between described multiple gate stack structure; Perform flatening process, flush to make the top of described metal level and described gate stack structure; Return etching removal part and be positioned at described metal level on described drain region, to expose described Semiconductor substrate; Form dielectric layer on the semiconductor substrate, to cover the described Semiconductor substrate exposed; Wherein, be positioned at remaining described metal level on described drain region and form the drain contact be isolated from each other.
Exemplarily, flatening process is performed, to expose the step of described gate stack structure and described metal level after being also included in the described dielectric layer of formation.
Exemplarily, the material of described metal level is tungsten.
Exemplarily, the both sides of described gate stack structure are also formed with side wall.
Exemplarily, described gate stack structure comprises tunnel oxide, floating boom, gate dielectric layer, control gate and hard mask layer from below to up successively.
Exemplarily, described semiconductor device is NOR type flash memory.
Exemplarily, form described metal level on the semiconductor substrate before be also included in the step described source region and drain region being formed metal silicide.
Exemplarily, form described dielectric layer on the semiconductor substrate after do not need step that described dielectric layer is heat-treated.
In sum, manufacture method according to the present invention can not produce the bridge joint between drain contact in the ETOXNOR type flash memories formed, do not need to adopt the fill method with high filling capacity, do not need to adopt interlayer dielectric layer described in the high temperature anneal yet, and manufacture method of the present invention more can be good with silicification technics compatibility, final overall performance and the yields improving ETOXNOR type flash memories.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
The cross-sectional view that Figure 1A-1D obtains for a kind of ETOXNOR of making type flush memory device correlation step;
The plan structure schematic diagram that Fig. 2 A-2D obtains for a kind of ETOXNOR of making type flush memory device correlation step;
The cross-sectional view of the device that Fig. 3 A-3D obtains for the correlation step making ETOXNOR type flush memory device according to one embodiment of the present invention;
The plan structure schematic diagram of the device that Fig. 4 A-4D obtains for the correlation step making ETOXNOR type flush memory device according to one embodiment of the present invention;
Fig. 5 is the process chart making ETOXNOR type flush memory device according to one embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it will be apparent to one skilled in the art that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to illustrate how the present invention solves the problems of the prior art.Detailed being described below of obvious preferred embodiment of the present invention, but remove outside these detailed descriptions, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
Figure 1A-1D is a kind of cross-sectional view making ETOXNOR type flush memory device, and Fig. 2 A-2D is the plan structure schematic diagram corresponding to Figure 1A-1D.As shown in figs. la and 2, form multiple gate stack structure 101 on a semiconductor substrate 100, gate stack structure 101 comprises the tunnel oxide 102 be positioned in Semiconductor substrate 100, and the floating boom 103 be positioned on described tunnel oxide 102 and control gate 104, wherein floating boom 103 and control gate 104 carry out electric isolation by gate dielectric layer 105, also comprise the side wall 106 being positioned at gate stack structure 101 both sides in described Semiconductor substrate 100, the source region 107 formed in described Semiconductor substrate 100 between described multiple gate stack structure and drain region 108, also comprise the hard mask layer 109 be positioned on control gate 104.
As shown in figs. ib and 2b, in described Semiconductor substrate 100, deposition forms interlayer dielectric layer 110, and described interlayer dielectric layer 110 fills the space between gate stack structure 101, then, perform flatening process, expose gate stack structure 101 to get rid of unnecessary interlayer dielectric layer 110.
As shown in Fig. 1 C and 2C, adopt photoetching process etching to remove the interlayer dielectric layer 110 that is positioned on source region 107 and removal part and be positioned at interlayer dielectric layer 110 on drain region 108 to expose described Semiconductor substrate 100, after the described etch step of execution, on described drain region 108, form contact hole 111.
As shown in Fig. 1 D and 2D, form metal tungsten layer 112 on the semiconductor substrate, described metal tungsten layer 112 is filled described contact hole 111 and is covered described source region 107, then, performs flatening process to expose remaining interlayer dielectric layer 110.
According to the ETOXNOR type flash memory device structure that said method makes, the cavity be easy in generation interlayer dielectric layer causes the bridge joint between drain contact, affects performance and the yields of device.
In the present invention in order to solve the defect existed in prior art, the present invention proposes a kind of technique of making ETOXNOR type flash memories newly, by described method to solve the drawback existed in prior art.
Below in conjunction with Fig. 3 A-3D and Fig. 4 A-4D, the manufacture method of ETOXNOR type flash memories of the present invention is described in detail, the sectional structure schematic diagram of the device that Fig. 3 A-3D obtains for the correlation step making ETOXNOR type flash memory device structure, Fig. 4 A-4D is the plan structure schematic diagram of the device of the correlation step corresponding to Fig. 3 A-3D.
As shown in figures 3 a and 4, Semiconductor substrate 300 is formed multiple gate stack structure 301, gate stack structure 301 comprises the tunnel oxide 302 be positioned in Semiconductor substrate 300, floating boom 303, control gate 304 and hard mask layer 305 from below to up successively, wherein floating boom 303 and control gate 304 carry out electric isolation by gate dielectric layer 306, be positioned at the side wall 307 of gate stack structure 301 both sides in described Semiconductor substrate 300, the source region 308 in the described Semiconductor substrate 300 between described multiple gate stack structure 301 and drain region 309.The concrete technology step forming the multiple gate stack structure of above-mentioned NOR type flush memory device is as follows:
There is provided Semiconductor substrate 300, Semiconductor substrate can comprise any semi-conducting material, and this semi-conducting material can include but not limited to: Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V or group Ⅱ-Ⅵ compound semiconductor.
In a specific embodiment of the present invention, described Semiconductor substrate is P type semiconductor substrate, adopts boron ion implantation technology and thermal diffusion trap to push away technique and form P trap in described P type semiconductor substrate.
Then, described Semiconductor substrate 300 forms tunnel oxide 302, the material of tunnel oxide can be silica, the method forming tunnel oxide is thermal oxidation method, the thickness of the tunnel oxide formed is right at tens Izods, in one example, the thickness of described tunnel oxide is 80 dust to 110 dusts.
Described tunnel oxide 302 forms gate material layers, and gate material layers can comprise each material, and described each material is including but not limited to some metal, metal alloy, metal nitride and metal silicide, and laminate and its compound.Gate material layers also can comprise the polysilicon of doping and polysilicon-Ge alloy material and polycide material (polysilicon/metal silicide laminated material of doping).Similarly, any one the formation previous materials in several methods can also be adopted.Limiting examples comprises chemical gaseous phase depositing process and physical gas-phase deposite method, and the material of gate material layers is polysilicon layer in the present embodiment.
Etch described gate material layers and tunnel oxide 302, with the tunnel oxide 302 forming floating boom 303 and be positioned at below floating boom 303 in Semiconductor substrate 300.
Then, described floating boom 303 forms gate dielectric layer 306, described gate dielectric layer 306 can be ONO dielectric layer.Concrete, gate dielectric layer 306 can be oxidenitride oxide three layers of ONO sandwich structure altogether, those skilled in the art should be understood that, gate dielectric layer 306 also can for one deck nitride or one deck oxide or one deck nitride form the insulation systems such as one deck oxide.Can use and include but not limited to: the method for low-pressure chemical vapor deposition method, chemical gaseous phase depositing process and physical vapor deposition methods forms gate dielectric layer 306.Because of flash memories, to require the gate dielectric layer contacted with floating grid to possess good electrical, to avoid under normal voltage, being used for the floating grid of stored charge there is electric leakage or crosses the problem of earlier collapse, ONO for the material of gate dielectric layer 306, the uniform silicon oxide layer of one deck is formed with low-pressure chemical vapor deposition method, then, on silicon oxide layer, silicon nitride layer is formed with low-pressure chemical vapor deposition method, then, then with low-pressure chemical vapor deposition method form another layer of silicon oxide layer.
Gate dielectric layer 306 is formed another gate material layers, and gate material layers can comprise each material, and described each material is including but not limited to some metal, metal alloy, metal nitride and metal silicide, and laminate and its compound.Gate material layers also can comprise the polysilicon of doping and polysilicon-Ge alloy material and polycide material (polysilicon/metal silicide laminated material of doping).Similarly, any one formation previous materials of several methods can also be adopted.Limiting examples comprises chemical gaseous phase depositing process and physical gas-phase deposite method, and the material of gate material layers is polysilicon layer in the present embodiment.
The formation method of polysilicon can select low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions forming described polysilicon comprise: reacting gas is silane (SiH
4), the range of flow of described silane can be 100 ~ 200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700 ~ 750 degrees Celsius; Reaction chamber internal pressure can be 250 ~ 350 millimetress of mercury (mTorr), as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium or nitrogen, and the range of flow of described helium and nitrogen can be 5 ~ 20 liters/min (slm), as 8slm, 10slm or 15slm.
Exemplary, need to carry out pre-doping technique to gate material layers according to technique, impurity can be phosphorus, arsenic, boron, BF2 etc.
Exemplarily, described gate material layers forms hard mask layer 305, hard mask layer 305 material comprises silicon nitride, oxide, silicon oxynitride or amorphous carbon.Wherein, hard mask layer 305 comprises one or several in silicon nitride layer, oxide skin(coating), silicon oxynitride layer or amorphous carbon layer.Plasma reinforced chemical vapour deposition (PECVD) can be adopted to form silicon nitride layer, oxide skin(coating), silicon oxynitride layer, amorphous carbon layer or high temperature oxide layer (HTO).
Hard mask layer 305, described gate material layers described in patterning and the stacked structure be positioned at below described gate material layers, wherein said gate material layers for the formation of control gate, to form the gate stack structure 301 be jointly made up of hard mask layer 305, control gate 304, gate dielectric layer 306, floating boom 303 and tunnel oxide 302 in described Semiconductor substrate 300.
In the present invention one specific embodiment, described hard mask layer 305 is formed the mask of patterning, the mask of described patterning can be the photoresist layer of patterning, the mask of described patterning defines position, the length and width etc. of gate stack structure 301, hard mask layer 305, described gate material layers and the stacked structure that is positioned at below described gate material layers according to the mask etching of patterning, to form gate stack structure.
Then, for mask, ion doping injection is carried out to described Semiconductor substrate with described gate stack structure 301, to form source region 308 and drain region 309 in the Semiconductor substrate 300 of described gate stack structure 301 both sides.The technical process forming source-drain area is had the knack of for those skilled in the art, is not just described in detail, any applicable method can be adopted to form described source region 308 and drain region 309 at this.
As illustrated by figs. 3 b and 4b, in described Semiconductor substrate 300, deposition forms metal level 310, to fill the gap between described multiple gate stack structure 301, cover described source region 308 and described drain region 309, wherein, the material of metal level 310 can elect tungsten as, and tungsten has good filling capacity and is usually used in the filling of contact hole.Metal level 310 cover gate laminated construction 301 and the space be filled with between gate stack structure 301.
Exemplarily, described Semiconductor substrate 300 forms described metal level 310 before be also included in the step described source region 308 and drain region 309 being formed metal silicide.The step that source region and drain region are formed metal silicide is the technological means known for a person skilled in the art, is not just described in detail, any applicable method can be adopted to form described metal silicide at this.
Then, perform flatening process to remove unnecessary metal level 310, to expose gate stack structure 301, gate stack structure 301 and remaining metal level 310 top flush.
Flattening method conventional in field of semiconductor manufacture can be used to realize the planarization on surface.The limiting examples of this flattening method comprises mechanical planarization method and chemico-mechanical polishing flattening method.
As illustrated by figs. 3 c and 4 c, return the metal level 310 be positioned on drain region 309 of etching removal part, to expose described Semiconductor substrate 300, exemplarily, be positioned at remaining described metal level 310 on described drain region 309 and form the drain contact be isolated from each other.
Described time etching technics can adopt wet etching or dry etching.In a specific embodiment of the present invention, dry etching can be adopted to perform back etching technics, and dry method etch technology includes but not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Such as using plasma etching, etching gas can adopt based on oxygen (O
2-based) gas.Concrete, adopt lower radio-frequency (RF) energy also can produce low pressure and highdensity plasma gas to realize dry etching.As an example, using plasma etching technics, the etching gas of employing is based on oxygen (O
2-based) gas, the range of flow of etching gas can be 50 cc/min (sccm) ~ 150 cc/min (sccm), and reative cell internal pressure can be 5 millitorrs (mTorr) ~ 20 millitorr (mTorr).Wherein, the etching gas of dry etching can also be bromize hydrogen gas, carbon tetrafluoride gas or gas of nitrogen trifluoride.It should be noted that above-mentioned engraving method is only exemplary, be not limited to the method, those skilled in the art can also select other conventional methods.
As shown in Fig. 3 D and 4D, described Semiconductor substrate 300 forms dielectric layer 311, the Semiconductor substrate 300 that dielectric layer 311 cover gate laminated construction 301 and covering are exposed, then, perform flatening process and remove the dielectric layer 311 be positioned on gate stack structure 301, flush to make the top of remaining dielectric layer 311 and gate stack structure 301 (or metal level 310).Exemplarily, remaining dielectric layer 311, for isolating the metal level 310 be positioned on drain region 309, is equivalent to dielectric layer 311 for isolating drain contact.
The material of dielectric layer 311 can be SiO
2, Si
3n
4, SiON, SiON
2, and comprise other similar oxide of perofskite type oxide.Dielectric layer 311 can pass through chemical vapour deposition (CVD) (CVD) technique and be formed.Wherein, described Semiconductor substrate 300 forms described dielectric layer 311 after do not need step that described dielectric layer 311 is heat-treated.Because the present invention does not need to adopt FCVD etc. to have the fill method of high filling capacity to form described dielectric layer, therefore just do not need to adopt high annealing to process described dielectric layer yet, would not cause damage to the metal silicide formed on source-drain area before yet.
With reference to Fig. 5, illustrated therein is the process chart into making ETOXNOR type flash memory device structure according to one embodiment of the present invention.For schematically illustrating the flow process of whole manufacturing process.
In step 501, Semiconductor substrate is provided, form multiple gate stack structure on a semiconductor substrate, gate stack structure comprises tunnel oxide, floating boom, gate dielectric layer, control gate and hard mask layer from below to up successively, be positioned at the side wall of gate stack structure both sides in described Semiconductor substrate, be positioned at source region and the drain region of side wall both sides described in described Semiconductor substrate;
In step 502, deposition forms metal level on the semiconductor substrate, performs flatening process to expose described gate stack structure;
In step 503, return etching removal part and be positioned at described metal level on described drain region to expose described Semiconductor substrate;
In step 504, deposition forms dielectric layer to isolate remaining metal level on the semiconductor substrate.
In sum, manufacture method according to the present invention can not produce the bridge joint between drain contact in the ETOXNOR type flash memories formed, do not need to adopt the fill method with high filling capacity, do not need to adopt interlayer dielectric layer described in the high temperature anneal yet, and manufacture method of the present invention more can be good with silicification technics compatibility, final overall performance and the yields improving ETOXNOR type flash memories.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to the present invention, within these variants and modifications all drop on the present invention's scope required for protection.
Claims (8)
1. make a method for semiconductor device, comprising:
Semiconductor substrate is provided, is formed with multiple gate stack structure on the semiconductor substrate, and the source region formed in described Semiconductor substrate between described multiple gate stack structure and drain region;
Form metal level on the semiconductor substrate, to fill the gap between described multiple gate stack structure;
Perform flatening process, flush to make the top of described metal level and described gate stack structure;
Return etching removal part and be positioned at described metal level on described drain region, to expose described Semiconductor substrate;
Form dielectric layer on the semiconductor substrate, to cover the described Semiconductor substrate exposed;
Wherein, be positioned at remaining described metal level on described drain region and form the drain contact be isolated from each other.
2. the method for claim 1, is characterized in that, is also included in after forming described dielectric layer and performs flatening process, to expose the step of described gate stack structure and described metal level.
3. the method for claim 1, is characterized in that, the material of described metal level is tungsten.
4. the method for claim 1, is characterized in that, the both sides of described gate stack structure are also formed with side wall.
5. the method for claim 1, is characterized in that, described gate stack structure comprises tunnel oxide, floating boom, gate dielectric layer, control gate and hard mask layer from below to up successively.
6. the method for claim 1, is characterized in that, described semiconductor device is NOR type flash memory.
7. the method for claim 1, is characterized in that, is also included in the step described source region and drain region being formed metal silicide before forming described metal level on the semiconductor substrate.
8. the method for claim 1, is characterized in that, does not need the step of heat-treating described dielectric layer after forming described dielectric layer on the semiconductor substrate.
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| US6512263B1 (en) * | 2000-09-22 | 2003-01-28 | Sandisk Corporation | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming |
| CN1536670A (en) * | 2003-04-03 | 2004-10-13 | 力晶半导体股份有限公司 | Flash memory unit with selective grid positioned in substrate and its making method |
| CN1536672A (en) * | 2003-04-03 | 2004-10-13 | 力晶半导体股份有限公司 | Flash memory and its making method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6512263B1 (en) * | 2000-09-22 | 2003-01-28 | Sandisk Corporation | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming |
| CN1536670A (en) * | 2003-04-03 | 2004-10-13 | 力晶半导体股份有限公司 | Flash memory unit with selective grid positioned in substrate and its making method |
| CN1536672A (en) * | 2003-04-03 | 2004-10-13 | 力晶半导体股份有限公司 | Flash memory and its making method |
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