CN105612582A - Independently addressable memory array address spaces - Google Patents

Independently addressable memory array address spaces Download PDF

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Publication number
CN105612582A
CN105612582A CN201480054681.8A CN201480054681A CN105612582A CN 105612582 A CN105612582 A CN 105612582A CN 201480054681 A CN201480054681 A CN 201480054681A CN 105612582 A CN105612582 A CN 105612582A
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line
address space
memory cell
coupled
address
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Granted
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CN201480054681.8A
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CN105612582B (en
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卓依·A·曼宁
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Micron Technology Inc
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Micron Technology Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7202—Allocation control and policies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.

Description

Independently addressable memory array address space
Technical field
The present invention relates generally to semiconductor memory devices and method, and more particularly, the present invention relates to can be independentThe relevant Apparatus and method in memory array address space of addressing.
Background technology
Storage arrangement is provided as the internal semiconductor integrated circuit in computer or other electronic system conventionally. Exist manyDissimilar memory, comprises volatile memory and nonvolatile memory. Volatile memory can need electric power withMaintain its data (for example, host data, wrong data etc.) and comprise random access memory (RAM), dynamic randomAccess memory (DRAM), static RAM (SRAM), Synchronous Dynamic Random Access Memory (SDRAM)And IGCT random access memory (TRAM) etc. Nonvolatile memory can be stored by maintenance in the time not poweringData and persistant data is provided, and can comprise NAND flash memory, NOR flash memory and resistance-variable storageDevice (deposit at random by for example phase change random access memory devices (PCRAM), resistive random access memory (RRAM) and reluctance typeAccess to memory (MRAM), such as spinning moment shifts random access memory (STTRAM)) etc.
Electronic system comprises some processing resources (for example, one or more processor) conventionally, and described some processing resources can be examinedRope and carry out instruction and by the result store of performed instruction to correct position. Processor can comprise some functional units, exampleAs ALU (ALU) circuit, floating point unit (FPU) circuit and/or combined logic block, described functional unit (for example) can in order to by data (for example, one or more operand) actuating logic computing (for example AND, OR, NOT,NAND, NOR and xor logic computing) and carry out instruction. For instance, functional unit circuit (FUC) can be in order to rightOperand is carried out arithmetical operation (for example, addition, subtraction, multiplication and/or division).
In the time instruction being provided to FUC for execution, can relate to the some assemblies in electronic system. For example, instruction can be byProcessing resource (for example, controller and/or host-processor) produces. Data (for example, will it being carried out to the operand of instruction)Can be stored in can be by the memory array of FUC access. Can be from described memory array search instruction and/or data and canSequencing and/or buffered instructions and/or data before FUC starts that data are carried out to instruction. In addition, because can pass through FUCCarry out dissimilar computing with one or more clock cycle, thus also can sequencing and/or buffered instructions and/or data inBetween result.
In many examples, processing resource (for example, processor and/or the FUC that is associated) can be in memory array outside, andCan be via the bus access data (for example,, to carry out instruction) of processing between resource and memory array. Data can be via alwaysLine moves to the register of memory array outside from memory array.
Brief description of the drawings
Fig. 1 is the frame of the equipment of the form of the computing system that comprises storage arrangement according to being of some embodiment of the present inventionFigure.
Fig. 2 illustrates according to the schematic diagram of the part of the memory array of some embodiment of the present invention.
Fig. 3 illustrates according to the signal of a part for the memory array that is coupled to sensing circuit of some embodiment of the present inventionFigure.
Detailed description of the invention
The present invention comprises the Apparatus and method for relevant with access memory array address space. Example memory array comprises:The first address space, it comprises the memory cell that is coupled to the first number selection line and some sense wires; And second groundSpace, location, it comprises the memory cell that is coupled to the second number selection line and described some sense wires. Described the first groundSpace, location is independently addressable with respect to described the second address space.
Some embodiment of the present invention can reduce memory array outside between actuating logic operational stage in order to storage inBetween the number of register of result. With for example, by for example previous PIM system and there is ppu and (, be positioned storageDevice array outside, for example the processing resource on independent IC chip) the register phase of processing resource access of systemRatio, for example, when processing resource and memory array cell and be coupled (, integrated), can improve being associated with access function resisterThe power consumption of degree of parallelism and/or reduction. For example, some embodiment can provide the data that use from some registers to carry outComprehensively complete computing function, for example integer is added, integer subtracts each other, (content can for integer multiply, integral divide and CAMAddressable memory) function, and for example, via bus (, data/address bus, address bus, control bus) data are not sent outMemory array and sensing circuit. This type of computing function can relate to carry out some logical operations (for example, AND, NOT,NOR, NAND, XOR etc.). But embodiment is not limited to these examples. In some embodiment, in arrayColumn of memory cells can be used as and the register of carrying out computing function and being associated. For instance, be used as the storage of registerDevice cell row can be the part of address space, and described address space is with respect to the address space that comprises other column of memory cellsIndependently addressable.
Formerly in front method, can (for example,, via the bus that comprises I/O (I/O) line) by data from array and sensing electricityRoad be sent to can for process resource (for example processor, microprocessor and/or computing engines) some registers, described inProcess resource and can comprise the ALU circuit and/or other functional unit circuit that are configured to carry out suitable logical operation. But,Via bus, data are sent to register or can relate to remarkable power consumption from register transfer to memory from memoryAnd time demand. Be positioned on same chip even if process resource and memory array, arrive meter data are shifted out to arrayCalculate circuit (this can relate to for example carry out sense wire address access (for example, the triggering of row decoded signal (firing)) with by data fromSense wire is sent to I/O line; Described data mobile is arrived to array periphery; And described data are provided to and computing function phaseAssociated register) time still can consume remarkable electric power.
In describing in detail below of the present invention, with reference to the accompanying drawing that forms part of the present invention, and in the accompanying drawings with the side of explanationHow formula can put into practice one or more embodiment of the present invention if being shown. Enough describe these embodiment in detail so that affiliated fieldThose skilled in the art can put into practice embodiments of the invention, and should be understood that without departing from the scope of the invention,Other embodiment can be utilized and process, electric and/or structural change can be carried out. As used herein, indicator " N "(especially about the reference number in graphic) instruction: some special characteristics that can comprise appointment like this. As used herein," some " specific matters can refer to that (for example, some memory arrays can refer to one or more storage for one or many person in this type of thingsDevice array).
Figure herein follows numbering convention, and wherein the first or former bit digital are identified corresponding to graphic figure number and remaining digitElement in graphic or assembly. Can be by using like or the assembly between the different figure of similar numeral identification. Come for exampleSay, 130 can refer to the element " 30 " in Fig. 1, and like can be described as 230 in Fig. 2. As should be appreciated that, can addAdd, exchange and/or eliminate the element of showing in various embodiment in this article so that some extra enforcement of the present invention to be providedExample. In addition, as should be appreciated that, ratio and relative scalar explanation some embodiment of the present invention of the element providing in figure be provided,And should not be regarded as limited significance.
Fig. 1 is the form of the computing system 100 that comprises storage arrangement 120 according to being of some embodiment of the present inventionThe block diagram of equipment. As used herein, storage arrangement 120, memory array 130 and/or sensing circuit 150 are alsoCan be considered as separately " equipment ".
System 100 comprises the main frame 110 that is coupled to storage arrangement 120, and storage arrangement 120 comprises memory array130. Main frame 110 can be host computer system, for example individual laptop computer, desktop PC, digital camera, movesMobile phone or memory card reader, and the main frame of various other types. Main frame 110 can comprise system board and/or backboardAnd can comprise some processing resources (for example, the control circuit of one or more processor, microprocessor or a certain other type).System 100 can comprise independent integrated circuit, or main frame 110 and storage arrangement 120 both can be on same integrated circuit.System 100 can be (for example) server system and/or high-performance calculation (HPC) system and/or described high-performance calculation (HPC)The part of system. Although example demonstrated in Figure 1 explanation has the system of von Neumann (VonNeumann) framework,But can implement embodiments of the invention, described Fei Fengnuoyi by non-von Neumann framework (for example, figure spirit (Turing) machine)Graceful framework can not comprise one or more assembly (for example, CPU, ALU etc.) being conventionally associated with von Neumann framework.
For clarity, simplified system 100 to concentrate on and the feature of certain relevant of the present invention. For example. Memory arrayRow 130 can be DRAM array, SRAM array, STTRAM array, PCRAM array, TRAM array,RRAM array, NAND flash array and/or NOR flash array. Array 130 can comprise and is arranged through selection line(can be described as in this article word line or access line) coupling row and (can be described as in this article digital line or data by sense wireLine) memory cell of row of coupling. Although show single array 130 in Fig. 1, embodiment is so not limited. ExampleAs, storage arrangement 120 can comprise some arrays 130 (for example, some DRAM cell libraries). In conjunction with Fig. 2, reality is describedExample DRAM array.
Storage arrangement 120 for example comprises in order to latch, via I/O bus 156 (, data/address bus) by I/O circuit 144The address circuit 142 of the address signal providing. Receive and decode address letter by row decoder 146 and column decoder 153Number with access memory array 130. In some examples, can be by more or fewer row decoder decode address signal.For instance, storage arrangement can comprise three row decoders. As used herein, row decoder can be described as and selects to separateCode device. In some examples, row decoder 146 can be in order to decoding corresponding to the memory cell in memory array 130Address space 131. In Fig. 1, address space 132 is independently addressable with respect to address space. Can pass through use senseThe voltage of slowdown monitoring circuit 150 sensing sense wires and/or electric current change and from memory array 130 reading out datas. Sensing circuit150 can for example, from data page described in memory array 130 reading out data pages (, OK) latch. I/O circuit 144 can be used forCarry out bidirectional data communication via I/O bus 156 and main frame 110. Write circuit 148 is in order to write data into storageDevice array 130.
In some embodiment, row decoder 146 can receive the first number from address circuit 142 by the first number lineIndividual position. Described the first number position can through pre decoding, with the second number line in triggering row decoder 146, (for example, warp be pre-Decoding line). Described the second number line can be coupled to the some final decoder in row decoder 146. Described final decodingEach in device can be connected to the described exclusive combination through pre decoding line. Each in described final decoder can be in order toActivate the row of address space 131. Thereby, via the row in shared address line decode address space 331. For instance, existRow decoder 146 places, can receive eight bit address from address circuit 142 by eight lines. Described eight positions can be through pre decodingTo activate 20 through pre decoding line. Each in described final decoder can be connected to described 20 through pre decoding lineExclusive combination for example, to activate any one (, the 28th row) in 256 row. Be executed at row decoder 146 places and connectThe number of receiving the decoding between some positions and several row of activation can be greater or less than the number of showing in example above. LiftExample, can exist than the pre decoding being associated with row decoder 146 and final decoding is more and/or pre decoding still less andFinal decoding.
In some examples, term decoding can be included in the pre decoding carried out in row decoder 146 and/or column decoder 153,The decoding of final decoding and/or any other type. In some examples, term pre decoding comprises: circuit is implemented pre decodingProcess makes not addressing address discretely. Term pre decoding and decoding in this article can in order to distinguish, term can discrete addressingLine and/or the individually line of addressing.
In some examples, the row being associated with address space 132 is independent of other row of memory array 130 and indivedualAddressing and/or decoding. As used herein, discrete address can be without decoding to activate the address of specific selection line. LiftExample, address circuit 142 can receive the address being associated with address space 132 and can activate and select line and the institute of not decodingState address. In some examples, it is capable that indivedual row of addressing and/or the row of discrete addressing can be described as full decoder. With address space131 memory cells that are associated and the memory cell being associated with address space 132 for example can comprise otherwiseFor DRAM array, SRAM array, STTRAM array, PCRAM array, TRAM array, RRAMMemory cell in array, NAND flash array and/or NOR flash array and the configuration of other memory. To tieClose Fig. 2 and Fig. 3 and describe other difference between address space 131 and address space 132 in detail.
Control circuit 140 signal being provided from main frame 110 by control bus 154 of decoding. These signals can comprise in order to controlThe chip of the operation (comprise data read, data write and data erase operation) that system is carried out memory array 130 is enabledSignal, write and enable signal and address latch signal. In various embodiments, control circuit 140 is responsible for carrying out independentlyThe instruction of machine 110. Control circuit 140 can be the controller of state machine, sequencer or a certain other type.
Below further describe the example of sensing circuit 150 in conjunction with Fig. 3. For example, in some embodiment, sensing circuit150 can comprise some sensing amplifiers and some computation modules, and described some computation modules can comprise accumulator (for example, figureThe computation module 333 of showing in 3) and can transport in order to (for example,, to the data that are associated with complementary sense wire) actuating logicCalculate. In some embodiment, sensing circuit (for example, 150) is available to use the data that are stored in array 130 as defeatedEnter actuating logic computing, and the result store of described logical operation can be got back to array 130 and not via sense wire addressAccess transmission (for example, not triggering row decoded signal). Corresponding to the row of address space 132 at actuating logic computing and/or meterCalculate between functional period and can be used as temporary storage device (for example, register). Thereby, can use sense slowdown monitoring circuit 150 carry out but notProcessing resource by sensing circuit outside is (for example,, by the processor that is associated with main frame 110 and/or be positioned deviceOther treatment circuit of (for example, on control circuit 140 or other places) on 120, for example ALU circuit) carry out various calculatingFunction, and/or except carry out by the processing resource of described sensing circuit outside various computing functions can use sense slowdown monitoring circuit150 carry out various computing functions.
In various previous methods, for example, the data that are associated with operand will read also from memory via sensing circuitBe provided to outside ALU. Described outside ALU circuit will use operand to carry out computing function and result can be via local I/OLine is transmitted back to array. By contrast, in some embodiment of the present invention, sensing circuit (for example, 150) is configured toTo being stored in the memory cell being associated with address space 131 and the memory cell being associated with address space 132The computing of data actuating logic, and result store is got back to array 130 and is not enabled this locality of being coupled to described sensing circuitI/O line.
Thereby in some embodiment, carrying out computing function can not need posting of array 130 and sensing circuit 150 outsidesStorage, this is because sensing circuit 150 can be carried out suitable logic fortune with the address space of array 130 131 and 132Calculate. In addition, can in the situation that not using external treatment resource, carry out this similar computing function. Therefore, address space 132Available to supplement at least to a certain extent and/or to replace some these type of external registers. But, in some embodiment,Can use in conjunction with some registers of array 130 outsides and/or storage arrangement 120 outsides the address space of array 130132。
Fig. 2 illustrates according to the schematic diagram of the part of the memory array 230 of some embodiment of the present invention. In this example,Memory array 230 be 1T1C (transistor one capacitor) memory cell 270-0,270-1,270-2,270-3 ...,The DRAM array of 270-N (for example, being referred to as memory cell 270), each memory cell is by access device 202 (examplesAs, transistor) and memory element 203 (for example, capacitor) composition.
In some embodiment, memory cell 270 is that destructive-read memory unit (for example, reads and is stored in unitIn data can destroy described data make to be initially stored in data in described unit after being read through refreshing). StorageDevice unit 270 be arranged through select line 204-0 (row 0), 204-1 (row 1), 204-2 (row 2), 204-3 (row 3) ...,The row of 204-N (row N) coupling and the row that for example, are coupled by sense wire (, digital line) 205-1 (D) and 205-2 (D_). ?In some embodiment, array 230 can comprise the address space that is coupled to independent circuit. For instance, as institute's exhibition in Fig. 2Show, selection line 204-2, the 204-3 of address space 231 ..., 204-N is coupled to selective decompression device 246 and address skyBetween 232 selection line 204-0 and 204-1 be coupled to address circuit 242. In some examples, address space 232At least one in selection line 204-0 and 204-1 can be coupled to the selective decompression device that is independent of selective decompression device 246.
In this example, each cell columns is associated with a pair of complementary sense wire 205-1 (D) and 205-2 (D_). Although figureThe only memory cell 270 of single row of explanation in 2, but embodiment is so not limited. For example, specific array can haveThe unit of some row and/or sense wire (for example, 4,096,8,192,16,384 etc.). In Fig. 2, storageDevice unit 270 is coupled to sense wire 205-1. The grid of discrete cell transistor 202 is coupled to its corresponding selection line 204-0For example, to 204-N (, be referred to as and select line 204), the first regions and source/drain is coupled to its corresponding sense wire 205-1, andTransistorized the second regions and source/drain of discrete cell is coupled to its corresponding capacitor 203. Although it is undeclared in Fig. 2,Sense wire 205-2 also can have the memory cell that is coupled to himself.
In Fig. 2, via the selection line 204-2 in some shared address line decode addresses space 231 to 204-N. Thereby,Activate and select line 204-2 to 204-N via the pre decoding for example, being associated with row decoder circuit (, row decoder 246).In some embodiment, owing to pre decoding process, only can start at any given time and select line 204-2 to 204-NIn one (owing to pre decoding constraint). Selection line 204-0 and the 204-1 of address space 232 are directly coupled to address electricityRoad 242 and can (for example, not decode address in the situation that) being activated discretely by address circuit 242. Thereby, select line204-0 and 204-1 can activate simultaneously and can be together with select line 204-2 to activate to the one in 204-N through pre decoding simultaneously.
In some embodiment, select line 204-2 independently addressable with respect to selecting line 204-0 and 204-1 to 204-N,This is because select line 204-2 to be coupled to row decoder 246 and to select line 204-0 and 204-1 direct-coupling to 204-NTo address circuit 242, and/or because select line 204-2 to be coupled to some shared ground to 204-N via row decoder 246Location line and selection line 204-o and 204-1 can discrete addressing. In some embodiment, the first address space (for example, correspondenceIn the address space of selecting line 204-0 and 204-1) (for example, arrive corresponding to selection line 204-2 with respect to the second address spaceThe address space of 204-N) independently addressable, this is because be coupled to first corresponding to some selection lines of the first address spaceDecoder and be coupled to the second decoder corresponding to some selection lines of the second address space.
In some embodiment, because the first address space and the second address space are independently addressable, can activate simultaneouslyThe selection line of the first address space and the second address space. Address space is coupled to some enforcements of shared address line thereinIn example, only can activate the one in described selection line in preset time. But, in this type of embodiment, be coupled to sharedThe selection line of the address space of address wire can activate with one or more selection line corresponding to another address space simultaneously.
In some examples, be coupled to corresponding to the memory cell of the selection line of address space 232 and can be used as register.The memory cell that, is coupled to the corresponding line of address space 232 can be used as that (for example) be associated with actuating logic computingTemporary storage device. What as an example, memory cell 270-0 and 270-1 can be used as being activated by computation module is temporary transientStorage device, described computation module is coupled to sensing amplifier 206 with actuating logic computing. Further describe in conjunction with Fig. 3Use the example of memory cell as register.
Decoder 246 can receive corresponding to the address of the specific selection line of decoder 246 (for example,, from address circuit 242)And as input. Decoder 246 can be via decode described address activate suitable shared address line to swash of pre decoding processThe specific selection line (for example, selecting line 204-2 to 204-N) of address space 231 alive. In this example, decoder 246The address of line 204-2 to 204-N selected in decoding. In some examples, can separate with more or fewer decoderThe address that code is associated with address space 231.
In some examples, decoder 246 can be independent of the decoder of the selection line that activates address space 232. ?In some embodiment, main frame can carry out access and possibly cannot carry out access to address space 232 address space 231.For instance, main frame can be coupled to the selection line 204-2 of address space 231 to the memory of 204-N by direct accessUnit 270-2 is to 270-N, but possibly cannot access be coupled to the selection line 204-0 of address space 232 and depositing of 204-1Storage unit 270-0 is to 270-1.
In some embodiment, and as illustrated in fig. 2, the memory cell of address space 232 and address space 231Memory cell have spacing and locate. In Fig. 2, the selection line of address space 232 is positioned memory array 230Edge part office (for example, on edge), but embodiment is so not limited. In some embodiment, corresponding toThe selection line of address space 232 and/or address space 231 can not gathered the selection line for consecutive number. For example, address skyBetween some selection lines of 231 can comprise some selection lines of the address space 232 being positioned between it.
In some embodiment, address space 231 and address space 232 can be respectively and the first address block and the second address blockBe associated. Each address block can comprise (for example) some addresses. Continuation address can refer to by single address from the first address numerical valueBe increased to the address of FA final address. Address block can comprise whole between the first address of described address block and FA final addressAddress. Address block can be divided into some addresses sub-block. For instance, memory array 230 can be associated with address block, instituteState address block can comprise the first address sub-block being associated with address space 231 and be associated with address space 232 secondAddress sub-block.
Main frame can have limited capability (for example, the address space 232 of the address that direct access is associated with address space 232Can be by user's access). For example, can use the limited access of specific address space (or its part) to retain described spyDetermine the use of address space. For instance, as further described in conjunction with Fig. 3, the address being associated with address space 232Can be through retaining for calculating operation. In some embodiment, the main frame of unknown address can carry out limited depositing to described addressGet. In some embodiment, main frame can be to address space 231 and address space 232 direct accesses. At some embodimentIn, main frame can be to the part direct access of address space 231 and/or address space 232. For instance, main frame can be to depositingStorage unit 270-1 and row 204-1 direct access and cannot be to memory cell 270-0 and row 204-0 direct access. ?In some examples, main frame can be to address space 231 direct accesses and cannot be to address space 232 direct accesses.
Fig. 3 illustrates showing according to the part of the memory array that is coupled to sensing circuit 330 of some embodiment of the present inventionIntention. The memory array 330 that Fig. 3 comprises the memory array 230 being similar in Fig. 2.
In this example, sensing circuit comprises sensing amplifier 306 and computation module 333. Sensing circuit can be in Fig. 1The sensing circuit 150 of showing. Sensing amplifier 306 is coupled to the complementary sensing corresponding to the memory cell of particular columnLine D, D_. Sensing amplifier 306 can for example be stored in, in selected unit (, memory cell 370) to determine through operationState (for example, logical data value). Embodiment is not limited to example sensing amplifier 306. For example,, according to hereinThe sensing circuit of some embodiment of describing (for example, can comprise current-mode sensing amplifier and/or single-ended sensing amplifierBe coupled to the sensing amplifier of a sense wire).
In some embodiment, computation module (for example, 333) can comprise and sensing amplifier (for example, 306) and/or array (exampleAs, 330) the transistor of memory cell 370 some transistors of having spacing and forming, described spacing can meet specificFeature sizes (for example, 4F2、6F2Etc.). As described further below, computation module 333 can be in conjunction with sensing amplifier306 together operation so that use from the data of the memory cell 370 in array 330 and carry out various logic as inputComputing, and result store is got back to the memory cell 370 in array 330 and do not transmitted number via sense wire address accessFor example, according to (, not triggering row decoded signal, make data be sent to the electricity of array and sensing circuit outside via local I/O lineRoad). Thereby some embodiment of the present invention can realize and use the electric power that is less than various previous methods to carry out associated with itLogical operation and computing function. In addition, because having eliminated across local I/O line, some embodiment transmit data to carry out calculatingThe needs of function, therefore, compared with previous method, some embodiment can use computation module (for example, 333) and memory listUnit 370 realizes the parallel processing capability increasing.
In example illustrated in fig. 3, comprise and be coupled to sense wire D and D_ corresponding to the circuit of computation module 333In each five transistors; But embodiment is not limited to this example. Transistor 307-1 and 307-2 have pointBe not coupled to the first regions and source/drain of sense wire D and D_, and be coupled to cross-couplings latch and (for example, be coupled toPair of cross coupled transistor (for example cross-couplings nmos pass transistor 308-1 and 308-2 and cross-couplings PMOSTransistor 309-1 and 309-2) grid) the second regions and source/drain. As further described, comprise crystal hereinThe cross-couplings latch of pipe 308-1,308-2,309-1 and 309-2 can be described as less important latch and (amplifies corresponding to sensingThe cross-couplings latch of device 306 can be described as main latch in this article).
Transistor 307-1 and 307-2 can be described as transmission transistor, and it can be via corresponding signal 311-1 (Passd) and 311-2(Passdb) enable with by the voltage on corresponding sense line D and D_ or current delivery to comprise transistor 308-1,308-2,The input (for example, the input of less important latch) of the cross-couplings latch of 309-1 and 309-2. In this example,The first regions and source/drain that the second regions and source/drain of transistor 307-1 is coupled to transistor 308-1 and 309-1 withAnd the grid of transistor 308-2 and 309-2. Similarly, the second regions and source/drain of transistor 307-2 is coupled to crystalline substanceThe first regions and source/drain of body pipe 308-2 and 309-2 and the grid of transistor 308-1 and 309-1.
The second regions and source/drain of transistor 308-1 and 308-2 is coupled to negative control signal 312-1 (Accumb) jointly.The second regions and source/drain of transistor 309-1 and 309-2 is coupled to positive control signal 312-2 (Accum) jointly.Accum signal 312-2 can be supply voltage (for example, Vcc) and Accumb signal can be reference voltage (for example, ground connection).Enable signal 312-1 and 312-2 activate corresponding to less important latch comprise transistor 308-1,308-2,309-1 andThe cross-couplings latch of 309-2. Amplify common points 317-1 and share operating through activating sensing amplifierDifferential voltage between node 317-2, makes node 317-1 be driven into Accum signal voltage and Accumb signalOne in voltage (for example, to the one in Vcc and ground connection), and node 317-2 is driven into Accum signal voltageAnd another one in Accumb signal voltage. As described further below, signal 312-1 and 312-2 are labeled as " Accum "And " Accumb ", this is because less important latch can be used as accumulator when in order to actuating logic computing. In some enforcementIn example, accumulator comprise form less important latch crossing coupling transistor 308-1,308-2,309-1 and 309-2 andTransmission transistor 307-1 and 308-2. As further described herein, in some embodiment, comprise and be coupled to sensingThe computation module of the accumulator of amplifier can be configured to actuating logic computing, and described logical operation comprises passing through a pair of mutualThe data value that signal (for example, voltage or electric current) at least one in benefit sense wire represents is carried out accumulating operation.
Computation module 333 also comprises inverted transistors 314-1 and 314-2, and it has the respective digit line of being coupled to D and D_The first regions and source/drain. The second regions and source/drain of transistor 314-1 and 314-2 is coupled to respectively transistorThe first regions and source/drain of 316-1 and 316-2. The grid of transistor 314-1 and 314-2 is coupled to signal 313(InvD). The grid of transistor 316-1 is coupled to common points 317-1, the grid of transistor 308-2, transistor 309-2Grid and the first regions and source/drain of transistor 308-1 be also coupled to common points 317-1. With complimentary fashion, crystalline substanceThe grid of body pipe 316-2 is coupled to common points 317-2, the grid of transistor 308-1, the grid of transistor 309-1 andThe first regions and source/drain of transistor 308-2 is also coupled to common points 317-2. Thereby, enable signal InvD in order toMake to be stored in data value in less important latch anti-phase and described inverse value is driven on sense wire 305-1 and 305-2.
In Fig. 3, computation module 333 is configured to carry out AND, NAND and/or NOT (for example, anti-phase) computing.How following instance can use the data that are stored in array 330 (for example,, with address space 331 and address space by confirming332 data that are associated) carry out 3 input NAND computings and can how (for example, to feel via sensing circuit as inputSurvey amplifier 306 and computation module 333) operation by the result store of NAND computing in array. Described example relates toAnd be coupled to by being stored in the memory cell 370 of selecting line 304-0 to 304-N and being jointly coupled to sense wire 305-1In data value (for example, logical one or logical zero) to use be the corresponding input of NAND computing. The result of NAND computingCan be stored in and select line 304-0 at least one the memory cell in 304-N.
As an example, the memory cell of row 304-1 (for example, unit 370-1) can be used as the register of computation module 333.For example, computation module 333 can use data in the row that is stored in address space 331 as input, and can calculate meritThe intermediate object program of energy is kept in the row of address space 332. In this example, the result store of calculating operation can be got back toThe row of the row of address space 331 and/or address space 332. In some embodiment, can be by the result of computing function simultaneouslyStore one or more row of address space 332 and the row of address space 331 into.
Use the memory cell of address space 332 to carry out temporary transient storage can to prevent from using the memory list of address space 331Unit carries out the needs of temporary transient storage, and it can increase amount that can access memory. For instance, if computation module 333 makesWith the memory cell of address space 331, as temporary storage device, the described unit of address space 331 cannot be used soIn other data of storage, it can suppress the use (for example, passing through main frame) of address space 331. For example, use address skyBetween 331 can limit the total amount of the address space that can be used for main frame as temporary storage device. On the contrary, in conjunction with retouching hereinThe embodiment stating, uses address space 332 for example, to allow computation module 333 to carry out some patrolling as temporary storage device ()Volume computing and not restricting host use the ability of address space 331.
The example that address space 332 wherein can be used as the logical operation of register is below described. For example, 3 input NANDThe first operation stages of computing can comprise: use the memory cell (for example, unit 370-0) of sensing amplifier 306 to row 0Carry out the data value that sense operation is stored to determine, described data value can be used as the first input of NAND computing. DescribedSense operation relates to activation row 0 (for example,, via address circuit 342) and makes the voltage (for example, Vcc) corresponding to logical oneOr for example, go up (and another voltage is on complementary sense wire D_) corresponding to the voltage (, ground connection) of logical zero in sense wire D,Make the data value storage of institute's sensing in the main latch corresponding to sensing amplifier 306. Store at sensing capable 0After device unit 370-0, enable Passd signal 311-1 and Passdb signal 311-2 and enable Accumb signal 312-1And Accum signal 312-2, it causes being stored in copying to through sense data value in row 0 memory cell 370-0Corresponding to the less important latch of computation module 333. Then inactive Passd signal and Passdb signal; But, keep openingWith Accum signal and Accumb signal (during second, third and the 4th operation stages, as described below). ThenInactive row 0 and generation balance. Balance for example can relate to, under balanced voltage (, it can be Vcc/2) complementary sense wire DAnd D_ is shorted together. For example, before balance can betide () memory cell sense operation.
The second stage of 3 input NAND computings comprises: to row 1 memory cell (for example, use sensing amplifier 306370-1) carry out sense operation to determine the data value of its storage, described data value is as the second input of NAND computing.Thereby, enable row 1 and sense wire D and D_ are driven into different in Vcc and ground connection separately by address circuit 342One. In this example, the Vcc voltage on sense wire D is corresponding to the logical one being stored in memory cell 370-1And the ground voltage on sense wire D is corresponding to logical zero; But embodiment is not limited to this example. Store at sensing capable 1After device unit 370-1, enable Passd signal 311-1 and keep stop using Passdb signal 311-2 (for example, only enablePassd). Recall (recall) and keep enabling Accumb signal 312-1 and Accum signal 312-2. If be stored in row 1Data value in memory cell 370-1 is logical zero, asserts that so the accumulated value being associated with less important latch is low,Make less important latch stores logical zero. If the data value being stored in row 1 memory cell 370-1 is not logical zero,So less important latch keeps row 0 data value (for example, logical one or logical zero) of its storage. Thereby, in this example,Less important latch is as zero (0) accumulator. Then inactive Passd signal, the row 1 of stopping using, and there is balance.
The phase III of 3 input NAND computings comprises: to row 2 memory cells (for example, use sensing amplifier 306370-2) carry out sense operation to determine the data value of its storage, described data value is as the 3rd input of NAND computing.Thereby, enable row 2 and sense wire D and D_ are driven into different in Vcc and ground connection separately by row decoder 346One. After the capable 2 memory cell 370-2 of sensing, enable Passd signal 311-1 and keep the Passdb letter of stopping usingNumber 311-2 (for example, only enabling Passd). Recall and keep enabling Accumb signal 312-1 and Accum signal 312-2.If the data value being stored in row 2 memory cell 370-2 is logical zero, asserts so and be associated with less important latchAccumulated value be low, make less important latch stores logical zero. If be stored in row 2 memory cell 370-2Data value is not logical zero, and so less important latch is preserved its previously stored value (for example, the value of its storage). Thereby,Be stored in value (for example, the output of accumulator) in less important latch and be stored in corresponding row 0 memory cell 370-0,The AND of the data value in row 1 memory cell 370-1 and row 2 memory cell 370-2. Then the Passd that stops using believesNumber, the row 2 of stopping using, and there is balance.
The fourth stage of 3 input NAND computings comprises: inactive balance is floated sense wire D and D_. Then enableInvD signal 313, it causes being stored in anti-phase (for example, make cumulative output anti-phase) of data value in less important latch.Thereby, if any one stored logic 0 in memory cell 370-0,370-1 and 370-2 is (for example,, if NANDAny one in three inputs of computing is logical zero), sense wire D_ will corresponding to the voltage of logical zero (for example, carry soGround voltage) and sense wire D for example, by the voltage (, Vcc) carrying corresponding to logical one. If memory cell 370-0,Whole person's stored logics 1 in 370-1 and 370-2 (for example, if the whole persons in three inputs of NAND computing allLogical one), sense wire D_ will carry the voltage and the sense wire D that carry corresponding to logical one corresponding to logical zero soVoltage. Then enabling the main latch of sensing amplifier 306 and sense wire D now contains to come voluntarily and 0 stores to row 2The corresponding input data values of device unit 370-0,370-1 and 370-2 through with non-(NANDed) result. Thereby, ifRow 0 is to any one stored logic 0 in row 2 memory cells, and sense wire D will be in Vcc, and if row 0 soTo the whole person's stored logics 1 in row 2 memory cells, sense wire D will be in ground connection so. Then, can be by NANDThe result store of computing is got back to the memory cell being associated with address space 332. In some examples, can be by NANDThe result store of computing is for example got back to, with address space 331 address space of shared address line decoding (, via) and is associatedMemory cell. In this example, can be by the result store of NAND computing to row 1 memory cell 370-1. WillThe result store of NAND computing relates to via address circuit 342 and activates row 1 to row 1 memory cell 370-1. Row 1The capacitor 303 of memory cell 370-1 will for example be driven to, corresponding to (, the logical one of the data value on sense wire DOr logical zero) voltage, this overrides any data value being previously stored in row 1 memory cell 370-1 substantially. ExampleAs, for example, in the time of the intermediate object program that result is with more complex calculation is associated of logical operation (, NAND), will described in patrolThe result of volume computing be saved in register, can be useful. For instance, preserve and be expert in 1 memory cell 370-1Result can be used as the input in subsequent logic computing. Embodiment is so not limited.
In some embodiment, the result of logical operation can be written to the memory cell being associated with address space 331.For instance, result store can be got back to the memory cell of row 204-2 to 204-N. In some embodiment, logicThe result of computing can not stored and got back to array (for example, getting back to the unit of address space 331 or address space 332). For example,After actuating logic computing, result for example, can be sent to outside dress from accumulator (, the accumulator of computation module 333)Put (external host that for example, is coupled to sensing amplifier via local I/O line).
And one of ordinary skill in the art should be appreciated that, the ability of carrying out NAND logical operation can make more complicated meterCalculate function, the execution of for example addition, subtraction and multiplication and other Major Mathematics function and/or pattern comparing function becomes canEnergy. For instance, a series of NAND computings can be through combination to carry out full adder function. As an example, if full adderNeed 12 NAND doors to add two data values together with carry input and carry output, can carry out so and amount to 384Individual NAND computing (12x32) is to add two 32-bit numbers. Embodiments of the invention also can be non-cloth in order to carry outWoods (boolean) (for example, copy, relatively etc.) and/or can be more complicated or more uncomplicated compared with NAND computingLogical operation.
In some examples, the data value being stored in corresponding in the memory cell of the row of address space 331 can be copiedTo the memory cell of the row corresponding to address space 332. For instance, will be stored in memory cell 370-3Data value copies to memory cell 370-1 and can comprise and described data value is copied to sensing from memory cell 370-3 putLarge device 306. Then, can select line 204-1 and described data value is copied to and deposited from sensing amplifier 306 by activationStorage unit 370-1.
The in the situation that of inactive I/O circuit, can carry out data value is copied to memory cell from sensing amplifier 306370-1. Data value is copied to memory cell and do not activate I/O circuit and can save time and provide from sensing amplifier 306Source, this is because of inactive I/O circuit, and compared with activating the situation of I/O circuit, can carry out and copy sooner.
As another example, data value can be copied to address sky from the memory cell 370-3 of address space 331 simultaneouslyBetween 332 memory cell 370-0 and 370-1. For instance, data value can be copied to from memory cell 370-3Sensing amplifier 306, and described data value is copied to memory cell 370-0 simultaneously and deposits from sensing amplifier 306Storage unit 370-1. Address circuit 342 can activate memory cell 370-0 and 370-1 simultaneously, and this is because and addressThe memory cell that space 332 is associated is by addressing discretely. On the contrary, owing to decoding corresponding to ground via shared address lineThe row in space, location 331, therefore at every turn can by data from sensing amplifier 306 copy to row 304-2 to 304-N onlyOne.
In some embodiment, can by data value from the row of address space 331 copy to address space 331 different rows andThe row of address space 332. For instance, data value can be copied to sensing amplifier 306 from memory cell 370-3,And described data value is copied to memory cell 370-1 and 370-2 from sensing amplifier 306 simultaneously. Can by data fromMemory cell 370-3 copies to memory cell 370-1 and 370-2 simultaneously, and this is because of for to be decoded by row decoder 346The address (for example,, via pre decoding) being associated with memory cell 370-2 and because be associated with memory cell 370-1Address by addressing discretely. , row decoder 346 can be when address circuit 342 can activate selection line 304-1Activate and select line 304-2.
In some embodiment, data value can be copied to the row of address space 331 from the row of address space 332. For example, data value can be copied to sensing amplifier 306 and copies from sensing amplifier 306 from memory cell 370-1To memory cell 370-3. As another example, data value can be copied to address space from the row of address space 332332 several rows. For instance, can by data value from memory cell 370-0 copy to sensing amplifier 306 and fromSensing amplifier 306 copies at least two different memory unit that are associated with address space 332. At some examplesIn, data value can be copied to colleague mutually and/or the address space 332 of address space 332 from the row of address space 332Some different rows. Data value can be copied to simultaneously to different rows and the address sky of address space 332 from the row of address 332Between 331 row.
In some embodiment, can in the circulation of single sensing, carry out above-mentioned copying (for example, and without additional arrays balance,Again the sensing of line activating and/or bit line). For instance, in the circulation of single sensing by data value from address space 331The row row that copies to address space 332 can comprise the described row of sensing address space 331. With from address space 331Described row sense data value time performed comparing, can carry out and copy and without the extra sense of the described row of address space 331Survey and without extra balance. In addition, can carry out and copy and without additional row access. For instance, can for example, by (, activatingTrigger) the selection row of the address space 332 and data value of the row sensing from address space 331 is copied to address space 332One or more row, but not again sensing corresponding to the bit line of selected unit. Having following ability can be multiple by reducing executionMake the number of required sensing circulation and the remarkable performance that is better than previous method be provided: in single sensing circulation by data valueCopy to the several rows of address space 332 from the row of address space 331; Data value is copied from the row of address space 332To the row of address space 331; And/or by data value some from the address reproduction of address space 332 to address space 332Address.
Embodiments of the invention are not limited to specific sensing circuit configuration illustrated in fig. 3. For example, different computation module electricityRoad can be in order to carry out according to the logical operation of some embodiment described herein. Although undeclared in Fig. 3, someIn embodiment, control circuit can be coupled to array 330, sensing amplifier 306 and/or computation module 333. This controls electricityRoad can (for example) on the chip identical with array and sensing circuit and/or external treatment resource (for example ppu) upper realExecute, and can control and enable/stop using to carry out logic as described herein corresponding to the various signals of array and sensing circuitComputing.
Sum up
The present invention comprises the device and method for access memory array address space. Example memory array comprises: theOne address space, it comprises the memory cell that is coupled to the first number selection line and some sense wires; And second addressSpace, it comprises the memory cell that is coupled to the second number selection line and described some sense wires. Share via someSelect line described the first number selection line of decoding. Described the first address space can be independent with respect to described the second address spaceAddressing.
Although illustrated and described specific embodiment herein, one of ordinary skill in the art should be appreciated that, as calculated withRealize alternative the shown specific embodiment of layout of identical result. The present invention wishes to contain one or more reality of the present inventionExecute adjusting or changing of example. Should be understood that non-limiting way is described with illustrative approach above. Affiliated fieldTechnical staff checking above after describing and will understand embodiment above and specifically described other embodiment not hereinCombination. The scope of one or more embodiment of the present invention comprises and wherein uses other application of structure and method above. Therefore,The four corner of the equivalent that should have the right to have with reference to appended claims and this claims is determined the present inventionThe scope of one or more embodiment.
In previous embodiment, for simplify object of the present invention, by some characteristic sets in single embodiment.The method of the present invention should not be interpreted as reflecting that disclosed embodiment must use than being clearly set forth in eachThe intention of more feature in item claim. But as appended claims reflection, subject matter of the present invention is fewIn whole features of disclosed single embodiment. Therefore, hereby appended claims is incorporated in detailed description of the invention,Wherein each claim is independently as independent embodiment.

Claims (36)

1. a memory array, it comprises:
The first address space, it comprises the memory cell that is coupled to the first number selection line and some sense wires; And
The second address space, it comprises the memory list that is coupled to the second number selection line and described some sense wiresUnit;
Wherein said the first address space is independently addressable with respect to described the second address space.
2. memory array according to claim 1, wherein only activates described the first number in preset time and selects lineIn one and wherein activate described the second number simultaneously and select line.
3. memory array according to claim 2, wherein activates described the first number simultaneously and selects the choosing in lineSelecting line and described the second number selects one in line to select line.
4. memory array according to claim 1, wherein activates described the first number simultaneously and selects the choosing in lineSelecting line and described the second number selects one in line to select line.
5. memory array according to claim 4, wherein activate simultaneously described the first number select in line described inSelect line and all described the second numbers to select line.
6. memory array according to claim 4, wherein only activates described the first number in preset time and selects lineIn one.
7. according to the memory array described in arbitrary claim in claim 1 to 6, wherein said the first address space phaseFor described the second address space independently addressable comprising: described the first number selects a line to be coupled to decoder and instituteStating the second number selects line to be directly coupled to address circuit.
8. memory array according to claim 7, wherein said address circuit is coupled to described decoder.
9. according to the memory array described in arbitrary claim in claim 1 to 6, wherein said the first address space phaseFor described the second address space independently addressable comprising: described the first number selects a line to be coupled to the first decoderAnd described the second number selects line to be coupled to the second decoder.
10. memory array according to claim 9, wherein said the first decoder and described the second decoder are coupled toShared address circuit.
11. according to the memory array described in arbitrary claim in claim 1 to 6, wherein said the first address space phaseFor described the second address space independently addressable comprising: described the first number selects a line to be coupled to via decoderSome shared address lines and described a second number selection line can discrete addressing.
12. according to the memory array described in arbitrary claim in claim 1 to 6, wherein the second number described in independent addressingOrder is selected each in line.
13. according to the memory array described in arbitrary claim in claim 1 to 6, comprising described the first address skyBetween described memory cell by described some sense wires be coupled to comprise described the second address space described in depositStorage unit.
14. according to the memory array described in arbitrary claim in claim 1 to 6, is wherein independent of described the second numberDecode described the first number of individual selection line is selected line.
15. according to the memory array described in arbitrary claim in claim 1 to 6, comprising described the second address skyBetween described memory cell be positioned on the marginal portion of described memory array.
16. according to the memory array described in arbitrary claim in claim 1 to 6, and wherein said the second address space is usedMake the temporary storage device of computation module.
17. according to the memory array described in arbitrary claim in claim 1 to 6, wherein said temporary storage device byDescribed computation module is as register.
18. according to the memory array described in arbitrary claim in claim 1 to 6, and wherein said computation module is coupled toDescribed some sense wires and comprise the transistor that has spacing and form with described memory cell.
19. 1 kinds of methods, it comprises:
Activating first number of memory array selects one in line to select line;
Carrying out sensing via the sensing circuit of sense wire that is coupled to described memory array is stored in and is coupled to described selectionData in the first number memory cell of line; And
To be stored in described data Replica in described the first number memory cell to the second number memory listUnit, the second number that described the second number memory cell is coupled to described memory array is selected one in lineSelect line;
Wherein said the first number selects line to select line independently addressable with respect to described the second number.
20. methods according to claim 19, wherein copy the institute being stored in described the first number memory cellStating packet contains: described data are copied to described the second number memory cell and do not deposit from described sensing circuitGet I/O I/O line.
21. methods according to claim 20, wherein copy to described the second number by described data from described sensing circuitAn order memory cell further comprises: described data are copied to a 3rd number memory from described sensing circuitUnit, described a 3rd number memory cell is coupled to described the first number selects another selection line in line.
22. methods according to claim 21, wherein copy to described the second number by described data from described sensing circuitAn order memory cell with described data are copied to described a 3rd number memory cell from described sensing circuitOccur simultaneously.
23. according to the method described in arbitrary claim in claim 19 to 22, wherein activates described the first number and selectsDescribed selection line in line comprises: activate described selection line via decoding circuit, described decoding circuit is independent of and swashsThe decoding circuit that the described selection line of living in described the second number selection line is associated.
24. 1 kinds of methods, it comprises:
Activate first number of memory array and select the selection line in line, be wherein coupled to the choosing of described the first numberThe memory cell of selecting line is used as temporary storage device by computation module;
Carry out sensing via the sensing circuit of sense wire that is coupled to described memory array and be stored in the storage of the first numberData in device unit, described the first number memory cell is coupled to described the first number selects the institute in lineState selection line; And
To be stored in described data Replica in described the first number memory cell to the second number memory listUnit, described the second number memory cell is coupled to the selection of the second number selection line of described memory arrayLine;
Wherein said the first number selects line to select line independently addressable with respect to described the second number.
25. methods according to claim 24, wherein copy the institute being stored in described the first number memory cellStating packet contains: described data are copied to from described the first number memory cell as temporary storage deviceDescribed sensing circuit.
26. methods according to claim 25, wherein copy the institute being stored in described the first number memory cellStating packet contains: described data are copied to described the second number memory cell and do not deposit from described sensing circuitGet I/O I/O line.
27. methods according to claim 25, wherein copy the institute being stored in described the first number memory cellStating packet contains: described data are copied to a 3rd number memory cell, the described the 3rd from described sensing circuitA number memory cell is coupled to described the first number selects another selection line in line.
28. methods according to claim 25, wherein copy the institute being stored in described the first number memory cellStating packet contains: described data are copied to and are coupled to described the first number selection line from described sensing circuit simultaneouslyIn another select a 3rd number memory cell of line and be coupled to the institute in described the first number selection lineState described the first number memory cell of selecting line.
29. according to the method described in arbitrary claim in claim 24 to 28, wherein copies and is stored in described the first numberDescribed data in individual memory cell are included in single sensing circulation and copy.
30. 1 kinds of equipment, it comprises:
The first address space of memory array, it comprises that being coupled to the first number selects the of line and some sense wiresAn one number memory cell;
The second address space of described memory array, it comprises that being coupled to the second number selects line and described some sensesThe second number memory cell of survey line, wherein said the second address space can with respect to described the first address spaceIndependent addressing; And
Sensing circuit, it is configured to:
At least receive the first data value of being associated with described the first address space and with described the second address space phaseThe second associated data value; And
Hold as the second input as the first input and with described the second data value with described the first data valueRow logical operation.
31. equipment according to claim 30, wherein said the first address space is associated with the first address block and secondAddress space is associated with the second address block, and wherein said the first address block separates with described the second address block.
32. equipment according to claim 31, it further comprises the processing resource of described sensing circuit outside, described inProcess resource described the first address space is carried out to access, wherein said processing resource is not to described the second address spaceCarry out access.
33. equipment according to claim 32, wherein said processing resource comprises external host.
34. equipment according to claim 31, it further comprises the processing resource of described sensing circuit outside, described inProcess resource at least a portion of described the first address space and described the second address space is carried out to access.
35. according to the equipment described in arbitrary claim in claim 30 to 34, and wherein said sensing circuit is configured to holdGo described logical operation and do not transmit data via sense wire address access.
36. according to the equipment described in arbitrary claim in claim 30 to 34, and wherein said sensing circuit comprises and comprises crystalline substanceThe computation module of body pipe, the first number memory cell and described a second number storage described in described transistor AND gateThere is spacing device unit.
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