CN1073283C - 芯片上引线型引线框架 - Google Patents

芯片上引线型引线框架 Download PDF

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CN1073283C
CN1073283C CN97111828A CN97111828A CN1073283C CN 1073283 C CN1073283 C CN 1073283C CN 97111828 A CN97111828 A CN 97111828A CN 97111828 A CN97111828 A CN 97111828A CN 1073283 C CN1073283 C CN 1073283C
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lead
chip
wire
pad
lead frame
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CN1170235A (zh
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姜信英
金洪奭
权正泰
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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Abstract

一种适用于将被分为两个独立电路块的芯片安装在其上的芯片上引线型引线框架，该两个独立电路块各自具有相对于芯片中央部位横向对称地设置的焊盘。该芯片上引线型引线框架具有多个伸长的共同引线，每一共同引线配合各自设置于电路块而具有相同功能的每一焊盘对的引线键合焊盘，每一共同引线从芯片中央部位槽向地延伸，使得其超过了芯片期望边缘而引出。在此引线框架中，可降低引脚数，从而使封装尺寸为最小。

Description

芯片上引线型引线框架
本发明涉及一种芯片上引线型引线框架，特别涉及一种用于代替多芯片封装的高度集成半导体存储器件的芯片上引线型引线框架。
芯片上引线型引线框架具有一种引线配置于一芯片上的结构，以制造高度集成半导体存储器件，其具有减小的封装面积且降低了电源线的噪音产生。
有关这种用于高度集成半导体存储器件的芯片上引线型引线框架，简单说明如下。
一般而言，一个芯片上引线型引线框架具有用于诸如接地电压线与供应电压线的电源线的引线、用于诸如CASL(低)、CASU(高)、WE(写入使能)、OE(输出使能)与RAS信号的控制信号的引线、用于输入/输出信号的引线、以及用于地址信号的引线。每一引线具有一末端，其延伸至安装于引线框架上的芯片的中央部位的一期望位置。即，引线在其末端引线键合至各自地设置于芯片中央部位的焊盘。因此，在引线与芯片之间可得到电气连接。由于这些焊盘设置于这种结构中的芯片中央部位处，信号传输线的长度可以最短。可以达成一种容易设计的信号传输线。因此，可制造出一种稳定的半导体元件。
另一种芯片上引线型引线框架结构也已经提出。在这种芯片上引线型引线框架结构中，如前述引线框架结构，每一信号传输线具有一个延伸至安装于该引线框架上的芯片中央部位的一期望位置的末端。该引线框架也设有诸如接地电压引线与供应电压引线的电源线，其跨过芯片中央部位而纵向地延伸。利用引线键合技术，这些电源线电连接至芯片上的焊盘。
在该种结构中，电力传输是由伸长至芯片中央部位的接地电压引线或供应电压引线而实现。该电源线与设置于芯片上的电源线的线路相比较，具有较低的电阻。因此，它的优点在于可改善操作速度。
另一方面，在诸如一个十亿(Giga)等级的动态随机存取存储器(DRAM)的高度集成半导体元件的情况下，其可能具有一个太大的尺寸而无法使元件以一单一个步骤制造。在此情况下，用于该半导体元件的芯片应分为512百万(Mega)等级的两个DRAM的电路块。每一个电路块具有独立的焊盘，用于控制信号线、电源线、输入/输出信号以及地址信号，使得例如512百万等级的相关DRAM可独立地操作。
图1说明一种具有常用架构的芯片上引线型引线框架，以及一个安装于该引线框架上的芯片。如图1所示，以图号10标示的芯片被分为两个独立的电路块。该芯片具有以一单一线状设置于左侧电路块中央部位的左侧焊盘P1……Pn，以及一单一线状设置于右侧电路块中央部位的右侧焊盘P’1……P’n。这些左侧与右侧焊盘连接至信号线与电源线，且彼此独立以操作例如该512百万等级的各个DRAM。左侧引线L1……Ln与右侧引线L’1……L’n也设置于芯片10的上，使得这些引线具有邻近左侧与右侧焊盘而各自地设置的末端。左侧引线L1……Ln与右侧引线L’1……L’n从相关的焊盘横向地延伸，使得这些引线各自地从芯片10的相关的侧边伸出。
另一方面，图2说明一种具有另一常用架构的芯片上引线型引线框架，以及一个安装于该引线框架上的芯片。如图2所示，以图号10标示的芯片10具有以一单一线状设置于芯片10中央部位的左侧焊盘P1……Pn，以及以一单一线状设置于芯片10中央部位的右侧焊盘P’1……P’n。左侧引线L1……Ln与右侧引线L’1……L’n也设置于芯片10之上，使得它们具有各自地设于邻近这些左侧与右侧焊盘的末端。引线L1与Ln通过线路20彼此连接，该线路20连接至引线L1与Ln且都沿着芯片10中央部位的空间而延伸。引线L’1与L’n通过线路30彼此连接，该线路30连接至引线L’1与L’n同时沿芯片10中央部位的空间而延伸。
图3说明一种半导体封装，其制造利用将一芯片安装于具有图1或图2架构的芯片上引线型引线框架，且对于该安装芯片的引线框架实施键合过程与模制过程。如图3中所示，该半导体封装具有86个引脚，在其等末端处分别标示出其功能或目的。即，此半导体封装设有用于供应电压VCC的引线1、18、69与86；用于供应电压VCCq的引线2、6、14、73、77与85；用于接地电压VSS的引线19、42、45与68；用于接地电压VSSq的引线3、7、15、76、81与84；用于诸如CASL、CASU、WE、OE与RAS信号的控制信号的引线23、24、25、26、61、62、64与69；用于输入/输出信号I/00至I/07的引线4、5、……16与17；用于输入/输出信号I/08至I/015的引线70、71、……、82与83；以及，用于地址信号A0至A14的引线27、……、41与46……60。由于此种架构具有一横向对称的焊盘/引线设置，其需有大量的引脚。
如上所述，常用的芯片上引线型引线框架具有一种包括独立电路块的架构，这些独立电路块具有一对称结构。因此，需要一种对称的焊盘/引线设置。结果，增加了所产生的封装的尺寸。
因此，本发明的一个目的旨在解决上述问题，即解决封装尺寸的增加，且旨在提供一种芯片上引线型引线框架，其具有一种架构，于该架构中在各自设置于安装在引线框架上的芯片的两个电路块的横向对称的焊盘间，具有相同功能的焊盘以共同线路成对地连接在一起，从而使封装尺寸为最小。
根据本发明的一个方面，本发明提供了一种芯片上引线型(LOC)的引线框架，它适合于在其上安装被分为两个独立电路块的芯片，所述两个独立电路块分别具有相对于芯片中心部位横向对称配置的焊盘对，所述引线框架包括：多个延长的共同引线，每个共同引线适合与具有相同功能的包括分别以中心部位横向对称布置在两个独立电路块上的相应于电源线、控制信号、以及地址信号的各属于两个独立的电路块的焊盘对的每个焊盘进行引线键合，其中，相邻的共同引线沿相反方向横向延伸，且每个共同引线从芯片的中央部位直线地横向延伸，使引线超出芯片的边缘；以及多个独立的引线，与分别布置在电路块上的焊盘引线键合并连接到输出输入信号。
本发明的其他目的与特点将由参照附图的实施例说明而变得明白，其中：
图1用以说明具有一种常用架构的芯片上引线型引线框架的一个平面图；
图2用以说明具有另一种常用架构的芯片上引线型引线框架的一个平面图；
图3用以说明一种半导体封装的一个平面图，该种半导体封装利用将一芯片安装于一种具有图1或图2的架构的芯片上引线型引线框架而制造；
图4用以说明具有一种根据本发明的架构的芯片上引线型引线框架的一个平面图；
图5用以说明一种半导体封装的一个平面图，该种半导体封装利用将一芯片安装于一种具有图4的架构的芯片上引线型引线框架而制造；以及
图6用以说明一种高度集成的半导体元件的一个平面图，该种半导体元件使用本发明的芯片上引线型引线框架而制造。
参考图4，说明一种具有根据本发明的架构的芯片上引线型引线框架。该种芯片上引线型引线框架适于安装一个具有两个横向对称且独立的电路块。
如图4所示，以图号10标示的芯片具有设置于该芯片10中央部位上的一单一线的左侧焊盘P1……Pn，及设于该芯片10中央部位上的一单一线的右侧焊盘P’1……P’n。这些左侧与右侧焊盘分别包括耦接至诸如VCC、VCCq、VSSq与VSS等不同电源的焊盘、耦接至诸如CASL、CASU、WE、OE与RAS等控制信号的焊盘、耦接至I/0信号的焊盘、以及耦接至地址信号A0至A14的焊盘。
该种芯片上引线型引线框架包括多个伸长的共同引线，每一共同引线配合具有相同功能的每一焊盘对的引线键合焊盘。这些邻近的共同引线的一引线引出至左侧，而另一引线引出至右侧。
用共同引线连接的焊盘对，其包括耦接至诸如VCC、VCCq、VSSq与VSS等不同电源的焊盘、耦接至诸如CASL、CASU、WE、OE与RAS等控制信号的焊盘、以及耦接至地址信号A0至A14的焊盘。
对于耦接至I/0信号的焊盘，该种芯片上引线型引线框架包括独立的引线，上述独立引线针对左侧焊盘而引出至左侧且针对右侧焊盘而引出至右侧。
引出至左侧的引线L1、L3,L5……Ln-3与Ln-1与左侧和右侧焊盘的奇数焊盘相关，而引出至右侧的引线L2、L4、L6……Ln-2与Ln和右侧焊盘的偶数焊盘有关。
图5说明了一种半导体封装，其利用将一个芯片安装于具有图4的架构的一种芯片上引线型引线框架上而制造，且利用用于该安装芯片的引线框架的引线键合过程与模制过程。
如图5所示，该种半导体封装具有56个引脚，其分别于其末端处标出其功能或目的。在这种半导体封装中，其引脚数相对于常用的半导体封装减少了。于图5中，标示为NC(未连接)者代表未使用的引脚。
根据本发明，耦接至一电源线VCC、VCCq、VSS或VSSq、一控制信号LCAS(低CAS)、UCAS(CAS)、WE、OE或RAS、或者一地址信号A0……或A14的每一焊盘对的左侧与右侧焊盘利用引线键合而连接至一共同线路，而耦接至I/0信号I/01……I/07等的左侧焊盘以及耦接至I/0信号I/08……I/01 5的右侧焊盘无须使用引线键合而分别连接至独立的引线。
虽然根据本发明而制造的半导体封装使用包括两个独立电路块的一个芯片，但该芯片如同一个单一的电路而动作。这是因为地址信号的输入与输出能够于两个电路块其中的一个达成，其由I/0信号所选取。
图6说明一种高度集成半导体元件，其使用本发明的芯片上引线型引线框架而制造。该半导体元件包括一个芯片10，其被分为两个独立的电路块100与200。其中该半导体元件是一个十亿(Giga)等级的DRAM，每一个电路块可以是一个512百万(Mega)等级(64M×8)的DRAM。参考图6，所显示的焊盘设置于每一个电路块中央部位上的一单一线。
虽然本发明已以应用至一个十亿等级DRAM的半导体元件而说明，但其也可应用于较高或较低等级的半导体元件。
如前述说明所明白揭示，本发明提供一种芯片上引线型引线框架，其具有一种架构，于该架构中在各自设置于安装在引线框架上的芯片的两个电路块的横向对称的焊盘间，具有相同功能的焊盘以共同引线成对连接在一起，从而使引线所占面积为最小。因此，可以使封装尺寸最小。
在包括设有一单一电路块的芯片的高度集成半导体元件的情形中，一个包括在该电路块中的构件的性能退化将可能使得整个半导体元件无用。在包括区分为独立的电路块的芯片的半导体元件的情形中，甚至当这些电路块之一的性能退化时，因为另一个电路块可正常地动作，半导体元件将能够正常地动作。所以，本发明提供了半导体元件生产上的改善。
虽然本发明的优选实施例已针对说明的目的而揭示，本领域的技术人员将可理解的是，在不偏离如随附权利要求中所界定的本发明的范畴与精神下，不同的修改、添加与替代都是可能的。

Claims (1)

1．一种芯片上引线型引线框架，它适合于在其上安装被分为两个独立电路块的芯片，所述两个独立电路块分别具有相对于芯片中心部位横向对称配置的焊盘对，所述引线框架包括：
多个延长的共同引线，每个共同引线适合与具有相同功能的包括分别以中心部位横向对称布置在两个独立电路块上的相应于电源线、控制信号、以及地址信号的各属于两个独立的电路块的焊盘对的每个焊盘进行引线键合，其中，相邻的共同引线沿相反方向横向延伸，且每个共同引线从芯片的中央部位直线地横向延伸，使引线超出芯片的边缘；以及
多个独立的引线，与分别布置在电路块上的焊盘引线键合并连接到输出输入信号。
CN97111828A 1996-06-24 1997-06-24 芯片上引线型引线框架 Expired - Fee Related CN1073283C (zh)

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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100427541B1 (ko) * 1997-06-30 2004-07-19 주식회사 하이닉스반도체 패턴 필름 제조 방법 및 이를 이용한 칩 모듈
US6268643B1 (en) * 1997-12-22 2001-07-31 Texas Instruments Incorporated Lead frame device for delivering electrical power to a semiconductor die
US6534861B1 (en) 1999-11-15 2003-03-18 Substrate Technologies Incorporated Ball grid substrate for lead-on-chip semiconductor package
KR100381892B1 (ko) * 1999-11-24 2003-04-26 삼성전자주식회사 듀얼-리드 타입 정방형 반도체 패키지 및 그를 사용한양면 실장형 메모리 모듈
US6445603B1 (en) 2000-08-21 2002-09-03 Micron Technology, Inc. Architecture, package orientation and assembly of memory devices
US6541849B1 (en) * 2000-08-25 2003-04-01 Micron Technology, Inc. Memory device power distribution
US6275446B1 (en) 2000-08-25 2001-08-14 Micron Technology, Inc. Clock generation circuits and methods
US8174099B2 (en) * 2008-08-13 2012-05-08 Atmel Corporation Leadless package with internally extended package leads
TW201530726A (zh) * 2014-01-29 2015-08-01 Eorex Corp 記憶體與記憶體儲存裝置
TWI539565B (zh) * 2014-01-29 2016-06-21 森富科技股份有限公司 記憶體與記憶體球位焊墊之佈局方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH039407A (ja) * 1989-06-06 1991-01-17 Fujitsu Ten Ltd 制御装置の検査方式

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5365113A (en) * 1987-06-30 1994-11-15 Hitachi, Ltd. Semiconductor device
KR0158868B1 (ko) * 1988-09-20 1998-12-01 미다 가쓰시게 반도체장치
JP2567961B2 (ja) * 1989-12-01 1996-12-25 株式会社日立製作所 半導体装置及びリ−ドフレ−ム
US5229329A (en) * 1991-02-28 1993-07-20 Texas Instruments, Incorporated Method of manufacturing insulated lead frame for integrated circuits
US5250840A (en) * 1992-02-24 1993-10-05 Samsung Electronics Co., Ltd. Semiconductor lead frame with a chip having bonding pads in a cross arrangement
SG44840A1 (en) * 1992-09-09 1997-12-19 Texas Instruments Inc Reduced capacitance lead frame for lead on chip package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH039407A (ja) * 1989-06-06 1991-01-17 Fujitsu Ten Ltd 制御装置の検査方式

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