CN1081833C - 绝缘体上硅薄膜晶体管 - Google Patents

绝缘体上硅薄膜晶体管 Download PDF

Info

Publication number
CN1081833C
CN1081833C CN96122891A CN96122891A CN1081833C CN 1081833 C CN1081833 C CN 1081833C CN 96122891 A CN96122891 A CN 96122891A CN 96122891 A CN96122891 A CN 96122891A CN 1081833 C CN1081833 C CN 1081833C
Authority
CN
China
Prior art keywords
oxide layer
silicon layer
thickness
region
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN96122891A
Other languages
English (en)
Other versions
CN1158009A (zh
Inventor
铃木裕二
高野仁路
铃村正彦
早崎嘉城
岸田贵司
白井良史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP01217396A external-priority patent/JP3210853B2/ja
Priority claimed from JP8012172A external-priority patent/JPH09205210A/ja
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Publication of CN1158009A publication Critical patent/CN1158009A/zh
Application granted granted Critical
Publication of CN1081833C publication Critical patent/CN1081833C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

Abstract

一种SOI(绝缘体上硅)型薄膜晶体管，包括掩埋氧化层、第一导电类型的硅层，以及上氧化层。硅层具有第二导电类型的体区、第一导电类型的源区、漏区以及漂移区。硅层形成有在其中形成掺杂区且厚度为T1的第一部分，以及在其中形成到达掩埋氧化层的体区且厚度为T2的第二部分。确定厚度T1和T2，以便满足以下关系式：0.4μm＜T1；0.4μm≤T2≤1.5μm；以及T2＜T1。此晶体管显示出改进的功耗、高的击穿电压和低的导通电阻，同时也具备制作工艺方法的优点。

Description

绝缘体上硅薄膜晶体管
本发明涉及SOI(绝缘体上硅)型薄膜晶体管，它具有改进的功耗、高的击穿电压和低的导通电阻。
过去，SOI-LDMOSFET(侧向双扩散金属氧化物半导体场效应晶体管)和IGBD(绝缘栅双极型晶体管)已作为功率晶体管而著称。作为SOI-LDMOSFET的一个例子，如图7所示第5,300,448号美国专利揭示一种具有线性掺杂分布的高压薄膜晶体管。该晶体管包括硅衬底10D、在硅衬底上形成的掩埋氧化层20D、在掩埋氧化层上形成的薄硅层30D，以及上氧化层40D。硅层30D)具有源区33D、体区31D、漏区32D，以及在其中形成线性掺杂区35D的漂移区34D。在上氧化层40D中，具有与漏区32D接触的漏极50D、与源区33D接触的源极60D，以及由栅氧化层41D从硅层30D上加以隔开的栅极70D。
例如，当把正电压加到栅极70D时，刚好在栅极下面体区31D的表面附近形成沟道，俾使电子通过此沟道及线性掺杂区35D从源区33D流向漏区32D，以获得源和漏区之间的导通状态。另一方面，当从栅极70D上移去正电压或把负电压加到栅极时，则沟道消失，以获得在源和漏区之间的截止状态。
通常，希望这种晶体管显示出源区33D和漏区32D之间高的击穿电压，以及低的导通电阻。因为硅层30D的厚度较薄，所以击穿电压倾向于降低。此已有技术通过在厚度2000到3000的硅层30D中形成线性掺杂区35D来实现低的导通电阻和高的击穿电压。然而，当硅层变薄时，引起漂移区34D的功耗问题，换句话说即热辐射。这将引起晶体管的热奔或击穿。图2示出当硅层变薄时，热阻增加。即，它意味着功耗随硅层变薄而降低。
另一方面，如图8所示，第5,246,870号美国专利则揭示一种高压薄膜晶体管。该晶体管包括n型或p型导电性的硅衬底10E、在硅衬底上形成的掩埋氧化层20E、在掩埋氧化层上形成的硅层30E，以及上氧化层40E。硅层30E具有n型导电性的源区33E、p型导电性的体区31E、n型导电性的漏区32E，以及具有侧向线性掺杂区35E的漂移区34E。硅层30E被绝缘材料的隔离区80E所包围。此晶体管也具有与漏区32E相接触的漏极50E、与体区31E和源区33E两者相接触的源极60E，以及由薄的栅氧化层41E从硅层30E上加以隔开的栅极70E。此已有技术通过在厚度为1000到2000的硅层30E中形成线性掺杂区35E来实现源和漏区(33E和32E)之间高的击穿电压和低的导通电阻。此外，栅极70E具有与其短路的场板71E。由于场板71E覆盖在线性掺杂区35E上面，所以漂移区34E得以很好地保护而不受外部电场的干扰，并使导通电阻进一步减少。
然而，由于硅层30E中线性掺杂区35E的厚度很薄，所以该晶体管在功耗声面具有与第5,300,448号美国专利的晶体管相同的问题。
本发明旨在一种用于改善上述问题的SOI(绝缘体上硅)型薄膜晶体管。也即，该晶体管包括在硅衬底上形成的掩埋氧化层、在掩埋氧化层上形成的第一导电类型的硅层，以及在硅层上形成的上氧化层。硅层具有第二导电类型的体区、第一导电类型的源区、第一导电类型的漏区，以及在源和漏区之间形成的第一导电类型的漂移区。在体区中形成源区，以与掩埋氧化层相隔开。此晶体管也具有与体区和源区两者相接触的源极、与漏区接触的漏极，以及位于源和漏极之间并由薄的氧化层与硅层相隔开的栅极。在本发明中，形成的硅层具有两种厚度，其中厚度为(T1)的第一部分形成有漂移区，而厚度为(T2)的第二部分中则形成有到达掩埋氧化层的体区。确定厚度(T1)和(T2)，以便满足以下关系式：
0.4μm＜T1
0.4μm≤T2≤1.5μm
T2＜T1
具有上述结构的本发明表现出改进的功耗、高的击穿电压，以及低的导通电阻，并在晶体管的制作工艺上其备多种优点。当厚度T1小于0.4μm时，不足以改善功耗，也即漂移区的热辐射。当厚度T2小于0.4μm时，引起在体区中形成的源区到达掩埋氧化层的问题，这是因为用常规的硅工艺技术不能把源区的扩散深度抑制在小于大约0.3μm。这降低了晶体管的击穿电压。另一方面，当厚度T2大于1.5μm时，很难在硅层中有效地形成体区。也即，必须在高温下和/或很长的时间内进行热处理，以形成体区。这导致高的芯片制作成本。此外，这样的热处理可引起晶体管性质的变化。将在以后详细描述此晶体管制作工艺中的另外一些优点。
第一部分的厚度T1最好是1μm或更大，以进一步改善漂移区的功耗。
在本发明的较佳实施例中，在硅层的上表面形成从第二部分向第一部分延伸的斜坡。体区沿此斜坡从第二部分伸向第一部分。栅极具有一场板，此场板与斜坡平行并中薄氧化层以与斜坡隔开的关系延伸。由于刚好在栅极下面体区斜坡的附近形成倾斜的沟道，以获得在源和漏区之间的导通状态，所以此晶体管可提供更低的导通电阻。
在本发明的另一个较佳实施例中，漂移区形成有线性掺杂区。特别是栅极最好具有一场板，该场板与栅极短路，且使栅极和场板最好以与硅层隔开的关系沿侧向延伸，而不覆盖在线性掺杂区上面。这提供在源和漏区之间较高的击穿电压。
漏区最好与掩埋氧化层隔开。当在硅层的第二部分中形成体区以达到掩埋氧化层时，在硅层中形成漏区，以与掩埋氧化层隔开，则可进一步增加击穿电压。
从以下结合附图对本发明较佳实施例所进行的描述中，本发明的这些以及另外的目的和优点将变得明显起来。
图1是本发明第一实施例薄膜晶体管的剖面图；
图2示出热阻和硅层厚度之间的关系；
图3是厚度(T2)小于0.4μm的一部分硅层的剖面图；
图4示出用LOCOS方法形成隔离区的二氧化硅厚度和氧化时间之间的关系；
在图5A和5B中，图5A是本发明第二实施例薄膜晶体管的剖面图，图5B则示出击穿电压V和场板与图5A中侧向线性掺杂区之间侧向距离L之间的关系；
图6是第二实施例改进型的薄膜晶体管的剖面图；
图7是已有技术薄膜晶体管的剖面图；以及
图8是已有技术薄膜晶体管的剖面图。
第一实施例
如图1所示，SOI型薄膜晶体管包括n型硅衬底10、在此硅衬底上形成的掩埋氧化层20、在掩埋氧化层上形成的n型硅层30，以及上氧化层40。硅层30具有p型体区31、n型漏区32、n型源区33，以及n型漂移区34。漂移区34在体区31和漏区32之间延伸。在体区31中形成源区33。在上氧化层40中，具有与漏区32接触的漏极50、与体区31和源区33两者相接触的源极60，以及位于源和漏极之间并由薄的栅氧化层41与硅层30相隔开的栅极70。栅极70具有与栅极短路的场板71。硅层30形成有厚度为T1的第一部分38和厚度为T2的第二部分36。在此实施例中，厚度T1和T2分别是1.0μm和0.5μm。漂移区34在第一部分38中侧向延伸。在第一部分38中也形成漏区32，以与掩埋氧化层20隔开。在第二部分36中形成体区31和源区33，俾使体区到达掩埋氧化层20，以增加漏和源区之间的击穿电压，而源区33则与掩埋氧化层20相互隔开。
当把正电压加到栅极70时，则刚好在栅极70下面体区31的表面附近形成n型沟道，以致有电子从源区33通过此沟道和漂移区34流向漏区32，以获得在源和漏区之间的导通状态。另一方面当从栅极70上移去正电压或把负电压加到栅极时，则沟道消失以获得在源和漏区之间的截止状态。
图2示出热阻和硅层厚度之间的关系。它表明热阻随硅层30变薄而增加。因此，当第一部分38的厚度T1变薄时，漂移区34的功耗减少。当厚度T1小于0.4μm时，有可能引起晶体管的热奔。在此实施例中，确定厚度T1为1μm，以改善功耗。当厚度T1增加到大于0.4μm时，漂移区34的功耗可得以改善。此外，当厚度T1增加到大于0.4μm而小于5μm的范围内时，则晶体管的导通电阻降低。
当第二部分36的厚度T2小于0.4μm时，则因用常规的硅工艺技术不能把源区的扩散厚度抑制到小于大约0.3μm，而导致在体区31中形成的源区33到达掩埋氧化层20的问题。也即，如图3所示，当厚度T2小于0.4μm时，体区31被延伸在源极60和掩埋氧化层20之间的源区33分成与源极60接触的第一小区31a，和面对栅极70的第二小区31b。在此情形下，由于第二小区31b保持在电漂浮状态，因而使晶体管的击穿电压降低。
当第二部分36的厚度T2大于1.5μm时，则导致晶体管制作工艺中的以下问题。即，晶体管通常具有在第二部分36中向外形成的隔离区80，用以使硅层30与靠近该晶体管待安装的器件在电学上相互绝缘。可用LOCOS(硅的局部氧化)方法形成隔离区80。LOCOS包括以下步骤：在硅衬底上沿预定的构图形成氮化硅薄膜，然后在氧化气氛中对硅衬底进行热处理。由于热处理期间氧原子不能通过氮化硅薄膜扩散进入硅衬底，故硅衬底的裸露硅表面得以选择性地氧化。当用LOCOS方法形成隔离区80时，在靠近隔离区的厚度为T2的硅层30上进行硅的氧化。因此，当厚度T2增加时，需较长的氧化时间形成隔离区80。例如，图4示出用LOCOS方法形成隔离区的二氧化硅的厚度与氧化时间之间的关系，这是在1100℃的氧化温度下测量的。它表示二氧化硅的厚度随氧化时间的延长而逐渐增加，并在大约1.5μm处饱和。由此关系，可以理解，在LOCOS方法采用的1100℃的标准氧化温度下形成厚度大于1.5μm的隔离区是困难的。因此，第二部分36的厚度T2确定为1.5μm或更小，以有效且容易地形成靠近硅层30的隔离区80。
此外，在氧化处理期间逐渐氧化LOCOS方法中所使用的氮化硅薄膜。因此，当隔离区的厚度增加时，为了防止氮化硅薄膜正下方硅的氧化需要较厚的氮化硅薄膜。然而，产生的问题是形成厚的氮化硅薄膜要花费很长的淀积时间，且由于厚氮化硅薄膜的内部应力较大可引起厚氮化硅薄膜的开裂或SOI大圆片的翘曲。因此，第二部分36的厚度T2确定为1.5μm或更小，以防止产生这些问题。
此外，当用LOCOS方法形成隔离区时，刚好位于氮化硅薄膜周边部分以下的硅层倾向于被局部氧化。通常称此硅层的氧化区为“鸟嘴”。鸟嘴区随隔离区厚度的增加而扩大。在扩大的鸟嘴区中发生的应力集中或晶格缺陷将对晶体管的性质户生坏的影响。在本发明中，确定第二部分36的厚度T2为1.5μm或更小，以控制鸟嘴区的形成为最小。
此外，由于在硅层30的第二部分36中形成的体区31至掩埋氧化层20，所以当厚度T2大于1.5μm时，必须在较高的温度下和/或在较长的时间内进行热处理，以形成体区31。再此，这样的热处理有可能引起晶体管性质的改变。因此，为了有效而稳定地在硅层30中形成体区31，把第二部分36的厚度T2确定为1.5μm或更小。
总之，由于硅层30形成有厚度T1大于0.4μm的第一部分38，以及厚度T2确定为0.4μm到1.5μm且小于厚度T1的范围内的第二部分36，故此晶体管可提供以下优点：
(1)在第一部分38中形成的漂移区34表现出改进的功耗、高的击穿电压，以及低的导通电阻；
(2)可通过较低温度下较短时间的热处理，在第二部分36中有效而容易地形成体区31至掩埋氧化层20。
(3)在LOCOS方法中无需用厚的氮化硅薄膜可靠近第二部分36容易地形成隔离区80，而与此同时把鸟嘴区控制到最小。
第二实施例
如图5A所示，除了以下的特点外，第二实施例的SOI型薄膜晶体管的结构基本上与第一实施例中的晶体管相同。因此，不必对共同的部分和操作进行重复的描述。相似的部分由具有后缀字母“A”的相似标号表示。
在厚度T1为1.0μm的第一部分38A中形成n型漂移区34A。漂移区34A具有沿第一部分38A的侧向延伸的线性掺杂区35A。掺杂区35A的掺杂浓度沿从p型体区31A向n型漏区32A的方向逐渐增加。可用第5,300,448号美国专利中描述的方法形成掺杂区35A。在上氧化层40A中形成栅极70A，它具有与其短路的场板71A。如图5A所示，上氧化层40A的栅极70A和场板71A以与硅层30A隔开的关系侧向延伸，且不覆盖在掺杂区35A上面。图5B中示出击穿电压V和介于掺杂区35A与具有场板71A的栅极70A之间的侧向距离L之间的关系。当用一负值表示距离L时，它意味着栅极70A和场板71A两者都以距离L从掺杂区35A侧向位移。在负的距离L内，击穿电压保持在大约450V。另一方面，当用一正值表示距离L时，则意味着栅极70A和场板71A中的至少一个以距离L覆盖在掺杂区35A上面。图5B示出当正的距离L增加时击穿电压快速降低。因此，当在漂移区34A中形成掺杂区35A时，上氧化层40A的栅极70A和场板71A两者最好都侧向延伸而不覆盖在掺杂区35A上面。
硅层30A在其上表面形成有从厚度T2为0.5μm的第二部分36向具有厚度T1的第一部分38A延伸的斜坡。体区31A沿斜坡37A从第二部分36A伸向第一部分38A，并到达掩埋氧化层20A。场板71A随斜坡37A平行地延伸，并由薄的氧化层41A与体区31A相隔开。当对栅极70A施加以正电压时，则在体区31A的表面附近沿斜坡37A形成倾斜的沟道，致使电子通过此倾斜的沟道和掺杂区35A从n型源区33A流向漏区32A，以获得在源和漏区之问的导通状态。倾斜的沟道使晶体管的导通电阻减少。此外，当在硅层30A中形成31A至掩埋氧化层20A，而漏区32A在硅层30A中延伸，以与掩埋氧化层20A相隔开，则可进一步增加源和漏区之间的击穿电压。
作为第二实施例的改进，如图6所示，在硅层30B的具有厚度T2为0.8μm的第二部分可侧向并向外形成具有厚度T3为0.5μm的第三部分39B。除了以下特点外，此改进的薄膜晶体管的结构与第二实施例中晶体管的结构基本上相同。因此，不必对共同的部分和操作进行描述。相似的部分由具有后缀字母“B”的相似标号来表示。
在硅层30B的具有厚度T1为1.4μm的第一部分38B中形成n型漂移区34B、侧向线性掺杂区35B，以及n型漏区32B。在第二部分36B中形成p型体区31B。在此改进中，由于在靠近具有厚度T3小于厚度T2的第三部分39B处形成隔离区80B，故有可能增强用LOCOS方法形成隔离区80B。
在上述实施例中，使用通过打磨和抛光经键合的SOI衬底获得的SOI衬底。然而，替代SOI衬底，可以使用以SIMOX(由注入氧分离)、BE(经键合和刻蚀)形成的SOI衬底、通过在绝缘衬底上外延生长单晶硅而形成的SOI衬底，或者由灵巧切割(Smart Cut)技术形成的SOI衬底。

Claims (7)

1.一种绝缘体上的硅型薄膜晶体管，包括：
在半导体衬底上形成的掩埋氧化层；
在所述掩埋氧化层上形成的第一导电类型的硅层，所述硅层具有第二导电类型的体区、所述第一导电类型的源区、所述第一导电类型的漏区，以及在所述源和漏区之间形成的所述第一导电类型的漂移区，在所述体区中形成所述源区，以与所述掩埋氧化层相隔开；
在所述硅层上形成上氧化层；
与所述体区和所述源区两者相接触的源极；
与所述漏区接触的漏极；以及
位于所述源和漏极之间并由薄的氧化层与所述硅层相隔开的栅极；
其特征在于所述硅层形成有在其内形成漂移区且厚度为T1的第一部分，以及在其内形成到达所述掩埋氧化层的所述体区且厚度为T2的第二部分，以及其中所述的厚度T1和T2，为此加以确定，俾使满足以下关系式：
0.4μm＜T1
0.4μm≤T2≤1.5μm
T2＜T1。
2.如权利要求1所述的薄膜晶体管，其特征在于所述第一和第二导电类型分别是n型和p型。
3.如权利要求1所述的薄膜晶体管，其特征在于所述漂移区形成有侧向的线性掺杂区。
4.如权利要求3所述的薄膜晶体管，其特征在于所述栅极具有与所述栅极短路的场板，其中所述栅极和场板以与硅层隔开的关系沿侧向延伸，而不覆盖在所述线性掺杂区上面。
5.如权利要求1所述的薄膜晶体管，其特征在于所述厚度T1是1μm或更大。
6.如权利要求1所述的薄膜晶体管，其特征在于在所述硅层的上表面形成从所述第二部分向所述第一部分延伸的斜坡，所述体区沿所述斜坡从所述第二部分伸向所述第一部分，所述栅极具有一场板，它与所述斜坡平行并以由所述薄氧化层与所述斜坡隔开的关系延伸。
7.如权利要求1所述的薄膜晶体管，其特征在于在所述硅层中形成所述漏区，以与所述掩埋氧化层相隔开。
CN96122891A 1996-01-26 1996-10-30 绝缘体上硅薄膜晶体管 Expired - Fee Related CN1081833C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP01217396A JP3210853B2 (ja) 1996-01-26 1996-01-26 半導体装置
JP012173/96 1996-01-26
JP012172/96 1996-01-26
JP8012172A JPH09205210A (ja) 1996-01-26 1996-01-26 誘電体分離型半導体装置

Publications (2)

Publication Number Publication Date
CN1158009A CN1158009A (zh) 1997-08-27
CN1081833C true CN1081833C (zh) 2002-03-27

Family

ID=26347747

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96122891A Expired - Fee Related CN1081833C (zh) 1996-01-26 1996-10-30 绝缘体上硅薄膜晶体管

Country Status (7)

Country Link
US (1) US5780900A (zh)
EP (1) EP0786818B1 (zh)
KR (1) KR100249290B1 (zh)
CN (1) CN1081833C (zh)
DE (1) DE69634745T2 (zh)
HK (1) HK1000853A1 (zh)
TW (1) TW360982B (zh)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3527034B2 (ja) * 1996-09-20 2004-05-17 株式会社半導体エネルギー研究所 半導体装置
SG67518A1 (en) 1997-06-30 1999-09-21 Matsushita Electric Works Ltd Solid-state relay
US6346451B1 (en) * 1997-12-24 2002-02-12 Philips Electronics North America Corporation Laterial thin-film silicon-on-insulator (SOI) device having a gate electrode and a field plate electrode
US6310378B1 (en) 1997-12-24 2001-10-30 Philips Electronics North American Corporation High voltage thin film transistor with improved on-state characteristics and method for making same
KR100257765B1 (ko) * 1997-12-30 2000-06-01 김영환 기억소자 및 그 제조 방법
JPH11297941A (ja) * 1998-04-09 1999-10-29 Nec Corp 半導体装置
US5969387A (en) * 1998-06-19 1999-10-19 Philips Electronics North America Corporation Lateral thin-film SOI devices with graded top oxide and graded drift region
US6232636B1 (en) * 1998-11-25 2001-05-15 Philips Electronics North America Corporation Lateral thin-film silicon-on-insulator (SOI) device having multiple doping profile slopes in the drift region
US6127703A (en) * 1999-08-31 2000-10-03 Philips Electronics North America Corporation Lateral thin-film silicon-on-insulator (SOI) PMOS device having a drain extension region
US6221737B1 (en) * 1999-09-30 2001-04-24 Philips Electronics North America Corporation Method of making semiconductor devices with graded top oxide and graded drift region
US6369408B1 (en) * 1999-10-06 2002-04-09 Agere Systems Guardian Corp. GaAs MOSFET having low capacitance and on-resistance and method of manufacturing the same
US6166411A (en) * 1999-10-25 2000-12-26 Advanced Micro Devices, Inc. Heat removal from SOI devices by using metal substrates
US6483147B1 (en) 1999-10-25 2002-11-19 Advanced Micro Devices, Inc. Through wafer backside contact to improve SOI heat dissipation
US6191453B1 (en) * 1999-12-13 2001-02-20 Philips Electronics North America Corporation Lateral insulated-gate bipolar transistor (LIGBT) device in silicon-on-insulator (SOI) technology
TW564557B (en) * 1999-12-22 2003-12-01 Matsushita Electric Works Ltd Semiconductor device and process for producing the same
US6552395B1 (en) 2000-01-03 2003-04-22 Advanced Micro Devices, Inc. Higher thermal conductivity glass for SOI heat removal
US6613643B1 (en) 2000-01-28 2003-09-02 Advanced Micro Devices, Inc. Structure, and a method of realizing, for efficient heat removal on SOI
US6847081B2 (en) * 2001-12-10 2005-01-25 Koninklijke Philips Electronics N.V. Dual gate oxide high-voltage semiconductor device
KR100489802B1 (ko) * 2002-12-18 2005-05-16 한국전자통신연구원 고전압 및 저전압 소자의 구조와 그 제조 방법
US7501669B2 (en) 2003-09-09 2009-03-10 Cree, Inc. Wide bandgap transistor devices with field plates
DE102004005948B4 (de) 2004-02-02 2009-04-02 Atmel Germany Gmbh MOS-Transistor und Verfahren zur Herstellung einer MOS-Transistorstruktur
CN100421255C (zh) * 2004-04-28 2008-09-24 台湾积体电路制造股份有限公司 完全耗尽型soi多临界电压应用
US7550783B2 (en) * 2004-05-11 2009-06-23 Cree, Inc. Wide bandgap HEMTs with source connected field plates
US7573078B2 (en) * 2004-05-11 2009-08-11 Cree, Inc. Wide bandgap transistors with multiple field plates
US9773877B2 (en) * 2004-05-13 2017-09-26 Cree, Inc. Wide bandgap field effect transistors with source connected field plates
US7829400B2 (en) * 2005-01-12 2010-11-09 Sharp Kabushiki Kaisha Semiconductor device fabrication method and semiconductor device
US7217604B2 (en) * 2005-01-31 2007-05-15 International Business Machines Corporation Structure and method for thin box SOI device
US11791385B2 (en) * 2005-03-11 2023-10-17 Wolfspeed, Inc. Wide bandgap transistors with gate-source field plates
US20060255377A1 (en) * 2005-05-12 2006-11-16 Der-Wei Tu Field effect transistor with novel field-plate structure
JP5105160B2 (ja) 2006-11-13 2012-12-19 クリー インコーポレイテッド トランジスタ
US7598128B2 (en) * 2007-05-22 2009-10-06 Sharp Laboratories Of America, Inc. Thin silicon-on-insulator double-diffused metal oxide semiconductor transistor
JP5479671B2 (ja) 2007-09-10 2014-04-23 ローム株式会社 半導体装置
US9679981B2 (en) 2013-06-09 2017-06-13 Cree, Inc. Cascode structures for GaN HEMTs
US9847411B2 (en) 2013-06-09 2017-12-19 Cree, Inc. Recessed field plate transistor structures
US10026830B2 (en) * 2015-04-29 2018-07-17 Stmicroelectronics, Inc. Tunneling field effect transistor (TFET) having a semiconductor fin structure
US11195915B2 (en) * 2019-04-15 2021-12-07 Texas Instruments Incorporated Semiconductor devices with a sloped surface

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5246870A (en) * 1991-02-01 1993-09-21 North American Philips Corporation Method for making an improved high voltage thin film transistor having a linear doping profile

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922327A (en) * 1987-12-24 1990-05-01 University Of Toronto Innovations Foundation Semiconductor LDMOS device with upper and lower passages
US5362979A (en) * 1991-02-01 1994-11-08 Philips Electronics North America Corporation SOI transistor with improved source-high performance
EP0497427B1 (en) 1991-02-01 1996-04-10 Koninklijke Philips Electronics N.V. Semiconductor device for high voltage application and method of making the same
JP2731056B2 (ja) * 1991-10-09 1998-03-25 シャープ株式会社 薄膜トランジスタの製造方法
DE69316256T2 (de) * 1992-03-26 1998-08-06 Texas Instruments Inc Hochspannungstruktur mit oxydisolierter Source und RESURF-Drift-Zone in Massivsilizium
US5548150A (en) * 1993-03-10 1996-08-20 Kabushiki Kaisha Toshiba Field effect transistor
JP3217554B2 (ja) * 1993-09-17 2001-10-09 株式会社東芝 高耐圧半導体装置
US5378912A (en) * 1993-11-10 1995-01-03 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a lateral drift region
US5510275A (en) * 1993-11-29 1996-04-23 Texas Instruments Incorporated Method of making a semiconductor device with a composite drift region composed of a substrate and a second semiconductor material
US5382818A (en) * 1993-12-08 1995-01-17 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5246870A (en) * 1991-02-01 1993-09-21 North American Philips Corporation Method for making an improved high voltage thin film transistor having a linear doping profile

Also Published As

Publication number Publication date
EP0786818B1 (en) 2005-05-18
US5780900A (en) 1998-07-14
DE69634745D1 (de) 2005-06-23
CN1158009A (zh) 1997-08-27
KR100249290B1 (ko) 2000-03-15
DE69634745T2 (de) 2006-02-23
TW360982B (en) 1999-06-11
EP0786818A2 (en) 1997-07-30
HK1000853A1 (en) 2002-08-23
EP0786818A3 (en) 1998-03-25
KR970060530A (ko) 1997-08-12

Similar Documents

Publication Publication Date Title
CN1081833C (zh) 绝缘体上硅薄膜晶体管
US11610992B2 (en) Semiconductor device
US8237195B2 (en) Power MOSFET having a strained channel in a semiconductor heterostructure on metal substrate
CN1230880C (zh) 一种制造功率mos场效应管的方法
CN1175496C (zh) 具有栅电极和场板电极的横向薄膜绝缘体上硅（soi）器件
US5747831A (en) SIC field-effect transistor array with ring type trenches and method of producing them
CN1734784A (zh) 绝缘横向双扩散金属氧化物半导体（ldmos）集成电路技术
CN1726585A (zh) 沟槽－栅极半导体器件的制造方法
CN1591798A (zh) 在用于半导体器件的硅或碳化硅上形成厚氧化物的工艺
CN1075246C (zh) 半导体器件及其制造方法
CN102171827A (zh) 碳化硅半导体器件
CN1725508A (zh) 横向双扩散金属氧化物半导体ldmos元件及其加工方法
KR102188398B1 (ko) 산화물 반도체 박막 트랜지스터의 제조 방법
WO2006134810A1 (ja) 半導体デバイス
CN1976060A (zh) 具有介质应力产生区的晶体管及其制造方法
EP0504992A2 (en) A lateral insulated gate field effect semiconductor device
US20130168667A1 (en) Thin film transistor
KR20010033905A (ko) 측방향 디플리션이 있는 측방향 박막 실리콘 온 절연체디바이스
EP4270490A1 (en) Mosfet device and manufacturing method therefor
KR100290913B1 (ko) 고전압 소자 및 그 제조방법
TW441111B (en) Lateral thin-film silicon-on-insulator (SOI) device having multiple doping profile slopes in the drift region
CN111081778A (zh) 一种碳化硅沟槽型mosfet器件及其制造方法
CN1941386A (zh) 半导体器件
CN1110859C (zh) 双极型晶体管及其制造方法
WO2013084498A1 (en) Semiconductor device

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20020327

Termination date: 20131030