CN1094851A - 晶体管、半导体电路及其制造方法 - Google Patents

晶体管、半导体电路及其制造方法 Download PDF

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CN1094851A
CN1094851A CN94102725A CN94102725A CN1094851A CN 1094851 A CN1094851 A CN 1094851A CN 94102725 A CN94102725 A CN 94102725A CN 94102725 A CN94102725 A CN 94102725A CN 1094851 A CN1094851 A CN 1094851A
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silicon film
catalytic elements
amorphous silicon
concentration
film
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CN1126179C (zh
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张宏勇
鱼地秀贵
高山彻
竹村保彦
山本睦夫
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Abstract

形成一种包含催化剂的物质以同非晶硅膜紧密 接触，或将催化剂导入非晶硅膜。在低于通常非晶硅 结晶温度下热处理非晶硅膜，使其有选择地晶化。该 结晶区用作能用于有源矩阵电路的外部驱动电路中 的结晶硅TFT。保持非晶态的区用作可用于象素电 路中的非晶硅TFT。本发明可在同一衬底上用同一 工艺形成高速操作的结晶硅TFT和漏电流小的非 晶硅TFT，从而大大增强了批量生产率和改善了产 品诸性能。

Description

本发明涉及薄膜晶体管（TFT）和制造该晶体管的方法，还涉及具有多个薄膜晶体管（TFTs）和半导体电路及其制造方法。根据本发明产生的薄膜晶体管可在诸如玻璃之类的绝缘衬底上和在诸如单晶硅之类的半导体衬底两者之一上形成。尤其是，本发明涉及这样一种半导体电路，它包括在低速下工作诸如单片有源矩阵电路（可用于液晶显示器之类）的矩阵电路和一个驱动该有源矩阵电路并在高速下工作的外部电路。本发明还涉及通过根据热处理晶体化和活化而产生的薄膜晶体管。
近来，人们对具有薄膜活化层（active    layer）（还称之为活化区）的绝缘栅半导体器件进行了种种研究。特别对薄膜绝缘栅半导体器件或称为薄膜晶体管（TFTs）进行了努力研究。这类薄膜晶体管在透明绝缘衬底上如此形成以便能用于控制具有矩阵结构的在液晶显示器等驱动电路内的象素。薄膜晶体管根据所用半导体材料的种类和结晶状态分为非晶体硅TFT以及结晶硅两类。
非晶态的半导体一般其电场渗透率（field    mobility）小，因而不能用于必须以高速操作的TFT中。再者，由于P型非晶硅的电场迁移率极低，故不可能生产P沟道TFT（PMOS    TFT）。因此，不可能制造由P沟道TFT和N沟道TFT（NMOS    TFT）组合成一个完整MOS电路（CMOS）。
相反，晶体半导体具有比非晶体半导体较高的电场迁移率，因而能以高速操作。当采用结晶硅时，由于能以相同方式既可制造NMOS    TFT也可制造PMOS    TFT，故有可能制造CMOS电路。例如，一种有源矩阵型的已知液晶显示器件具有所谓单片结构，即由CMOS晶体TFT既构成有源矩阵区也构成外部电路（包括驱动电路等）。由于这些原由，人们对使用结晶硅的TFT进行了强有力的研究和开发。
在为获得结晶硅的一种方法实例中，是用激光或相当于激光的强光辐照非晶体硅而使其晶体化。然而，由于激光输出的不稳定性和由于极短工艺周期的不稳定性，该方法不具备批量生产或实际应用的前景。
如今可实际运用的一种方法是将非晶硅经加热使其结晶化的方法。按此法，有可能获得各批生产量之间变化很小的结晶硅。但该法有一个问题。
一般说来，结晶硅的形成要求长时间在大约600℃下进行热处理，或在1000℃高温或更高温下进行热处理。在运用后一种方法的情况下，可选衬底限于石英制造的衬底，导致衬底的成本极高。在应用前一种方法情况下，衬底可选范围广但又引起另一问题。
当使用廉价的无碱玻璃衬底（例如，由corning公司生产的7059号）时，传统的生产TFT工艺大致以下列方式进行：
（1）形成非晶硅膜;
（2）非晶硅膜的结晶（600℃或更高，24小时或更长）;
（3）形成绝缘栅膜;
（4）形成栅电极;
（5）引入掺杂（用离子植入法或离子掺杂法）;
（6）激活掺杂（600℃或更高，24小时或更长）;
（7）形成绝缘层;和
（8）形成源极和漏极。
在此工艺过程中，步骤（2）和（6）存有一些问题。多种无碱玻璃具有大约600℃的畸变温度（在Cornign    7059情况下为593℃）。在这种温度下的工艺过程引起诸如衬底收缩和弯曲之类的问题。在步骤（2），这是第一热处理工序，由于还未进行形成图案工艺（patterning    process），衬底的收缩不会引起严重问题。然而，在步骤（6），那时已经过图案形成工艺。所以在步骤（6），当衬底收缩时，在此后的一系列步骤中不能正确进行掩模对齐，从而构成损坏成品的主要原因。因此，人们希望在低于衬底畸变温度下进行步骤（2）的工艺，和在更低的温度下（最好在低于玻璃畸变温度50℃或更低的温度，更可取的是在低于步骤（2）最大工艺温度50℃或更低温度下）进行步骤（6）的工序。
为满足这些要求，可运用如上所述的使用激光之类的一种方法。然而，除了激光器输出不稳定的问题外，人们已觉察到的另一问题是由于受激光束辐照的那部分（源和漏区）和未受激光束辐照的那部分（有源区，即栅极下面的那个区域）之间出现的温度差所产生的应力，从而有损于可靠性。
另一方面，由非晶体半导体制成的TFT具有截止电流低的特性。因此这种TFT应用于不要求很高操作速度的液晶显示器的有源矩阵和象素电路中晶体管之类的用途中，在这种显示器中，仅仅单导电率型就足够了，并需要具有高度保持电荷的能力。然而，这种TFT不能应用于必须高速操作的外部电路中。
在一种结晶体硅TFT中，当无电压施加到栅极时（即，非选择周期期间），流过的漏电流大于在非晶硅TFT中的漏电流。当液晶显示器中使用结晶硅TFT时，采取配置用于补偿漏电流的辅助电容器及将两个TFT串联连接的措施，以减小漏电流。
图5示出一种用于液晶显示器的有源矩阵电路的方块图。衬底107上配置有作为外部电路的列译码器101和行译码器102。各包括一晶体管和一电容器的象素电路104形成在矩阵区103中。矩阵区和外部电路通过导线105和106彼此连接。用于外部电路的TFT需要具有高速性能，而在象素电路中所用的TFT需要有低的漏电流的性能。虽然这些性能实际上是互相矛盾的，但又要求在同一衬底上并通过同一工艺形成两种类型的TFT。
一般说来，结晶硅的形成要求长周期并在大约600℃下的热处理，或在高温1000℃或更高温的热处理。例如，要在同一衬底上制成具有高迁移率的多晶硅TFT组成的外部电路和利用高截止（OFF）电阻的非晶硅TFT结构是不可能的，因为非晶硅在上述热处理工序中被晶体化。
因此，从批量生产的观点出发，运用在生产TFT过程中用激光器的方法是困难的。另一方面，本领域的现状是找不到其他有效的方法。为解法这些难题，已导出本发明。本发明的一个目的是为在保持批量生产性的同时解决这些问题。
为解决这些难题，现已实施了该发明。然而，一种改进结构导致工艺复杂，产量较低和成本较高并不是人们所期望的。本发明的一个目的是通过在保持批量生产性的同时以最少地改变工艺过程使要求高迁移率的TFT和要求低漏电流的TFT这两种TFT能有选择地以简单方式产生。
本发明人的研究成果表明：将少量催化物质添加到非晶硅薄膜，便增强了结晶作用，降低了晶体形成的温度并缩短了结晶时间。至于催化材料，象镍（Ni），铁（Fe），钴（Co），铂（Pt）之类的简单物质或其化合物如硅化物是合适的。实际上，非晶硅薄膜可通过在非晶硅膜下面或上面形成膜，晶粒，或这些催化元素的族（cluster）或通过用象离子注入之类的方法在非晶硅膜中引入这些催化元素的方式;接着在适当温度下，一般在580℃或低些的温度下对非晶硅膜进行热处理而晶化。
在用化学汽相淀积法（CVD法）形成非晶硅膜的情况下，可将这些催化剂加入某种材料气体中;在用象溅射之类的物理气相法形成非晶硅膜的情况下，可将这些催化剂添加入象耙或淀积源的淀积材料中。虽然这是一种自然结果，但热处理的温度越高，晶化的时间就越短。此外，镍，铁，钴，铂的浓度越高，则晶化的温度越低而且结晶过程的时间越短。经本发明人的研究已发现，为增强结晶作用，至少一种元素的浓度应为1×1017cm-3或更多，最好为5×1018cm-3或更多。
此外，应注意：没有象这种催化材料的区域根本不会增强晶化作用，并能保持非晶态。例如，浓度为1017cm-3或更小，最好为1×1016cm-3或更小的非晶体在600℃或更高温度下开始结晶，但在580℃或更低温度下根本未加强结晶。不过，由于非晶硅中平衡空键（neutralizing dangling bonds）所需的氢气在300℃或更高的环境中被释放，故为获得适当的半导体特性最好在氢气气氛中进行热处理。
在本发明中，利用在上述催化材料作用下的晶化特性去形成非晶硅膜。其一部分被有选择地晶化并用作有源矩阵电路的外部电路中的结晶硅TFT。非晶态的另一部分被用作矩阵区（象素电路）中的非晶硅TFT。结果，可在同一衬底上同时形成具有低的漏电流和快动作的相反特性之晶体管电路。
由于上述催化材料之任一种对硅都是不理想的材料，故最好它们的浓度尽可能地低。在本发明人的研究中，为尤其用其作为活性区，这些催化材料的浓度最好总量不高于1020cm-3，以获得令人满意的可靠性和特性。另一方面，事实表明：即使在源，漏之类中存在相当大量催化材料，也不是问题。
本发明人发现，上述诸问题可通过把注意力集中在这一催化元素的效果上并加以利用而得以解决。本发明TFT的制造方法简要说明如下：
1）淀积非晶硅膜
1′）导入催化元素（用离子注入或离子掺杂法）
2）非晶硅膜的结晶（在600℃或低些，8小时范围内）
3）淀积绝缘栅膜
4）形成栅电极
5）引导掺入的杂质（用离子注入或离子掺杂法）
5′）将有催化元素的材料淀积到硅膜
6）激活掺入的杂质（600℃或低些，8小时范围内）
7）形成夹层绝缘体
8）形成源漏电极
或，
1）淀积非晶硅膜
1′）引导催化元素（用离注入或离子掺杂法）
2）非晶硅膜的晶化（600℃或稍低，8小时范围内）
3）绝缘栅膜的淀积
4）形成栅极
5）引入掺入的杂质（用离子注入或离子掺杂法）
5′）引入催化元素（用离子注入或离子掺杂法）
6）激活掺入的杂质（600℃或稍低，8小时范围内）
7）形成夹层绝缘体
8）形成源，漏极
在这些工序中，次序5）和5′）可颠倒。工序1′）可被替换成″将含有催化元素的薄膜之类粘接在非晶硅膜上或下面的工序″。从精确控制催化元素的浓度观点出发，象离子注入之类的方法是理想的。但从简化工序和紧缩设备资金的观点来看，若所得到的TFT特性是令人满意的，则可利用该方法。
在本发明中，通过所述工序1′）引入到非晶硅膜的催化元素大大增强了其结晶作用。另一方面，通过5′）主要导入到源，漏区的催化元素大大增强了该区域的再结晶作用。因此，对于结晶和激活来说，600℃或低些，一般为550℃或稍低温度便够了。8小时的热处理时间范围，一般4小时内也够了。特别当用离子注入法或离子掺杂法开始均匀分布催化元素时，结晶过程极易进行。
在本发明中，由于采用任一工艺方法使栅极存在于活化区上，故催化元素将未在工序5′）直接被粘附或注入到活化区。因此，改变活化区和杂质区中的催化元素的浓度是可能的。例如，通过相对减小要加到活化区的催化元素的浓度，最大限度地减小了对TFT的特性和可靠性的坏影响。通过增大要加到杂质区的催化元素的浓度，抑制了衬底的收缩和畸变，在相当低温下激活，并可增加产量。TFT的可靠性和特性几乎无损失。
在本发明中，厚度为1000
Figure 941027252_IMG2
或稍薄的非晶硅膜也是经催化元素而晶化的。这种非晶硅膜将不是由通常热处理而结晶的。从防止TFT的这一步骤部分的针孔（pinhole）和绝缘性的缺陷，和避免栅极-栅极的断接的观点出发，结晶硅膜的厚度要求1000A或更薄，最好为500
Figure 941027252_IMG3
或更薄。这是非用激光器结晶作用方法是得不到的，但本发明是通过甚至在低温下的加热处理而获得这一点的。自然这有助于产品的进一步改善。现将利用几个实施例更详细地进一步说明本发明。
图1（A）至1（E）是显示实施例1中所进行的生产过程诸步骤的截面视图;
图2（A）至2（E）是显示实施例2中所进行的生产过程诸步骤的截面视图;
图3（A）至3（E）是显示实施例3中所进行的生产过程诸步骤的截面视图;
图4（A）至4（E）是显示实施例4中所进行的生产过程诸步骤的截面视图;和
图5是显示单片有源矩阵电路的一个实例的示意图。
图1是显示实施例1所进行生产过程诸步骤的截面视图。首先，用溅射法在衬底（Corning 7059）10上形成由氧化硅制成的厚度为2000
Figure 941027252_IMG4
的基底膜11。然后用等离子CVD法淀积内在（Ⅰ-型）非晶硅膜12，其厚度为500至1500
Figure 941027252_IMG5
，例如为1500
Figure 941027252_IMG6
。用离子植入法以11×1013至5×1014cm-2，例如为5×1013cm-2的剂量将镍离子植入非晶硅膜。结果，存在于非晶硅膜（图1（A））镍离子浓度约为5×1018cm-3。
接着，为使硅膜结晶化，将其置于氮气气氛中进行550℃下4小时的热处理工序。然后给硅膜绘制图形，以形成硅岛区13。用溅射法淀积1000
Figure 941027252_IMG7
厚的氧化硅膜14，作为栅绝缘膜。在此溅射过程中，用氧化硅作为靶，衬底温度为200至400℃，例如为250℃。该溅射工序在氧及氩气气氛中进行，而氩对氧之比为0至0.5。例如0.1或更小。
此后，用减压CVD法淀积硅膜（包含0.1至2%的磷）达3000至8000
Figure 941027252_IMG8
厚度，例如为6000
Figure 941027252_IMG9
。最好连续进行形成氧化硅和硅膜的步骤。然后给硅膜绘制图形，以形成栅极15（图1（B））。
然后，用等离子掺杂法利用栅极作为掩膜将杂质（磷）植入硅区。在此工序中，三氢化磷（pH3）用作掺杂气体，加速电压为60至90kv，例如为80kv，剂量为1×1015至8×1015cm-2，例如为2×1015cm-2。因此，形成N-型杂质区16a和16b（图1（C））。
接着，杂质区上的氧化硅膜14被刻蚀掉，以露出杂质区16。用溅射法在图1（D）所示的整个区域上均匀地形成厚度为5至200
Figure 941027252_IMG10
（例如20
Figure 941027252_IMG11
）的镍硅化物膜（分子式为Ni Six，其中0.4≤X≤2.5，例如X＝2.0）17。当该膜以大约20
Figure 941027252_IMG12
的减小了的厚度形成时，它不是连续的而是呈现聚集的粒子团外貌。然而在此实施例中（图1（D））这些都不会产生任何问题。
此后，在氮气气氛下，进行480℃下（它比上述结晶工序的温度低70℃）4小时的热处理工序从而激活杂质。在此热处理过程中，首先，镍从覆盖杂质区的硅化镍膜扩散至N型杂质区16a和16b。所以，热处理使再结晶易于进行。这样便激活了杂质区16a和16b。
然后，用等离子CVD法形成作为绝缘层的6000A厚的硅氧化膜18并在该绝缘层中形成接触孔。在TFT的源和漏区通过诸如氮化钛和铝之类的多层金属材料膜形成电极/导线19a和19b。最后，在1    atm的氢气气氛中，在350℃下进行热处理30分钟，作为上述过程的结果，完成了一个薄膜晶体管的制造（图1（E））。
用二次离子质谱仪（SIMS）测量如此生产出的TFT的活性区（栅极以下区域）中镍的浓度，其结果约为1×1018至5×1018cm-3。在杂质区16中镍的浓度大约为1×1019至5×1019cm-3。
实施例2
图2是显示本实施例所进行的生产过程步骤的截面视图。首先用溅射法在衬底（Corning 7059）上形成2000
Figure 941027252_IMG13
厚，由硅氧化物制成的底膜21。然后，借助等离子CVD法淀积厚度为500至1500
Figure 941027252_IMG14
，例如为1500
Figure 941027252_IMG15
的内在（Ⅰ-型）非晶硅膜22和用溅射法淀积厚度为200
Figure 941027252_IMG16
的硅氧化膜23。用离子植入法以5×1013cm-2的剂量将镍离子植入非晶硅膜（图2（A））。
接着，对非晶硅膜进行550℃的氮气气氛下的热处理工序达8小时，以晶化该非晶硅膜。此后，将该硅膜制成图形，以形成硅岛区24。
利用四乙氧基甲硅烷（Si（OC2H5）4，TEOS）和氧气作为原料，用等离子CVD法形成厚度为1000
Figure 941027252_IMG17
的硅氧化物膜25，作为结晶硅TFT的栅绝缘膜。除这些原料气体外，还使用了三氯化乙烯（C2HCl3）作为原料之一。在生成该膜以前，令400SCCM的氧气通过一个小室，在衬底温度为300℃，总压力为5Pa，RF功率为150W的条件下产生等离子。这种状态维持10分钟。此后将300SCCM的氧气，15SCCM的TEOS和2SCCM的三氯化乙烯导入小室以进行硅氧化膜的膜成形。在膜成形过程中，衬底温度，RF功率和总压力分别为300℃，75W和5Pa。在膜成形完成之后，将100Torr氢气导入小室，并在350℃下进行氢气热处理达35分钟。
此后，借助溅射法淀积厚度为3000至8000
Figure 941027252_IMG18
，例如为6000 的钽膜。可使用钛，钨，钼或硅来替代钽。不过，要求该材料要有足够的耐热性，以使其能经得住后来的激活工序。最好连续进行形成硅氧化物25和钽膜的步骤。然后对钽膜绘制图形，以形成TFT的栅极26。钽导线的表面经阳极氧化，以在其上形成氧化层27。该阳极氧化是在1至5%乙烯乙二醇的洒石酸溶液中进行的。所得到的氧化层具有2000
Figure 941027252_IMG20
的厚度（图2（B））。
然后借助等离子掺杂法，利用栅极作为掩模将杂质（磷）植入硅区。在此工序中，将磷化氢（pH3）用作掺杂气体，加速极电压为80kv，剂量为2×1015cm-2。结果形成N型杂质区28a和28b。由于阳极氧化之故，栅极26被移离杂质区28（图2（C））。
借助离子植入法，利用栅极作为掩模，以1×1014至2×1015cm-2的剂量（例如为5×1014cm-2将镍离子植入硅区，结果，N型杂质区28a和28b的浓度大约为5×1019cm-3（图2（D））。
此后，在氮气气氛下进行4小时的450℃热处理，从而激活杂质。在此热处理工序中，由于镍离子被植入N型杂质区28a和28b，故热处理导致再结晶易于进行。这样，杂质区28a和28b被激活。
然后，用等离子CVD法将TEOS用作原料形成厚度为2000 的硅氧化膜29作为一层绝缘膜，并在绝缘层中形成接触孔。借助多层诸如钛氮化物和铝之类的金属材料形成源和漏电极/导线30a和30b。上述过程的结果，即完成了一个半导体电路（图2（E））。
就这样产生的薄膜晶体管而言，当其栅极电压为10V时，场效应渗透率（field effect mobility）是70至100cm2/vs，阈值电压为2.5至4.0V漏电流为10-13A或小于栅极加有-20V时的漏电流。
实施例3
本实施例中，用基本相同的方法将结晶硅TFT和非晶硅TFT形成在同一衬底上。图3为本实施例所进行生产过程诸步骤的截面视图。首先，用溅射法在衬底（Corning 7059）110上形成厚度为2000
Figure 941027252_IMG22
，由硅氧化物制成的底膜111。然后，用等离子CVD法淀积500至1500
Figure 941027252_IMG23
厚的内在（Ⅰ型）非晶硅膜112（例如1500
Figure 941027252_IMG24
厚），接着用溅射法有选择地形成厚度为5至200
Figure 941027252_IMG25
，例如为20
Figure 941027252_IMG26
的硅化镍膜（分子式为Ni Six，其中0.4≤X≤2.5，例如X＝2.0）113（图3（A））。
然后，在一种氢气还原气氛下（氢的部分压力最好从0.1至1atm），进行4小时的500℃热处理工序，以实现晶化。结果使硅化镍膜113下面的非晶硅膜结晶，以变成结晶硅膜112a。相反，不存在硅化镍膜的硅膜区仍然如112b所示处于非晶态（图3（B））。
用光刻法对这样获得的硅膜绘制图形，以形成硅岛区114a（结晶硅区）和另一硅岛区114b（非晶硅区）。用溅射法淀积1，000 厚的氧化硅膜115，作为栅绝缘膜。在此溅射过程中，将氧化硅用作靶，衬底温度为200至400℃，例如为350℃。该溅射工序在氧与氩的气氛中进行，其中氩对氧之比为0至0.5，例如0.1或更小。此后，用减压CVD法淀积硅膜（含0.1至2%的磷），其厚度为6000至8000
Figure 941027252_IMG28
，例如为6000
Figure 941027252_IMG29
。最好连续地进行形成氧化硅及硅膜的步骤。然后对硅膜绘制图形，以形成栅极116a，116b和116c（图3（C））。
然后，用等离子掺杂法并利用栅极作为掩模将杂质（磷和硼）植入硅区。在此工序中磷化氢（pH3）和乙硼烷（B2H6）用作掺杂气体，加速电压在前者情况下为60至90kv，例如为80kv，和在后者情况下为40至80kv，例如为65kv，剂量为1×1015至8×1015cm-2，例如对磷为2×1015cm-2，对硼为5×1015cm-2。结果，形成P型杂质区117a和N型杂质区117b和117c。在此情况下，在掺入磷杂质后，以1×1013至1×1015cm-2，例如为5×1014cm-2的剂量掺入镍杂质（图3（D））。
然后，在氢还原气氛下，进行4小时的500℃热处理工序，以激活杂质。在此过程中，由于镍离子在予先已结晶的区域114a中扩散，该热处理使再结晶易于进行。同样在硅岛区114b中，由于掺磷区117C中还掺有镍，故即使在这种程度热处理下也足以进行晶化。这样，杂质区117a至117c被激活。非晶硅TFT的活性区由于其内不存在镍而未被晶化，然后，用等离子CVD法形成作为一层绝缘膜，厚度为6000 的氧化硅膜118，并在该绝缘膜中形成接触孔。借助诸如氮化钛和铝之类的多层金属材料膜形成用于结晶硅TFT的电极/导线119a，119b和119c和用于非晶硅TFT的电极/导线119d和119e。最后，在1atm氢气气氛下，进行30分钟350℃下的热处理工序。作为上述工艺的结果，完成一半导体电路（图3（E））。
由二次离子质谱仪（SIMS）测量如此得到的TFT各活性区中的镍浓度，结果同时观测到在结晶硅TFT中，镍离子为1×1018至5×1018cm-3而在非晶硅TFT中镍的浓度小于测量极限值（1×1016cm-3）。
实施例4
在本实施例中，将结晶硅TFT用于外部驱动电路而将非晶硅TFT用于象素电路。图4是显示该实施例所进行的生产过程诸步骤的截面视图。用溅射法在衬底（Corning 7059）120上形成钽膜，其厚度为500至2000
Figure 941027252_IMG31
，例如为1000
Figure 941027252_IMG32
。对钽膜绘制图形以形成非晶硅TFT的栅极接线121。用阳极氧化法在钽接线的外围形以形成厚度为1000至3000
Figure 941027252_IMG33
，例如为1500
Figure 941027252_IMG34
的阳极氧化膜122。
接着，用溅射形成厚度为2000
Figure 941027252_IMG35
的氧化硅膜123。氧化硅膜123既充当非晶硅TFT的栅绝缘膜也充当结晶硅TFT的基底绝缘膜。此后，用等离子CVD法淀积非晶硅膜124，厚度为200至1500
Figure 941027252_IMG36
，例如为500
Figure 941027252_IMG37
。当用光刻抗蚀剂125掩蔽非晶硅膜124的同时，借助离子植入法将镍离子植入硅膜，以产生包含1×1018至2×1019cm-3，例如为5×1018cm-3的镍区126。
区域126的深度为200至500 。以最佳方法选择加速能量以实现该深度。防止镍离子被植入结晶硅TFT中充当活性区的区域内。沟道长度为20um或更小，最好为10μm或更小。当沟道长度大于该值时，就不可能使整个活性区均结晶（图4（A））。
然后在0.1至1atm之氢气气氛下，进行8小时550℃的热处理工序，以实现晶化。作为该晶化工序的结果，植入镍的区，插入在两个镍植入区之间的区域以及它们的外围（这些区由图4（B）中的124a标明）也被晶化。550℃下8小时的热处理结果，横向产生大约10um的结晶体。相反，还未植入镍的区域124b仍处于非晶态（图4（B））。
对硅膜绘制图形，以形成硅岛区127a（结晶硅区）和另一硅岛区127b（非晶硅区）。用等离子CVD法将四乙氧基甲硅烷（TEDS，Si（OC2H5）4）和氧气用作原料形成1000 厚的氧化硅膜128，作为结晶硅TFT的栅绝缘膜。除这些原料气体以外，还有三氯化乙烯（C2HCl3）也用作原料之一。在形成膜以前，令400SCCM的氧气通过一小室，则在衬底温度为300℃，总压力5Pa和RF功率为150W的条件下产生等离子。该状态被维持10分钟。此后，将300SCCM的氧，15SCCM的TEOS和2SCCM的三氯化乙烯导入小室以进行氧化硅膜的膜成形。在该膜成形过程中，衬底温度，RF功率及总压力分别为300℃，75W和5Pa。完成该膜成形之后，将100Torr的氢气导入小室，并在350℃下进行35分钟的氢热处理。
此后，用溅射法淀积厚度为6000至8000 ，例如6000
Figure 941027252_IMG41
的铝膜（含2%的硅）。也可用钽，钛，钨或钼替代铝。最好连续地进行形成氧化硅128和铝膜的步骤。然后，对铝膜绘制图形以形成TFT的栅极129a和129b。对铝线条表面进行阳极氧化，以在其上形成氧化层。阳极氧化是在1至5%乙烯乙二醇的洒石酸溶液中进行的。所得到的氧化层厚度为2000A。通过从衬底背面进行曝光，以相对于栅极121自对准方式，在非晶硅TFT的氧化硅上形成光刻抗蚀掩模130（图4（C））
然后借助等离子掺杂法并利用栅极作掩模，将一种杂质（磷）注入硅区。在此工序中，将磷化氢（pH3）用作掺杂气体，加速电压为60至90kv，例如为80kv，剂量为1×1015至8×1015cm-2，例如为2×1015cm-2。结果，形成N型杂质区131a和131c。此后，左侧的结晶硅TFT（N-沟道TFT）与非晶硅TFT（矩阵区）由一种光致抗蚀剂掩蔽而杂质（硼）被植入右侧的结晶硅TFT（P-沟道TFT）的硅区。在此工序中，将乙硼烷用作掺杂气体，加速电压为50至80kv，例如为65kv。剂量为1×1015至8×1015cm-2，例如为5×1015cm-2，它大于事先已植入的磷的剂量。这样便形成了P型杂质区131b。
此后，借助激光器热处理法激活这些杂质。至于激光器采用了KrF准分子激光器（波长为248nm，脉宽为20ns）。另一方面还可用诸如XeF准分子激光器（波长为353nm），Xecl准分子激光器（波长为308nm），或ArF准分子激光器（波长为193nm）等其他激光器。激光器的能量密度为200至400mJ/cm2，例如为250mJ/cm2每点被辐照激光器的2至10射程例如为2射程。在激光器辐照期间，衬底可被加热至大约200至450℃。在加热衬底的情况下，应注意最佳能量密度随温度不同而变。非晶硅TFT的活性区未被晶化因其上有掩膜130。因此，结晶硅TFT的杂质区131a和131b以及非晶硅TFT的杂质区被激活（图4（D））。
然后，借助等离子CVD法，采用TEOS作为原料形成厚度为2000
Figure 941027252_IMG42
的氧化硅膜132作为一层绝缘膜。用溅射法淀积厚度为500至1000
Figure 941027252_IMG43
，例如为800
Figure 941027252_IMG44
的铟锡氧化（ITO）膜。对ITO膜进行刻蚀，以形成象素电极133在绝缘膜层132中形成接触孔。用诸如氮化钛力铝之类的多层金属材料膜形成结晶硅TFT（外部驱动电路）用的源和漏极/导线134a，134b和134c以及用于非晶硅TFT（象素电路）的电极/导线134d和134e。上述过程结果便产生一个半导体电路（图4（E））。
在这样生产的半导体电路中，结晶硅TFT（外部驱动电路）的诸性能均不次于通过传统的600℃热处理结晶工艺的诸步骤所产生的TFT的诸性能。例如，已证实由该实施例产生的移位寄存器在漏极电压15v下工作在11MHz而在漏极电压17v条件下，操作在16MHz，再者就可靠性试验而言，也未发现该移位寄存器与现有技术的移位寄存器之间有任何差别。
就非晶硅TFT（象素电路）的性能而言，漏电流为10-13A或更小。
根据本发明，由于非晶硅的结晶以及硅中掺的杂质的激活均是在诸如400至550℃的低温下进行并历时诸如4小时之类的短周期，故可改善生产率。当用传统方法运用600℃或更高温的工艺时，会导致玻璃衬底收缩而引起成品损坏的问题。根据本发明可容易地解决这类问题。
这意味着可在同一时间处理一块大尺寸的衬底。换言之，当处理大尺寸衬底时，可从一块衬底中切出许多半导体电路（矩阵电路等）从而可大大降低单位成本。当将这一特性应用于液晶显示器时，便有可能促进批量生产率并改善诸特性。正如以上所述，本发明在工业上是极为有利的。
再者，根据本发明可在同一衬底上借助同一工艺过程形成以高速操作的结晶硅TFT和以低的漏电流为特征的非晶硅TFT。当将该特性应用于液晶显示器时，增强批量生产率和改善产品性能是可能的。

Claims (23)

1、一种晶体管，包括：
包括置于一衬底上的结晶硅膜的活性区；和设置在邻近所述活性区的杂质区，
其中所述活性区包含1×1017cm-3或更高浓度的催化元素，以促进结晶作用，所述催化元素在所述杂质区的浓度高于所述催化元素在所述活性区的浓度。
2、权利要求1的晶体管，其特征在于所述催化元素至少为镍，铁钴和铂之一种。
3、如权利要求1的晶体管，其特征在于所述催化元素的浓度是由二次离子质谱仪所测得的值。
4、一种半导体电路，包括：
含有设置在一衬底上的结晶硅膜的活性区的晶体管;和
包含非晶硅膜制成的另一活性区的另一晶体管，
其中所述结晶硅膜和所述非晶硅膜设置在同一层，所述结晶硅膜中的催化元素浓度为1017cm-3或更高，而所述非晶硅膜中的催化元素浓度低于1017cm-3。
5、权利要求4的电路，其特征在于所述结晶硅膜中的所述催化元素的浓度为5×1018cm-3或更高。
6、如权利要求4的电路，其特征在于所述非晶硅膜中的所述催化元素的浓度为1×1016cm-3或更低。
7、如权利要求4的电路，其特征在于所述催化元素是镍，铁，钴和铂中至少之一。
8、如权利要求4的电路，其特征在于所述另一晶体管被用作活性矩阵区中的一个晶体管。
9、如权利要求4的电路，其特征在于所述晶体管，包括由结晶硅膜制成的活性区，并用于一移位寄存电路中。
10、如权利要求4的电路，其特征在于：在所述结晶硅膜中的催化元素的所述浓度和在所述非晶硅膜中的催化元素的所述浓度均由二次离子质谱仪测得的最小值来确定。
11、一种半导体电路，包括
包含由设在衬底上结晶硅膜制成的活性区的晶体管，和
包含由非晶硅膜制成的另一活性区的另一晶体管，
其中所述结晶硅膜和所述非晶硅膜设置在同一层，包含于所述结晶硅膜中的催化元素浓度是10倍于或更高倍于包含在所述非晶硅膜中的催化元素的浓度。
12、制造晶体管的一种方法，包括：
在衬底上形成一种催化元素浓度低于1×10cm的非晶硅膜;
将用于促进结晶作用的催化元素添加到所述非晶硅膜;
在所述硅膜上形成栅极;
用所述栅极作为掩模将杂质掺入到所述硅膜;
形成包含与所述硅膜接触的一种催化元素的物质;和
对所述硅进行热处理，以激活所述引入的杂质.
13、如权利要求12的方法，其特征在于所述添加步骤是通过形成一种包含与所述非晶硅膜接触的催化元素的物质，此后再用加热将所述催化元素同所述非晶硅膜相组合而完成。
14、如权利要求13的方法，其特征在于所述物质是所述催化元素与硅的一种化合物。
15、一种制造晶体管的方法，包括以下步骤;
在一衬底上形成具有低于1×1017cm-3的一种催化元素浓度的非晶硅膜;
将用于促进结晶作用的催化元素添加到所述非晶硅膜;
在所述硅膜上形成栅极;
利用所述栅极作为掩模将所掺杂质和催化元素导入所述硅膜的一部分，以获得所述导入的催化元素浓度为1×10cm或在所述部分中较高的浓度;以及
对所述硅膜进行热处理，以激活所述导入的杂质。
16、一种制造晶体管的方法，包括以下步骤;
在一衬底上形成具有低于1×1017cm-3或较高的催化元素浓度的非晶硅膜;
对所述非晶硅膜进行最大温度T1的热处理;
在所述硅膜上形成栅极;
利用所述栅极作为掩模将所掺杂质和催化元素导入所述硅膜;以及
对所述硅膜进行最大温度T2（＜T1）下的热处理，以激活所述导入的杂质。
17、如权利要求16的方法，其特征在于T1-T2＞50℃。
18、一种制造半导体电路的方法，包括以下步骤：
形成包含与非晶硅膜接触的催化元素的物质;
通过加热对所述非晶硅膜进行热处理，以使与所述催化元素接触中的所述非晶硅膜的一部分晶化;
将该硅膜该画成至少一个非晶硅区和至少一个结晶硅区;和
在所述非晶硅区和所述结晶硅区上各形成至少一个栅极。
19、如权利要求18的方法，其特征在于所述热处理步骤是在580℃或更低温度下完成的。
20、一种制造半导体电路的方法，包括以下步骤：
将一种催化元素引入一非晶硅膜;
通过加热对所述非晶硅膜进行热处理，以使所述催化元素被引入的那部分所述非晶硅膜被结晶;
将该硅膜刻画成至少一个非晶硅区和至少一个结晶硅区;和
在所述非晶硅区和所述结晶硅区上各形成至少一个栅极。
21、如权利要求20的方法，其特征在于所述热处理步骤是在580℃或更低温度下实现的。
22、一种晶体管，包括
一个半导体活性区;和
设置在所述半导体活性区邻近的半导体杂质区，
其中所述半导体杂质区中的催化元素浓度高于所述半导体活性区中催化元素的浓度。
23、一种半导体电路，包括
含有由结晶硅膜构成的活性区的晶体管;及
包含由非晶硅膜构成的另一活性区的另一晶体管，
其中所述结晶硅膜和所述非晶硅膜设置在同一层上，而且所述结晶硅膜中的催化元素浓度高于所述非晶硅膜中催化元素的浓度。
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US5595923A (en) 1997-01-21
KR100197780B1 (ko) 1999-06-15
CN1215223A (zh) 1999-04-28
TW278219B (zh) 1996-06-11
US5569936A (en) 1996-10-29
CN1221018C (zh) 2005-09-28

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