CN1112086C - 中心密集的周边球栅阵列电路封装和封装方法 - Google Patents

中心密集的周边球栅阵列电路封装和封装方法 Download PDF

Info

Publication number
CN1112086C
CN1112086C CN97190260A CN97190260A CN1112086C CN 1112086 C CN1112086 C CN 1112086C CN 97190260 A CN97190260 A CN 97190260A CN 97190260 A CN97190260 A CN 97190260A CN 1112086 C CN1112086 C CN 1112086C
Authority
CN
China
Prior art keywords
contact pad
encapsulation
substrate
integrated circuit
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN97190260A
Other languages
English (en)
Other versions
CN1185892A (zh
Inventor
M·巴尔罗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24497765&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CN1112086(C) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1185892A publication Critical patent/CN1185892A/zh
Application granted granted Critical
Publication of CN1112086C publication Critical patent/CN1112086C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/06—Arrangements of circuit components or wiring on supporting structure on insulating boards, e.g. wiring harnesses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
    • Y10T29/49222—Contact or terminal manufacturing by assembling plural parts forming array of contacts or terminals

Abstract

一种球栅阵列(BGA)集成电路封装(10)，该封装具有封装衬底(12)下表面(16)上的焊料球外二维阵列和焊料球中心二维阵列(34)。一般对焊料球进行回流焊将封装安装印制电路板上。将通过封装内的内部布线电连接到焊料球的集成电路(18)安装到衬底的相对表面。焊料球的外阵列位于集成电路的分布线的外部，以减小由集成电路和衬底之间热膨胀系数的差异造成的焊接应力。中心焊料球一般直接接封装的地和电源焊盘，以提供从集成电路到印刷电路板的直接热和电通道。

Description

中心密集的周边球栅阵列电路封装和封装方法
发明领域
本发明涉及集成电路封装以及封装的方法。
背景技术
集成电路一般安装到焊接在印制电路板的封装上。这种集成电路的封装类型之一是球栅阵列(“BGA”)封装。BGA封装具有位于封装衬底的下外表面上的多个焊料球。对焊料球进行回流焊使封装衬底贴附在印制电路板上。集成电路安装到封装衬底的上表面，并通过封装内的内部路径电连接焊料球。
图1显示的是现有技术BGA封装2的焊料球阵列。在封装的下表面焊料球4排列成二维图形。集成电路6位于封装2相对侧的中央。封装2一般由热膨胀系数与集成电路不同的材料组成。现已发现集成电路与封装之间不同的热膨胀会引入与温度有关的应力，该应力会使对应电路管芯的外边缘的区域内的焊料连接失败。
图2显示的是具有焊料球4的外二维阵列的现有技术BGA封装2。焊料球4位于远离集成电路6下封装区的区域。将焊料球4远离集成电路6放置可以减小由于封装与集成电路之间不同的热膨胀引起的焊料接点上的热应力。虽然有效地减少了焊料失败，但外阵列图形限制了封装的输入/输出(I/O)。此外，集成电路产生热量，传导穿过焊料球并进入印制电路板。将焊料球放置在封装的外围增加了穿过封装衬底的热路径。路径更长增加了封装的热阻和集成电路的结温度。希望能提供一种BGA封装，和现有技术BGA的封装相比，具有更长的产品寿命、更低的热阻和更多的I/O。
发明内容
本发明为球栅阵列(“BGA”)集成电路封装，具有焊料球的外二维排列和位于封装衬底的下表面上的焊料球的中央二维排列。一般对焊料球进行回流将封装安装到印制电路板上。通过封装内的内部路径电连接到焊料球上的集成电路安装在衬底的相对表面上。焊料球的外阵列位于集成电路的尺寸剖面(dimensional profile)外，可以减小集成电路与衬底之间不同的热膨胀引起的焊料应力。中心的焊料球一般直接接封装的地和电源焊盘，提供从集成电路到印制电路板的直接的热和电通路。
阅读下面详细的说明书和附图后，对本领域的普通技术人员来说，本发明的目的和优点将变得很明显。
附图说明
图1为现有技术球栅阵列集成电路封装的底视图；
图2为现有技术球栅阵列集成电路封装的底视图；
图3为本发明球栅阵列封装的侧面剖视图；
图4为图3所示的封装的底视图；
图5为另一球栅阵列封装的底视图。
具体实施方式
下面参照附图特别是参考数字介绍本发明，图3和4显示的是本发明的球栅阵列(“BGA”)集成电路封装10。封装10包括具有上表面14和相对的下表面16的衬底12。集成电路16安装在衬底12的上表面14上。集成电路18一般为微处理器。虽然介绍的是微处理器，但应该明白封装10也包含其它电器件。
衬底12的上表面14具有多个键合焊盘20和接地总线22。衬底12也有密集地位于集成电路18和接地焊盘22周围的单独的电源总线23。集成电路18通过焊线24连接到键合焊盘20和总线22和23。集成电路16一般用密封剂包封。虽然未显示和介绍焊线，集成电路18可以通过位于封装中电路管芯下表面的焊料球安装并连接到衬底，这种工艺通常称做“C4”或“倒装芯片”封装。
衬底12的下表面16具有多个接触焊盘28。接触焊盘28通过衬底12内的通孔30和内部路径32连接焊盘20。衬底可以由采用本领域公知的常规印制电路板或防火(co-fired)陶瓷的封装工艺制成。
用公知的球栅阵列工艺将多个焊料球34贴附在接触焊盘28上。一般对焊料球34进行回流焊使封装10贴附在印制电路板(未显示)。
接触焊盘28排列成外部的二维阵列36和中心的二维阵列38。每个阵列包含每个由许多介质间隔40隔离的多个接触焊盘28。外阵列36通过介质区42与中心阵列38隔离。外阵列36最好位于集成电路18的外尺寸剖面的外部。在这种方式中，外阵列36的焊料接点不受集成电路18的热膨胀系数与衬底12的热膨胀系数之间的差异引起的应力的影响。中心阵列38位于靠近集成电路16的区域内，在该区域内产生的热膨胀没有电路管芯的外边缘产生的多。因此，由于热膨胀的差异产生的焊料应力在中心阵列38的区域内最小。阵列分开提供了焊料接点上应力最小的图形。
外阵列36一般连接到集成电路16的信号线。中心阵列38最好连接到衬底12的接地总线20和电源总线23。将总线22和23连接到中心接触焊盘的通孔30提供了穿过衬底的直接的热路径。直接的热路径降低了封装10的热阻和集成电路18的结温度。此外，短的电通路降低了自感并减少了集成电路18的开关噪音。
在优选实施例中，在27×27毫米(mm)宽的衬底12上的封装10包括292个接触焊盘28，或35×35毫米(mm)宽的衬底12上包括352个接触焊盘28。接触焊盘28之间的介质间隔40一般约为1.27mm。封装10一般高度约为2.5mm。
将焊料球34贴附在接触焊盘28来装配封装10。集成电路18安装并连接到衬底12上。然后用密封剂26包封集成电路18。一般装运到最终用户的BGA封装10是通过回流焊料球34安装到印制电路板上的。
图5显示了封装10’的另一实施例，该封装10’在衬底12’的外阵列36’内有五或六列接触焊盘28。附加的焊盘28增加了封装10的输入/输出(I/O)。外阵列36’最好在集成电路18的外尺寸剖面的外部，以使焊料接点上的应力最小化。封装10’在27×27mm的衬底10上提供有324个接触焊盘28。封装60的更长的列提供了约35×35mm封装的I/O，在27×27mm的封装的印记内。
虽然在附图中介绍并显示了某些可仿效的实施例，但应该明白这些实施例仅为说明性的而不是限制性的，由于本领域的普通技术人员可以做出不同的其它修改，所以本发明并不受所显示的特定的结构和设置限制。

Claims (16)

1.一种球栅阵列封装，包括：
具有上表面和相对的下表面的衬底，所述下表面具有每个接触焊盘之间间隔第一距离的接触焊盘外阵列，和每个接触焊盘之间间隔第二距离的接触焊盘中心阵列，所述接触焊盘的中心阵列与所述接触焊盘的外阵列间隔大于第一距离和第二距离的第三距离；
贴附在所述衬底的所述接触焊盘上的多个焊料球。
2.根据权利要求1的封装，其中所述衬底的所述上表面具有多个键合焊盘。
3.根据权利要求2的封装，其中所述衬底的所述上表面具有通过延伸穿过所述衬底的多个通孔连接到所述中心阵列的接触焊盘的接地总线。
4.根据权利要求3的封装，其中所述接触焊盘的外阵列至少具有五列接触焊盘。
5.根据权利要求4的封装，其中所述衬底的所述上表面具有通过延伸穿过所述衬底的多个通孔连接到所述中心阵列的接触焊盘的电源总线。
6.根据权利要求5的封装，其中所述接触焊盘的中心阵列设置为4×4矩阵。
7.一种球栅阵列封装，包括：
具有上表面和相对的下表面的衬底，所述上表面具有多个键合焊盘，所述下表面具有每个接触焊盘之间间隔第一距离的接触焊盘外阵列，和每个接触焊盘之间间隔第二距离的接触焊盘中心阵列，所述接触焊盘的中心阵列与所述接触焊盘的外阵列间隔大于第一距离和第二距离的第三距离；
贴附在所述衬底的所述接触焊盘上的多个焊料球，
安装到所述衬底并连接到所述键合焊盘的集成电路。
8.根据权利要求7的封装，其中所述衬底的所述上表面具有通过延伸穿过所述衬底的多个通孔连接到所述中心阵列的接触焊盘的接地总线。
9.根据权利要求8的封装，其中所述接触焊盘的外阵列具有至少五列接触焊盘。
10.根据权利要求9的封装，其中所述衬底的所述上表面具有通过延伸穿过所述衬底的多个通孔连接到所述中心阵列的接触焊盘的电源总线。
11.根据权利要求10的封装，其中所述接触焊盘的中心阵列设置为4×4矩阵。
12.根据权利要求11的封装，其中所述集成电路用密封剂包封。
13.根据权利要求7的封装，其中所述接触焊盘的外阵列位于所述集成电路的外分布线的外部。
14.一种装配球栅阵列封装方法，包括以下步骤：
a)提供具有上表面和相对的下表面的衬底，所述下表面具有每个接触焊盘之间间隔第一距离的接触焊盘外阵列，和每个接触焊盘之间间隔第二距离的接触焊盘中心阵列，所述接触焊盘的中心阵列与所述接触焊盘的外阵列间隔大于第一距离和第二距离的第三距离；
b)将集成电路安装到所述衬底的上表面上。
c)将多个焊料球贴附在所述接触焊盘上。
15.根据权利要求14的方法，还包括密封所述集成电路的步骤。
16.根据权利要求15的方法，还包括用多个焊线将所述集成电路连接到所述衬底的步骤。
CN97190260A 1996-03-28 1997-03-07 中心密集的周边球栅阵列电路封装和封装方法 Expired - Lifetime CN1112086C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62335596A 1996-03-28 1996-03-28
US08/623,355 1996-03-28

Publications (2)

Publication Number Publication Date
CN1185892A CN1185892A (zh) 1998-06-24
CN1112086C true CN1112086C (zh) 2003-06-18

Family

ID=24497765

Family Applications (1)

Application Number Title Priority Date Filing Date
CN97190260A Expired - Lifetime CN1112086C (zh) 1996-03-28 1997-03-07 中心密集的周边球栅阵列电路封装和封装方法

Country Status (10)

Country Link
US (5) US5894410A (zh)
EP (2) EP1482773A1 (zh)
JP (4) JPH11506274A (zh)
KR (1) KR100288065B1 (zh)
CN (1) CN1112086C (zh)
AU (1) AU2070197A (zh)
DE (1) DE69732166T2 (zh)
IL (1) IL122107A (zh)
MY (1) MY123146A (zh)
WO (1) WO1997036466A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI558279B (zh) * 2012-03-07 2016-11-11 新光電氣工業股份有限公司 配線基板及配線基板的製造方法

Families Citing this family (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY123146A (en) * 1996-03-28 2006-05-31 Intel Corp Perimeter matrix ball grid array circuit package with a populated center
JPH1065039A (ja) * 1996-08-13 1998-03-06 Sony Corp 半導体装置
US6037044A (en) * 1998-01-08 2000-03-14 International Business Machines Corporation Direct deposit thin film single/multi chip module
JPH11284006A (ja) * 1998-03-31 1999-10-15 Fujitsu Ltd 半導体装置
US6060777A (en) 1998-07-21 2000-05-09 Intel Corporation Underside heat slug for ball grid array packages
JP3602968B2 (ja) * 1998-08-18 2004-12-15 沖電気工業株式会社 半導体装置およびその基板接続構造
US6655022B1 (en) 1998-09-24 2003-12-02 Intel Corporation Implementing micro BGA assembly techniques for small die
US6034425A (en) * 1999-03-17 2000-03-07 Chipmos Technologies Inc. Flat multiple-chip module micro ball grid array packaging
US6489557B2 (en) 1999-08-30 2002-12-03 Intel Corporation Implementing micro BGA™ assembly techniques for small die
US6566741B2 (en) 1999-10-21 2003-05-20 Intel Corporation Grounding of package substrates
US6392887B1 (en) 1999-12-14 2002-05-21 Intel Corporation PLGA-BGA socket using elastomer connectors
JP2001223324A (ja) * 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
US6448639B1 (en) 2000-09-18 2002-09-10 Advanced Semiconductor Engineering, Inc. Substrate having specific pad distribution
TW462121B (en) * 2000-09-19 2001-11-01 Siliconware Precision Industries Co Ltd Heat sink type ball grid array package
US6403896B1 (en) 2000-09-27 2002-06-11 Advanced Semiconductor Engineering, Inc. Substrate having specific pad distribution
US6816385B1 (en) 2000-11-16 2004-11-09 International Business Machines Corporation Compliant laminate connector
AU2002217987A1 (en) 2000-12-01 2002-06-11 Broadcom Corporation Thermally and electrically enhanced ball grid array packaging
US7161239B2 (en) * 2000-12-22 2007-01-09 Broadcom Corporation Ball grid array package enhanced with a thermal and electrical connector
US6906414B2 (en) * 2000-12-22 2005-06-14 Broadcom Corporation Ball grid array package with patterned stiffener layer
US20020079572A1 (en) 2000-12-22 2002-06-27 Khan Reza-Ur Rahman Enhanced die-up ball grid array and method for making the same
US7132744B2 (en) 2000-12-22 2006-11-07 Broadcom Corporation Enhanced die-up ball grid array packages and method for making the same
US6853070B2 (en) * 2001-02-15 2005-02-08 Broadcom Corporation Die-down ball grid array package with die-attached heat spreader and method for making the same
US7259448B2 (en) 2001-05-07 2007-08-21 Broadcom Corporation Die-up ball grid array package with a heat spreader and method for making the same
TW531873B (en) * 2001-06-12 2003-05-11 Advanced Interconnect Tech Ltd Barrier cap for under bump metal
US6617680B2 (en) * 2001-08-22 2003-09-09 Siliconware Precision Industries Co., Ltd. Chip carrier, semiconductor package and fabricating method thereof
GB2377080B (en) * 2001-09-11 2003-05-07 Sendo Int Ltd Integrated circuit package and printed circuit board arrangement
TW510034B (en) * 2001-11-15 2002-11-11 Siliconware Precision Industries Co Ltd Ball grid array semiconductor package
US6879039B2 (en) * 2001-12-18 2005-04-12 Broadcom Corporation Ball grid array package substrates and method of making the same
US7550845B2 (en) 2002-02-01 2009-06-23 Broadcom Corporation Ball grid array package with separated stiffener layer
US7245500B2 (en) * 2002-02-01 2007-07-17 Broadcom Corporation Ball grid array package with stepped stiffener layer
US6825108B2 (en) * 2002-02-01 2004-11-30 Broadcom Corporation Ball grid array package fabrication with IC die support structures
US6861750B2 (en) 2002-02-01 2005-03-01 Broadcom Corporation Ball grid array package with multiple interposers
US6876553B2 (en) * 2002-03-21 2005-04-05 Broadcom Corporation Enhanced die-up ball grid array package with two substrates
US7196415B2 (en) * 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
US20040104463A1 (en) * 2002-09-27 2004-06-03 Gorrell Robin E. Crack resistant interconnect module
SE0300686D0 (sv) * 2003-03-13 2003-03-13 Infineon Technologies Wireless A method and device for protection of a component or module
TWI225694B (en) * 2003-04-23 2004-12-21 Advanced Semiconductor Eng Flip chip package
JP4975437B2 (ja) * 2003-10-10 2012-07-11 台湾積體電路製造股▲ふん▼有限公司 電子装置
US7489517B2 (en) * 2004-04-05 2009-02-10 Thomas Joel Massingill Die down semiconductor package
US7482686B2 (en) * 2004-06-21 2009-01-27 Braodcom Corporation Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same
US7411281B2 (en) * 2004-06-21 2008-08-12 Broadcom Corporation Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same
US7432586B2 (en) 2004-06-21 2008-10-07 Broadcom Corporation Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages
US7235880B2 (en) * 2004-09-01 2007-06-26 Intel Corporation IC package with power and signal lines on opposing sides
US7786591B2 (en) 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
CN100424842C (zh) * 2004-11-17 2008-10-08 日本特殊陶业株式会社 布线基板的制造方法
US7269017B2 (en) * 2004-11-19 2007-09-11 Delphi Technologies, Inc. Thermal management of surface-mount circuit devices on laminate ceramic substrate
KR100574996B1 (ko) * 2004-11-25 2006-05-02 삼성전자주식회사 반도체 패키지 및 이를 이용한 메모리 카드, 및 이의제조에 이용되는 몰드
JP4738996B2 (ja) * 2004-12-13 2011-08-03 キヤノン株式会社 半導体装置
JP4592413B2 (ja) * 2004-12-27 2010-12-01 三洋電機株式会社 回路装置
US7772705B2 (en) * 2005-02-02 2010-08-10 Toshiba America Electronic Components, Inc. Low thermal resistance package
US7402757B1 (en) 2005-05-19 2008-07-22 Sun Microsystems, Inc. Method, system, and apparatus for reducing transition capacitance
KR100698526B1 (ko) * 2005-07-20 2007-03-22 삼성전자주식회사 방열층을 갖는 배선기판 및 그를 이용한 반도체 패키지
US8183680B2 (en) * 2006-05-16 2012-05-22 Broadcom Corporation No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement
DE102006032073B4 (de) 2006-07-11 2016-07-07 Intel Deutschland Gmbh Elektrisch leitfähiger Verbund aus einem Bauelement und einer Trägerplatte
US7804167B2 (en) * 2006-12-01 2010-09-28 Lsi Logic Corporation Wire bond integrated circuit package for high speed I/O
US20080246139A1 (en) * 2007-04-03 2008-10-09 Don Craven Polar hybrid grid array package
CN101304016B (zh) * 2007-05-10 2011-05-11 中芯国际集成电路制造(上海)有限公司 通用测试封装结构及方法
US7619901B2 (en) * 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
CN101425099B (zh) * 2007-10-31 2010-09-22 英业达股份有限公司 元件布设检测方法及系统
TWI343780B (en) * 2007-12-14 2011-06-11 Delta Electronics Inc Power module package structure
US7750460B2 (en) * 2008-02-21 2010-07-06 Lsi Corporation Ball grid array package layout supporting many voltage splits and flexible split locations
US7923847B2 (en) * 2008-08-27 2011-04-12 Fairchild Semiconductor Corporation Semiconductor system-in-a-package containing micro-layered lead frame
CN101944492A (zh) 2008-10-20 2011-01-12 联合科技公司 板上收缩封装
US8169065B2 (en) * 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US8901747B2 (en) 2010-07-29 2014-12-02 Mosys, Inc. Semiconductor chip layout
US8411444B2 (en) 2010-09-15 2013-04-02 International Business Machines Corporation Thermal interface material application for integrated circuit cooling
JP5819598B2 (ja) * 2010-11-16 2015-11-24 Ｎｅｃネットワークプロダクツ株式会社 インターポーザー
US8669780B2 (en) 2011-10-31 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional integrated circuit connection structure and method
JP2013149797A (ja) * 2012-01-19 2013-08-01 Denso Corp 半導体パッケージ
CN103378029B (zh) * 2012-04-18 2016-04-20 中芯国际集成电路制造(上海)有限公司 硅通孔结构
US9093429B2 (en) * 2012-06-27 2015-07-28 Freescale Semiconductor, Inc. Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices
US8890302B2 (en) * 2012-06-29 2014-11-18 Intel Corporation Hybrid package transmission line circuits
US8766453B2 (en) 2012-10-25 2014-07-01 Freescale Semiconductor, Inc. Packaged integrated circuit having large solder pads and method for forming
US9368422B2 (en) * 2012-12-20 2016-06-14 Nvidia Corporation Absorbing excess under-fill flow with a solder trench
KR102079795B1 (ko) * 2013-07-19 2020-02-21 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 화상형성장치 및 칩
KR102117477B1 (ko) * 2015-04-23 2020-06-01 삼성전기주식회사 반도체 패키지 및 반도체 패키지의 제조방법
US20170179069A1 (en) * 2015-12-18 2017-06-22 Jonathon R. Carstens Ball grid array solder attachment
CN105636344A (zh) * 2015-12-31 2016-06-01 福建睿能科技股份有限公司 一种电子设备
JP2018056228A (ja) * 2016-09-27 2018-04-05 ルネサスエレクトロニクス株式会社 半導体装置、システムインパッケージ、及び車載用システムインパッケージ
CN110740569A (zh) * 2018-07-19 2020-01-31 鸿富锦精密工业(武汉)有限公司 印刷电路板
CN112640110A (zh) * 2018-08-31 2021-04-09 富士胶片株式会社 摄像单元及摄像装置
CN110707055B (zh) * 2019-09-11 2021-12-28 长江存储科技有限责任公司 芯片、电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355283A (en) * 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
US5450283A (en) * 1992-11-03 1995-09-12 Motorola, Inc. Thermally enhanced semiconductor device having exposed backside and method for making the same
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4688170A (en) 1983-09-22 1987-08-18 Tau Systems Corporation Communications network for communicating with computers provided with disparate protocols
US4887148A (en) 1988-07-15 1989-12-12 Advanced Micro Devices, Inc. Pin grid array package structure
JP2670563B2 (ja) 1988-10-12 1997-10-29 富士通株式会社 半導体装置の製造方法
JPH0363944U (zh) * 1989-10-26 1991-06-21
DE69129619T2 (de) * 1990-09-19 1999-02-25 Fujitsu Ltd Halbleitervorrichtung mit einer vielzahl von anschlussstiften
US5216278A (en) * 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
JP2872825B2 (ja) * 1991-05-13 1999-03-24 三菱電機株式会社 半導体装置用パッケージ
JPH04350959A (ja) * 1991-05-28 1992-12-04 Hitachi Ltd 半導体装置およびその実装体
JPH05160292A (ja) * 1991-06-06 1993-06-25 Toshiba Corp 多層パッケージ
JPH0555418A (ja) * 1991-08-23 1993-03-05 Toshiba Corp 半導体集積回路装置
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
US5495397A (en) * 1993-04-27 1996-02-27 International Business Machines Corporation Three dimensional package and architecture for high performance computer
JP2708696B2 (ja) * 1993-06-30 1998-02-04 株式会社ピーエフユー 半導体素子実装コネクタ
US5545923A (en) * 1993-10-22 1996-08-13 Lsi Logic Corporation Semiconductor device assembly with minimized bond finger connections
US5367435A (en) 1993-11-16 1994-11-22 International Business Machines Corporation Electronic package structure and method of making same
US5642261A (en) 1993-12-20 1997-06-24 Sgs-Thomson Microelectronics, Inc. Ball-grid-array integrated circuit package with solder-connected thermal conductor
US5477082A (en) * 1994-01-11 1995-12-19 Exponential Technology, Inc. Bi-planar multi-chip module
JPH07212013A (ja) * 1994-01-25 1995-08-11 Pack Vision:Kk ボール・グリッド・アレイ及びボール・グリッド・アレイ用のプリント回路基板の製造方法
US5506756A (en) 1994-01-25 1996-04-09 Intel Corporation Tape BGA package die-up/die down
JP2647001B2 (ja) * 1994-05-31 1997-08-27 日本電気株式会社 テープキャリアならびに半導体デバイスの実装構造およびその製造方法
JPH0851171A (ja) * 1994-05-31 1996-02-20 Sumitomo Kinzoku Ceramics:Kk 半導体セラミックパッケージ
US5543661A (en) * 1994-05-31 1996-08-06 Sumitomo Metal Ceramics Inc. Semiconductor ceramic package with terminal vias
US5741729A (en) * 1994-07-11 1998-04-21 Sun Microsystems, Inc. Ball grid array package for an integrated circuit
JPH0855931A (ja) 1994-08-10 1996-02-27 Dainippon Printing Co Ltd 面実装半導体搭載装置及び面実装半導体搭載装置用基板
JP3104537B2 (ja) * 1994-08-30 2000-10-30 松下電器産業株式会社 電子部品
TW353223B (en) 1995-10-10 1999-02-21 Acc Microelectronics Corp Semiconductor board providing high signal pin utilization
US5703402A (en) * 1995-11-13 1997-12-30 Acc Microelectronics Corporation Output mapping of die pad bonds in a ball grid array
JP3294490B2 (ja) * 1995-11-29 2002-06-24 株式会社日立製作所 Ｂｇａ型半導体装置
US5650660A (en) 1995-12-20 1997-07-22 Intel Corp Circuit pattern for a ball grid array integrated circuit package
MY123146A (en) * 1996-03-28 2006-05-31 Intel Corp Perimeter matrix ball grid array circuit package with a populated center

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5450283A (en) * 1992-11-03 1995-09-12 Motorola, Inc. Thermally enhanced semiconductor device having exposed backside and method for making the same
US5355283A (en) * 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI558279B (zh) * 2012-03-07 2016-11-11 新光電氣工業股份有限公司 配線基板及配線基板的製造方法

Also Published As

Publication number Publication date
KR100288065B1 (ko) 2001-05-02
KR19990014736A (ko) 1999-02-25
US7543377B2 (en) 2009-06-09
DE69732166D1 (de) 2005-02-10
EP0835600A4 (en) 2000-01-12
JP2008252152A (ja) 2008-10-16
US6747362B2 (en) 2004-06-08
DE69732166T2 (de) 2005-12-15
EP0835600B1 (en) 2005-01-05
US20060180345A1 (en) 2006-08-17
JP5247281B2 (ja) 2013-07-24
US5894410A (en) 1999-04-13
EP0835600A1 (en) 1998-04-15
AU2070197A (en) 1997-10-17
CN1185892A (zh) 1998-06-24
WO1997036466A1 (en) 1997-10-02
MY123146A (en) 2006-05-31
US20020057558A1 (en) 2002-05-16
IL122107A (en) 2003-10-31
JPH11506274A (ja) 1999-06-02
US20040262038A1 (en) 2004-12-30
JP2011160009A (ja) 2011-08-18
JP2014187410A (ja) 2014-10-02
EP1482773A1 (en) 2004-12-01
US20080064138A1 (en) 2008-03-13
IL122107A0 (en) 1998-04-05

Similar Documents

Publication Publication Date Title
CN1112086C (zh) 中心密集的周边球栅阵列电路封装和封装方法
US7396702B2 (en) Module assembly and method for stacked BGA packages
US4677526A (en) Plastic pin grid array chip carrier
US6468834B1 (en) Method of fabricating a BGA package using PCB and tape in a die-up configuration
US5844782A (en) Printed wiring board and electronic device using same
CN1139116C (zh) 集成电路封装及具有该封装的计算机系统
US7061092B2 (en) High-density modularity for ICS
KR100192760B1 (ko) 메탈 캐리어 프레임을 이용한 bag반도체 패키지의 제조방법 및 그반도체 패키지
US5637916A (en) Carrier based IC packaging arrangement
US5886876A (en) Surface-mounted semiconductor package and its manufacturing method
US5663593A (en) Ball grid array package with lead frame
US5362656A (en) Method of making an electronic assembly having a flexible circuit wrapped around a substrate
US6507107B2 (en) Semiconductor/printed circuit board assembly
US6448639B1 (en) Substrate having specific pad distribution
US5663594A (en) Ball grid array type of semiconductor device
EP1333491A2 (en) Ball grid array package enhanced with a thermal and electrical connector
US20020096767A1 (en) Cavity down ball grid array package with EMI shielding and reduced thermal resistance
JPH0642525B2 (ja) 多チツプチツプキヤリア及び製造方法
US5455387A (en) Semiconductor package with chip redistribution interposer
US20040094833A1 (en) Semiconductor package
US5973931A (en) Printed wiring board and electronic device using same
US5910686A (en) Cavity down HBGA package structure
US6403896B1 (en) Substrate having specific pad distribution
US6747352B1 (en) Integrated circuit having multiple power/ground connections to a single external terminal
KR100367729B1 (ko) 멀티플 라인 그리드 어레이 패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20030618