CN1123067C - 具有与布线基板电连接的半导体芯片的半导体器件 - Google Patents

具有与布线基板电连接的半导体芯片的半导体器件 Download PDF

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CN1123067C
CN1123067C CN96194131A CN96194131A CN1123067C CN 1123067 C CN1123067 C CN 1123067C CN 96194131 A CN96194131 A CN 96194131A CN 96194131 A CN96194131 A CN 96194131A CN 1123067 C CN1123067 C CN 1123067C
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semiconductor chip
electrode
circuit board
spacer element
projection electrode
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CN1185859A (zh
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塚越功
松冈宽
广泽幸寿
三上喜胜
堂河内久司
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Showa Denko Materials Co ltd
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Hitachi Chemical Co Ltd
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Abstract

一种半导体器件，包括半导体芯片、布线基板和最好含介于其中的导电颗粒的粘结剂，多个间隔元件存在于粘结层上或下，所述间隔元件的高度几乎与包围的突出电极相同，顶视时，其形状至少为圆形和多边形中的一种，并位于由连接电极包围的区域中，该半导体器件的挠性强度高、可靠性高，可以用于各种信息卡等。

Description

具有与布线基板电连接的半导体芯片的半导体器件
技术领域
本发明涉及一种包括与布线基板电连接的半导体芯片的半导体器件，及用于其中的布线基板。
背景技术
关于电连接半导体芯片和布线基板的方法，已知有通过加压或热压用粘结剂把半导体芯片粘结于具有电极的布线基板上，布线基板的电极对应于半导体芯片的电极。在这种情况下，所用粘结剂有直接与两电极接触实现导电的绝缘粘结剂，或其中具有导电颗粒的各向异性导电粘结剂，在导电颗粒设于两电极之间时，通过加压这种导电粘结剂在厚度方向上表现出导电性。
近来，人们正试图减小半导体芯片的厚度，例如，减小IC卡中电子部件、液晶显示器件等的厚度，以便能改进轻便性和操作的难易度。例如，关于薄电子部件，预付卡的厚度约0.25mm，条形码标签的厚度约0.15mm等等。这些电子部件现在变得越来越薄。这样，目前所用半导体芯片的厚度为例如从约0.6mm减小到约0.3mm，或在极端的情况下，使其厚度为约0.02mm。
在这种情况下，对半导体芯片和布线基板间的粘结剂加压或用加压并加热，芯片会发生翘曲，因而会显著降低连接的可靠性。而且，在连接时，由于半导体芯片的中央部分容易变形，所以残余应力导致粘附强度下降，挠性强度不够，结果导致薄电子部件很难承载。
另一方面，半导体芯片厚度减小后，其挠性增加，会使芯片在装载期间更易变形。但，经常发生例如由于与基板的连接部分发生的气泡导致的粘结失效，会发生上述的挠性强度降低和可靠性变差。另外，在粘结剂的流动性不充分时，两电极间的接触或电极与导电颗粒间的接触变得不充分，因而会降低连接电阻。
发明内容
本发明的目的是提供一种包括与布线基板电连接的半导体芯片的半导体器件，甚至在半导体芯片很薄时也能够保持极佳的连接可靠性，并提供一种用于其中的布线基板，从而克服现有技术中的缺陷。
本发明提供一种半导体器件，该半导体器件包括：厚为0.3mm或更小的半导体芯片，其周边部分上有若干电极；布线基板，其上的电极对应于半导体芯片的电极；及半导体芯片和布线基板之间的粘结层，半导体芯片和布线基板中至少一个的电极突出于绝缘平面，平视时，有多个高度几乎与突出电极相同的间隔元件，即，当半导体芯片或布线基板其中之一具有突出电极时，间隔元件存在于半导体芯片或布线基板其中之一上，且间隔元件的高度与突出电极的高度相同；当半导体芯片和布线基板上都具有突出电极时，在半导体芯片和布线基板上都有间隔元件，且其上间隔元件的高度与其上突出电极的高度相同，且至少为圆形和多边形之一，它们存在于连接后由半导体芯片周边部分的电极包围的区域中。
本发明还提供一种布线基板，包括：基片；形成于基片上的多个电极，这些电极对应于将与基片连接的半导体芯片周边部分上的突出电极；及形成于由基片上的突出电极包围的区域中的多个间隔元件，平视时它们的高度几乎与半导体芯片上的突出电极相同，其形状至少为圆形和多边形之一。
本发明还提供一种电连接结构，通过在包括基片的布线基板上设置各向异性导电粘结剂、在基片上形成电路、放置半导体芯片、然后加压来获得，所述粘结剂含有导电颗粒，所述电路包括伸出预定高度的突出电极和位于突出电极所环绕的区域之中、高度与突出电极相同、从顶视角度看形状至少为圆形和多边形之一的多个间隔元件，所述半导体芯片包括支撑物、在支撑物上形成的电极和在电极上形成的绝缘层，从而在对应于布线基板上突出电极的预定位置露出电极，并使芯片上露出的电极与布线基板上的突出电极相对。
本发明还提供一种电连接结构，通过在包括基片的布线基板上设置各向异性导电粘结剂、在基片上形成电路、提供半导体芯片、放置半导体芯片、然后加压来获得，所述粘结剂含有导电颗粒，所述电路包括电极和位于电极所环绕的区域之中、从顶视角度看形状至少为圆形和多边形之一的多个间隔元件，所述半导体芯片包括支撑物、在支撑物上形成的突出电极和绝缘层，从而在对应于布线基板上电极的预定位置露出从绝缘层伸出预定高度的突出电极，并在放置半导体芯片时使半导体芯片的突出电极与布线基板上的电极相对，其中间隔元件的高度与突出电极的预定高度相同。
附图说明
图1是根据本发明一个实施例的半导体器件的剖面示意图；
图2是根据本发明另一个实施例的半导体器件的剖面示意图；
图3是根据本发明再一个实施例的半导体器件的剖面示意图；
图4是根据本发明又一个实施例的半导体器件的剖面示意图；
图5A至5D是贴装于布线基板上的虚设电极的平面图；
图6A至6F是根据本发明实施例的虚设电极的平面图；
图7A至7E是根据本发明实施例的虚设电极的剖面平面图；
图8A至8E是可应用于本发明的各种粘结层的剖面图；
图9是根据本发明的半导体器件的另一个实施例的剖面示意图。
具体实施方式
根据本发明，提供一种半导体器件，该半导体器件包括：厚为0.3mm或更薄的半导体芯片，芯片周边部分上有多个电极；具有多个电极的布线基板，这些电极与半导体芯片的电极相对应；及半导体芯片和布线基板之间的粘结层；半导体芯片和布线基板中至少一个的所述电极从绝缘平面向外延伸，构成突出电极，顶视时，多个间隔元件的高度几乎与突出电极的高度相同，且其形状至少为圆形和多边形之一，这些间隔元件位于接连后由半导体芯片周边部分上的电极包围的区域中。
关于本发明间隔元件的形状，术语“圆形”是指圆形、椭圆形、卵形、半圆形、弧形等，术语“多边形”是指三角形、方形、矩形、菱形、五角形、六角形、线形、L形、U形、V形等等。
在优选实施例中，间隔元件的形状至少为选自三角形、L形、半圆形和U形中的一种或这些形状的两种以上。最好是间隔元件设置成使每个角和/或封闭边指向连接区的中心。连接区是指通过粘结剂连接的区域，该区由基片上的电极包围着，这些电极相应于半导体芯片上周边部分的电极。关于设置问题，最好是间隔元件设置成从连接区中心到其周边的辐射状，或设置成沿连接区中心对称。另外，间隔元件可以有不平整的连接表面，并可以是导电的或绝缘的。
此外，连接用粘结剂最好含导电颗粒，这种颗粒在被压时仅在厚度方向产生导电性，如果必要，还可以含有粒径比导电颗粒小的的硬颗粒，所述硬颗粒充当填充元件。
根据本发明，还提供一种用于如半导体器件的电连接结构中的布线基板，包括：基片；形成于基片上的多个电极，这些电极相应于将要与基片连接的半导体芯片的周边部分上的电极；及形成于由基片上电极包围的区域的多个间隔元件，顶视时，这些间隔元件的形状至少为圆形和多边形中的一种。最好是所述形状的每个角或封闭边指向连接区的中心。间隔元件(或虚设电极)的高度应几乎与基片上的任何突出电极或将要连接的半导体芯片上的突出电极的高度相同。
下面参照附图说明本发明。
图1至4是一种半导体器件的剖面示意图，所述半导体器件包括与布线基板电连接的半导体芯片，该图用于说明本发明的某些实施例。图1至4中，数字1表示半导体芯片，数字2表示芯片上的电极，数字3表示绝缘层，数字4表示基片，数字5表示基片上的导电电路，数字6或6’表示间隔元件(有时称作虚设电极)，数字7和7’分别表示基片和芯片上的突出电极，数字11表示粘结剂，数字12表示导电颗粒。
图1和2中，无突点的芯片用作半导体芯片1。图3和4中，有突点(即，突出电极7’)的芯片用作半导体芯片1。
如上所述，一种趋势是减小半导体芯片1的厚度。本发明在使半导体芯片很薄以便增加芯片挠性方面特别有效。
关于半导体芯片1，一般使用硅或砷化镓制作的芯片。也可以用其它合适电子部件制作的其它类似芯片。
关于电极2，可以用通常用作半导体芯片1上布线的铝(Al)。也可以用由Cu、Au、焊料、Cr、Ni、Ag、Mo、Ta、Sn、氧化铟(ITO)、导电墨等制作的布线电极。这些金属可以单用或作为混合用或以层叠结构使用。
在电极2表面上，形成有氮化硅、氧化硅、聚酰亚胺等制作的绝缘层3，一般厚度为5μm或更薄，最好为约1-2μm，以便在某些部分暴露出电极2。在电极2的暴露部分上，通常称作突点的突出电极7可以形成为象图3和4所示的那样。通常，突出电极7从绝缘层3表面起的高度为0.1-5μm。本发明中，没有突点的芯片称作无突点芯片(见图1和2)。常用的无突点芯片在半导体芯片1的周边部分上有暴露的电极，原因是容易进行连接基片的输入和输出。半导体芯片通常为方形或矩形，术语“周边部分”是指靠近芯片的至少两边的部分(例如，参见以下的5C和5D)。
突出电极7或7’可以形成于基片4的边上(见图2)、半导体芯片1的边上(见图3和4)或芯片1和基片4的两边(附图中未示出)，或突出电极可以形成于基片上作为电路(例如图1中的电路5)、端子等。在突出电极形成于基片4上时最好为10-35μm。由于制造工艺中可以省却某些步骤，所以最好用无突点芯片。
关于基片4，可以使用由例如聚酰亚胺或聚酯等制成的塑料薄膜、玻璃与环氧树脂的混合物、硅半导体等、如玻璃或陶瓷等无机材料。如果有必要，基片4上有用粘结剂粘结的电路5(附图中未示出)。
电路5的材料没有特别限制，可以是所述电极2的那些材料。电路的厚度通常为约0.1-50μm。一般说来，在厚度约为4或5μm或更厚时，通常用铜箔或导电膏形成电路。
当在基片4或绝缘层3上不存在不平整时，或即使存在4或5μm或更小的不平整时，电极等一般可以利用附加方法或薄膜法得到。所用材料和其厚度的选择要考虑其特性，如电导率、耐腐蚀性，及如生产成本等经济问题。
多个间隔元件6形成于将与基片4连接的一侧上(图1和2)或形成于半导体芯片1上(图4)或形成于这两者上(图3)。间隔元件形成于至少由半导体芯片1的周边部分上的电极2包围的区域中，并且与突出的电极(图2-4的突出电极7和7’，图1的电路5)几乎等高。“几乎等高”是指一般为±20％，最好不超过突出电极高度的±10％。虚设电极6的高度较好限定为在突出电极的高度基础上为±5μm，更好为±2μm。特别优选的是间隔元件6形成于基片4的面上(图1和图2)，因为间隔元件可以与电路5和/或突出电极7同时通过电路处理的镀敷或腐蚀由金属形成。
下面参照图5A-5D和6A-6F详细说明多个间隔元件6的设置情况，这些图是半导体芯片连接之前的平面图。顶视时，间隔元件6分开设置于连接区中，其形状至少为多种圆形和多边形中一种。可以用线形(5A和5B)、L形或U形(5A和5B)、三角形(图5D)、或圆形(图5C)形成多边形。这些形状可以任意地组合或混合。
重要的是，考虑连接时粘结剂的流动性，以便从组件的中心向周边部分排除气泡。这样，这种设置的多个间隔元件对于尽可能地减少内部形成气泡很重要。换句话说，重要的是把间隔元件设置成使粘结剂在粘结过程中可以从半导体芯片1的中心顺畅地流到边缘部分。
顶视时，使粘结剂顺畅地流动的间隔元件设置(或突出于周边电极内连接平面8)的优选实施例为三角形(图6A)、L形(图6B)、半圆形(弧形)(图6C)和U形(图6D)。这些不同形状的元件可以单独使用，也可以两个或更多组合使用。而且，这些形状设置成各角(图6A、6B、6C、6E、6F)和/或封闭的边(图6D)指向连接区的中心。此外，这些形状最好是可以多种形式分开形成，以便更进一步加速粘结剂在分开部分中的流动。而且，基于如上所述的理由，间隔元件6可以设置成如图6A、6B、6E和6F那样的从连接区中心向周边的辐射状。更好是给拐角部分提供合适的粗糙度，以便使粘结剂顺畅地流动，如图6A所示。
在这些情况下，由于粘结剂从连接区的中心顺畅地流向周边部分，所以可以完全地去除连接部分的气泡，结果可以使电极之间或电极与导电颗粒之间的接触充分，从而提供低连接电阻。
在连接时，对粘结剂加压并加热，此时上电极和下电极间的那部分粘结剂流到相邻电极之间的间隙中，填充间隙并使过多的部分流到芯片连接区之外。所以，本发明中重要的是提供填充此间隙同时流出的步骤。间隔元件应设置成不会妨碍这种外流。
在间隔元件6的截面在如图7所示的电极连接平面处为不平整表面时，容易将导电颗粒和硬颗粒保持于元件上。在不平整表面制作成有例如槽(图7A)或波状条纹(图7B和7C)时，粘结剂可以更顺畅地流动，以便以最佳方式实现本发明。这种情况下，空心部分的深度较好为0.5μm或更大，更好为1μm-20μm。空心部分的深度还可以用平均粗糙度来表示(JISB0601，10个点的平均粗糙度)。而且，梯形(图7D)和倒梯形(图7E)截面也可以改善粘结剂的流动性。
在上述说明中，间隔元件6形成于半导体芯片周边电极内的区域中，但也可以在周边电极的区域中与周边电极混合形成间隔元件。而且，最好是间隔元件6设置成关于连接区的中心左右对称和/或上下对称(图6A-6F)，从而使粘结剂的流动均匀，从而几乎完全地去除气泡，和/或保持弯曲强度从而得到良好的连接。
关于间隔元件6的材料，不仅可以采用导电材料例如电极2和电路5的材料，还可以采用绝缘材料，例如绝缘层3的材料。这意味着，在连接时，对间隔元件6加压或加压同时加热，足以实现不发生较大变形的连接。所以，足以使间隔元件具有等同于或高于上述基片和半导体芯片的耐热性。
本发明中间隔元件6的高度几乎与突出电极7(包括图1中的电路5)相同。对此说明需进行一步的解释。在图1这种情况下，其中电路5充当突出电极，间隔元件6的高度几乎与电路5相同。但图2-4的情况下，间隔元件6的高度变为电路5和突出电极7(图2)的总高度或从绝缘层3的平面突出电极7和7’的高度(图3和4)。
关于粘结剂11，可以采用绝缘粘结剂(图8A)，直接粘结基片和芯片，使两电极彼此接触，在半导体芯片和布线基板间产生导电性。还可以采用各向异性导电粘结剂(图8B)，这种粘结剂中含有导电颗粒12，其量足以在加压时仅在厚度方向产生导电性，即通过导电颗粒(适于图1-4)在两电极间产生导电性。粘结剂可以为液态或膜状。最好是使用厚度恒定的连续膜状粘结剂。
在使用如图8B所示的含导电颗粒的各向异性导电粘结剂时，不必形成突出电极7(见图1)。由于省却了一步或几步工艺步骤，从节约资源和成本的观点出发这是有利和优选的。足以通过加压仅在厚度方向产生导电性的导电颗粒的含量约为按体积计绝缘粘结剂的0.1-15％，最好为0.3-10％。导电颗粒的含量取决于连接间距或连接电极的面积。
还可以采用层叠粘结膜，包括一层或多层绝缘粘结剂11，和各向同性导电粘结剂(图8C和8D)。这种层叠粘结膜对高间距连接特别有用，这是由于可以区分绝缘作用和导电作用得到连接的缘故。图9示出了一种通过把图8C所示粘结剂(两层粘结剂)加到图1所示结构得到的半导体芯片和基片的连接结构。如图9所示，基片4上的粘结剂主要由不含导电颗粒的粘结剂层(11’)构成，导致绝缘性的改善。
关于绝缘粘结剂11，可以采用电子部件常用的粘结剂，包括热塑性树脂粘结剂。其中，最好使用反应性粘结剂。反应性粘结剂广泛地包括可以热或光固化的材料。其中，由于连接后固化树脂材料的耐热性和抗湿性很好，所以最好采用这种固化树脂材料。特别是，由于环氧树脂粘结剂的固化时间短，连接作用很好且从分子结构的角度看粘结性很好，所以最好采用这种环氧树脂粘结剂。
环氧树脂包括例如高分子重环氧树脂、固态环氧树脂、液态环氧脂、用尿脘改性的环氧树脂、聚酯、丙烯酸橡胶、丙烯腈橡胶(NBR)、尼龙等。无需说，环氧树脂粘结剂可以含一种或多种固化剂、催化剂、偶合剂、填充剂等。
关于环氧树脂的固化剂，最好用潜固化剂，以便保持连接材料存储稳定性。术语“潜固化剂”是指固化剂可以与如环氧树脂等反应树脂一起稳定地存储于30℃或更低的温度下2个月以上，但是加热时可以快速实现反应树脂的固化。
关于导电颗粒12，可以用如Au、Ag、Pt、Ni、Cu、W、Sb、Sn、焊料等金属颗粒或碳颗粒。这些导电颗粒可以用作芯材料。另外，可以用这种导电材料涂敷如玻璃、陶瓷、如塑料的高聚物等非导电芯材料，在非导电颗粒表面上形成导电层。还可以使用绝缘层涂敷导电颗粒12得到的绝缘膜涂敷颗粒，或同时使用导电颗粒和绝缘颗粒。
颗粒尺寸的上限定为至少在微细电极上设置一个颗粒，最好在微细电极上设置5个或更多颗粒。具体地，颗粒尺寸的上限较好为50μm或更小，最好为20μm或更小。另一方面，颗粒尺寸的下限的确定要考虑大于绝缘层3的厚度的较大尺寸，和对电极不平整表面的适应性。为了防止颗粒的过分凝聚，该下限较好为0.5μm或更大，最好为1μm或更大。
导电颗粒12中，那些由如焊料等热熔金属制作的颗粒，和那些通过在如塑料等高聚物的芯颗粒模式上形成导电层得到的颗粒最好，因为这些导电颗粒具有良好的抗热压变形性或抗压变形性，在层叠时增大了和电路的接触面积，提高了可靠性。在用含高聚物作芯材料的导电颗粒时，由于与用焊料颗粒相反，没有明显的熔点，在接触温度可以广泛地控制软化状态，所以对获得能克服电极厚度或平整度偏差的连接材料特别有利。
而且，在用如Ni和W等硬颗粒或在表面有大量突起的颗粒作导电颗粒时，由于导电颗粒刺穿电极和布线图形，所以有利于得到低连接电阻，以提高可靠性，即使存在着氧化膜或污染层。
导电颗粒12最好是具有近乎均匀的颗粒尺寸，颗粒尺寸分布很小。在颗粒尺寸分布很小时，在加压连接时，电极间几乎保留了所有颗粒，流出量很小。考虑到连接表面的不平整性，颗粒尺寸的分布宽度最好为最大颗粒尺寸的1/2或更小。例如，在通过高聚物制作的芯材料上涂敷导电层得到易变形颗粒的情况下，可以获得在中心值附近±0.2μm或更小的高精度的颗粒尺寸。这种颗粒特别有用。在硬金属颗粒情况下，由于这些颗粒能刺穿电极，所以颗粒尺寸分布范围可以较宽，例如为最大颗粒尺寸的1/2或更小。
还可以使用导电颗粒和其它硬颗粒的混合物(图8E)。关于硬颗粒，可以采用其它较小导电颗粒和作填充剂的绝缘颗粒。这种颗粒混合物具有调节将要连接的电极间的间隙的作用。而且，由于在加压并加热时粘结剂的厚度可以控制在预定值，所以可以得到满意的粘结强度稳定性。在调节间隙的情况下，最好使硬颗粒的尺寸小于导电颗粒尺寸，并使硬颗粒的硬度大于导电颗粒。在将绝缘颗粒用作硬颗粒时，可以改善相邻电极的绝缘特性。
关于绝缘颗粒，可以采用由例如玻璃、石英、陶瓷等无机材料制作的颗粒或由例如聚苯乙烯、环氧树脂、苯并胍胺树脂等有机材料制作的颗粒。绝缘颗粒可以采取例如球形、纤维状等。这些绝缘颗粒可以单独使用或作为混合物使用。
根据本发明，即使半导体芯片的厚度为0.3mm或更薄，由于与突出电极有几乎相同高度的间隔元件存在于由半导体芯片周边电极包围的区域中，所以即使对通过粘结剂连接的半导体芯片和布线基板加压或加压并加热，也不会发生芯片翘曲，所以可以显著提高连接的可靠性。而且，由于半导体芯片中心部分几乎不变形，所以接触后，没有残余应力，因而可以提供足以装载薄电子部件的挠性强度。
此外，由于间隔元件设置成通过从中心向端部去除气泡而使内部几乎不存在气泡的形状，所以连接部分中几乎不存在气泡，所以可以获得低连接电阻和高连接可靠性。
而且，在更优选的实施例中，布线基板上间隔元件的高度几乎与突出于布线基板上的电路电极相同时，不需要特殊处理步骤，由于在电路处理时，镀敷和腐蚀可以同时进行，所以可以降低生产成本。
通过以下的实例说明本发明。
实例1
(1)半导体芯片
关于半导体芯片，可以采用IC芯片用于测试，该芯片的尺寸为2mm×10mm，厚100μm，连接侧覆盖1.5μm厚的氮化硅，具有200个所谓的焊盘，焊盘为四边上周边部分上的100μm见方的暴露的铝电极。
(2)布线基板
在0.1mm厚的玻璃-环氧树脂基板上，设置有15μm厚的铜箔电路端子，相应于IC芯片的电极焊盘的尺寸。如图5D所示，在由电路端子包围的区域中，设置有规则的三角形间隔元件，其边长500μm，其高度与电路(突出电极)的高度几乎相同，通过腐蚀使各角集中在该区域的中心。包围区域中的间隔元件所占面积为约24％。间隔元件表面的平均粗糙度(JISB0610)为1.4μm。
(3)各向异性导电膜
混合重量比为20/80的高分子重环氧树脂(Mn＝ca25000，由双酚A衍生出的苯氧基树脂.)和含密封于微胶囊中(液态双酚F型环氧树脂包括按重量计30％的微胶囊，此微胶囊的平均直径为2μm，为由聚氨基甲酸乙酯覆盖的咪唑衍生颗粒)的潜固化剂的液态双酚A型环氧树脂(环氧树脂当量185)，得到30％的乙酸乙酯溶液。关于导电颗粒，用颗粒尺寸为8±0.2μm的聚苯乙烯粒，其上涂有Ni和Au(Ni：0.2μm厚/Au0.02μm厚)。混合导电颗粒，并将之按体积计5％分散于乙酸乙酯溶液中。利用roll water将所得悬浊液涂在隔离体(40μm厚的硅酮处理过的聚对苯二甲酸乙二醇酯膜)上，在110℃干燥20分钟，得到15μm厚的各向异性导电膜。
(4)连接
各向异性导电膜切成3mm×12mm那么大，该尺寸稍大于半导体芯片的尺寸，并粘附于布线基板上。然后，剥离隔离体，进行对准半导体芯片上的焊盘与布线基板的电路端子，然后，在170℃，20kgf/mm2的压力下加压15秒，进行连接。
(5)评估
彼此面对的电极间的电阻作为连接电阻评估，相邻两电极间的电阻作为绝缘电阻评估。
连接电阻为0.1Ω或更小，绝缘电阻为108Ω或更大。这些值在于85℃和85％RH下处理1000小时后几乎不改变。这表明具有良好的长期可靠性。
将得到的半导体器件切割并抛光。用显微镜观察看见的剖面示于图1中。半导体芯片几乎不发生翘曲，连接部分中没发现气泡。
实例2
重复实例1的工艺，只是使用250μm厚的聚对苯二甲酸乙二醇酯膜作布线基板。该基板具有15μm厚的电路、和印刷法涂敷的Ag膏于其上形成的15μm厚的间隔元件(平均粗糙度为2.3μm)。
所得连接结构与图1所示结构相同。半导体芯片不发生翘曲，发现几个气泡，但表现出的长期可靠性良好。
由于该电路由Ag膏制作，所以连接电阻为1Ω或更小，该值稍大于实例1，绝缘电阻为108Ω或更大。
比较例1和2
除不形成间隔元件外，分别重复实例1和2的工艺。
在用玻璃-环氧树脂基片(比较例1)和薄膜基片(比较例2)的情况下，连接电阻高达约100Ω。
于85℃和85％RH条件下处理1000小时后，观察到产生了开路(布线断裂)。而且，在半导体芯片中心发现空心形翘曲。
实例3和4
除用含2％体积的Ni颗粒的各向异性导电粘结膜外，分别重复实例1和2的工艺，其中Ni颗粒尺寸为3±0.1μm。
用与实例1相同的方式评估所得连接结构。在两个实例中(实例3-玻璃-环氧树脂基片，实例4-薄膜基片)，连接部分厚度恒定为近3μm，此值为Ni颗粒尺寸的值。而且，聚苯乙烯粒变形，从而增大与电极的接触面积，并与电极连接，所以提供了良好的长期可靠性。
实例5
除用边长为0.5mm、宽为0.1mm且开口向外的L形虚设电极外，重复实例1的工艺。间隔元件占据的包围区的面积为约40％。
此时，半导体芯片不发生翘曲，长期可靠性良好。由于间隔元件设置成可以从中心向边缘去除气泡，所以内部几乎不存在气泡，可以得到连接部分没有气泡的连接结构。
实例6
除在半导体芯片焊盘上形成Au突点(离氮化硅表面3μm高)外，重复实例3的工艺。
此时，得到了良好的长期可靠性。
间隔元件仅形成于布线基板一侧(在15μm厚的铜层上无电镀形成3μm厚的Ni层)，不在半导体芯片上形成，但以约3μm的厚度进行连接，此值也是Ni颗粒尺寸，并且该连接同样良好。
实例7-9和比较例3
除半导体芯片和布线基板上的间隔元件形状改变外，重复实例1的工艺。
半导体芯片的尺寸变为5mm见方、厚0.05mm(实例7)，5mm见方、厚0.1mm(实例8)，5mm见方、厚0.3mm(实例9)，5mm见方、厚0.6mm(比较实例3)。也用芯片进行测试，其中连接侧涂有1.5μm厚的氮化硅，在周边部分的四边上，形成有100个100μm见方的称为焊盘的暴露铝电极。
布线基板与实例1中所用基板相同，即，在0.1mm厚的玻璃-环氧树脂基片上，形成有15μm厚的电路端子，相应于上述IC芯片的电极焊盘。在由电路端子包围的区域中，形成有间隔元件，其高度几乎与电路端子(突出电极)相同，其形状为开口向外的L形，宽度间距为1mm(见图6B)。间隔元件占据包围区的面积为约60％。
在实例7-9中，半导体芯片不发生翘曲，长期可靠性良好。连接部分没发现气泡，可以得到良好的连接。
在用一棒作轴弯曲与半导体芯片连接的布线基板时，可以保持电连接，直到棒的半径变为10mm(实例7)，25mm(实例8)和40mm(实例9)为止。这意味着半导体芯片越薄，挠性越好。这些半导体器件特别有用。
另一方面，根据比较例3，其中用常规厚度(比实例8-9厚)的半导体芯片，由于半导体芯片缺乏挠性，所以在100mm时容易发生断开，挠性强度很差。
实例10-12
除将间隔元件的形状变为半圆形(见图6C，实例10)、U形(见图6D，实例11)、辐射状三角形(见图6E，实例12)外，重复实例7的工艺。间隔元件占据包围区的面积为约50％(实例10-12)。
初始连接电阻为0.15Ω(实例10)、0.022Ω(实例11)、0.12Ω(实例12)。在实例10-12中，半导体芯片不发生翘曲，长期可靠性良好。而且，实例10-12中，可以得到连接部分没有气泡的良好连接。
比较例4
除用在连接区中心的边长为3mm的方形作间隔元件外，重复实例7的工艺。
结果，所得连接结构的平均连接电阻为12Ω，此值大于实例7的连接电阻0.010Ω，与实例7相比变化很大。
在比较例4的情况下，由于在连接时几乎没去除粘结剂，所以在间隔元件附近发现许多气泡。而且，由于形成于连接区中心的间隔元件数量上只有一个，所以，挠性实验中其挠性连接降低到50mm。
工业应用
如上所述，根据本发明，即使半导体芯片为0.3mm或更薄，由于在由半导体芯片的电极包围的区域中存在着多个高度几乎与突出电极相同的间隔元件，并设置成可以从连接部分去除气泡的形状，所以可以得到芯片不发生翘曲的挠性连接，且连接可靠性极佳。
包括与布线基板电连接的半导体芯片的半导体器件、和连接结构或本发明的组合可以应用于各种信息卡，例如IC卡、预付卡等。

Claims (16)

1.一种半导体器件，包括：与布线基板电连接的半导体芯片，所述芯片厚为0.3mm或更薄，其周边部分上有多个电极；具有多个电极的布线基板，这些电极与半导体芯片的电极相对应；及半导体芯片和布线基板之间的粘结层；半导体芯片和布线基板中至少一个的所述电极从绝缘平面向外伸出预定高度，平视时，当半导体芯片或布线基板其中之一具有突出电极时，间隔元件存在于半导体芯片或布线基板其中之一上，且间隔元件的高度与突出电极的高度相同；当半导体芯片和布线基板上都具有突出电极时，在半导体芯片和布线基板上都有间隔元件，且其上间隔元件的高度与其上突出电极的高度相同，且其形状至少为圆形和多边形之一，这些间隔元件位于接连后由半导体芯片周边部分上的电极包围的区域中。
2.如权利要求1的器件，其特征在于，顶视时，间隔元件的形状至少为选自三角形、L形、半圆形和U形中的一种，且其每个角和/或封闭边设置成指向所述区的中心。
3.如权利要求1的器件，其特征在于，间隔元件沿所述区中心对称设置。
4.如权利要求1的器件，其特征在于，粘结层含导电颗粒，用以在加压时仅在厚度方向产生导电性。
5.如权利要求1的器件，其特征在于，间隔元件设置成从所述区中心向外的辐射状。
6.如权利要求1的器件，其特征在于，只是布线基板上有突出电极和间隔元件。
7.如权利要求1的器件，其特征在于，只是半导体芯片上有突出电极和间隔元件。
8.如权利要求1的器件，其特征在于，布线基板和半导体芯片上都有突出电极和间隔元件。
9.如权利要求1的器件，其特征在于，布线基板或半导体芯片中的一个有突出电极，而另一个有间隔元件。
10.一种布线基板，包括：基片；形成于基片上的多个电极，这些电极对应于将与基片连接的半导体芯片周边部分上的电极；及形成于由基片上的电极包围的区域中的多个间隔元件，顶视时，其形状至少为圆形和多边形之一。
11.如权利要求10的布线基板，其特征在于，间隔元件的高度与基片上的突出电极或半导体芯片上的突出电极的高度相同。
12.如权利要求10的布线基板，其特征在于，顶视时，间隔元件的形状至少为选自三角形、L形、半圆形和U形中的一种，且其每个角和/或封闭边设置成指向所述区的中心。
13.如权利要求10的布线基板，其特征在于，间隔元件沿所述区中心对称设置。
14.如权利要求10的布线基板，其特征在于，间隔元件设置成从所述区中心向外的辐射状。
15.一种电连接结构，通过在包括基片(4)的布线基板上设置各向异性导电粘结剂(11)、在基片(4)上形成电路(5)、放置半导体芯片(1)、然后加压来获得，所述粘结剂(11)含有导电颗粒(12)，所述电路(5)包括伸出预定高度的突出电极(7)和位于突出电极所环绕的区域之中、高度与突出电极(7)相同、从顶视角度看形状至少为圆形和多边形之一的多个间隔元件(6，6’)，所述半导体芯片(1)包括支撑物、在支撑物上形成的电极和在电极上形成的绝缘层(3)，从而在对应于布线基板上突出电极(7)的预定位置露出电极(2)，并使芯片(1)上露出的电极(2)与布线基板上的突出电极(7)相对。
16.一种电连接结构，通过在包括基片(4)的布线基板上设置各向异性导电粘结剂(11)、在基片(4)上形成电路(5)、提供半导体芯片(1)、放置半导体芯片(1)、然后加压来获得，所述粘结剂(11)含有导电颗粒(12)，所述电路(5)包括电极和位于电极所环绕的区域之中、从顶视角度看形状至少为圆形和多边形之一的多个间隔元件(6，6’)，所述半导体芯片(1)包括支撑物、在支撑物上形成的突出电极(7’)和绝缘层(3)，从而在对应于布线基板上电极的预定位置露出从绝缘层伸出预定高度的突出电极(7’)，并在放置半导体芯片(1)时使半导体芯片(1)的突出电极(7’)与布线基板上的电极相对，其中间隔元件(6，6’)的高度与突出电极(7’)的预定高度相同。
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WO1996037913A1 (en) 1996-11-28
EP0827632B1 (en) 2002-01-09
EP0827632A1 (en) 1998-03-11
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US5804882A (en) 1998-09-08
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