CN1145039C - 具有可去活的扫描电路的电路装置 - Google Patents

具有可去活的扫描电路的电路装置 Download PDF

Info

Publication number
CN1145039C
CN1145039C CNB998114537A CN99811453A CN1145039C CN 1145039 C CN1145039 C CN 1145039C CN B998114537 A CNB998114537 A CN B998114537A CN 99811453 A CN99811453 A CN 99811453A CN 1145039 C CN1145039 C CN 1145039C
Authority
CN
China
Prior art keywords
circuit
protecting component
data line
highway section
electricity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB998114537A
Other languages
English (en)
Other versions
CN1320214A (zh
Inventor
H������ķ�ȿ�
H·帕尔姆
M·斯默拉
S·瓦尔斯塔布
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN1320214A publication Critical patent/CN1320214A/zh
Application granted granted Critical
Publication of CN1145039C publication Critical patent/CN1145039C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536Scan chain arrangements, e.g. connections, test bus, analog signals
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31719Security aspects, e.g. preventing unauthorised access during test
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544Scanning methods, algorithms and patterns
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555Control logic

Abstract

具有若干功能块(FB1…FBn)的电路装置,其中,每个功能块均与至少一个其它功能块相连,且该连接至少有一部分分别通过一个联锁元件(SFF1…SFFm)来实现,所述联锁元件可通过激活线路(扫描允许)从正常模式切换到测试模式,并具有另一数据输入和输出端,该另一数据输入和输出端借助数据线路段(DL1…DL1)如此地相互连接,使得所述联锁元件(SFF1…SFFm)形成一种实现扫描电路的写寄存器。沿着所述的激活线路(扫描允许)和/或数据线路段(DL1…DL1)至少布置一种可电编程的保护元件(SE),该保护元件将相关的线路断开,或将其与一个确定的电位相连。

Description

具有可去活的扫描电路的电路装置
技术领域
本发明涉及一种具有若干功能块的电路装置,其中,每个功能块均与至少一个其它功能块相连,而且该连接至少有一部分通过联锁元件来实现,所述联锁元件可通过激活线路从正常模式切换到测试模式,并具有另外一个数据输入和输出端,该另外一个数据输入和输出端借助数据线路段如此地相互连接,使得所述联锁元件形成一种实现扫描电路的写寄存器。
背景技术
US 4,534,028曾公开过这种电路装置。其中讲述的、在电路装置中实现的扫描电路被用来简单地测试该电路装置的功能块,因为通过可与写寄存器互连的、在此被构造为触发器的联锁元件,可以在确定的时间点上给各个功能块加上确定的输入状态,而且存放于联锁元件内的中间结果可通过该写寄存器重新读出。在此,功能块应该是一种执行某种可测试的功能的电路单元。
某些形式的电子电路,譬如用于芯片卡的电路对电路信息及芯片内部数据(例如用于密码方法的密钥)需要有较高程度的保密性。必须防止这种与安全有关的信息遭到外来分析和干扰操作。同时,针对这些与安全有关的电路块及数据,电路设计需要有一个最低程度的透明度和访问,以便通过测试来确保足够的可靠性。为了在生产期间或之后确保较高程度的测试保护,经常在电子电路中附加地集成了一些测试元件,譬如上述的扫描电路,这些测试元件可以将功能块置成几乎所有所需的状态,以便根据其功能性对其进行检验。
在此,为测试而添加的元件通常由中央测试控制器进行激活或去活。而该测试控制器则通过特殊的测试管脚由软件或外部信号激活。两种方案都比较容易被干扰操作,由此形成了潜在的危险性。为此,迄今用于提高集成电路的可分析性的方法与目前对特殊电子构件所要求的高安全性是相互矛盾的。
我们还已知,在测试或首次投入运行之后,电路装置的特殊功能块同其余电路的分开是不可逆的。
为此,申请DE 197 11 478 A1曾讲述过,测试ROM只能通过不可逆调的多路转换器读出,由此避免在测试后对测试ROM进行访问。
DE 27 38 113 A1曾公开过利用可损坏的入口来不可逆地阻止对具有与安全性或功能有关的内容的存储器进行访问。
然而这些已知的装置有个缺点,就是所述不可逆调或可损坏的电路元件布置在容易发现的地方,而且可较容易地“修复”,由此可能实现各种分析及干扰操作。
发明内容
因此,本发明的任务在于,对文章开头所述的电路装置进行改进,使得几乎不可能借助扫描电路进行滥用的分析。
在本发明的具有若干功能块的电路装置中,每个功能块均与至少一个其它功能块相连,而且该连接至少有一部分分别通过一个联锁元件来实现,所述联锁元件可通过激活线路从正常模式切换到测试模式,并具有另一数据输入和输出端,该另一数据输入和输出端借助数据线路段如此地相互连接,使得所述联锁元件形成一种实现扫描电路的写寄存器,其特征在于:沿着所述的激活线路和/或数据线路段至少布置一种可电编程的保护元件,该保护元件将其所在的激活线路和/或数据线路段断开,或将其所在的激活线路和/或数据线路段与一个确定的电位相连。
扫描电路的联锁元件分布在整个芯片平面上。由此,激活线路和由数据线路段组成的数据线路也经过整个芯片平面。而保护元件由此是分散地分布在芯片平面上,使得防止“侵害”的安全性极高。此外,通过适当地选择工艺,可为防止保护元件的再编程实现极高的安全性。在DE 196 04 776 A1中曾给出过这种保护元件的例子。
选择不同的保护元件作为可断或可生成的线路段,也即作为“熔断器”或“反熔断器”,这样可以提高安全性,因为“入侵者”不会立即知道究竟采用了哪类元件。也可以优选地采用该两种类型。另外,还可以通过联系逻辑门来使用所述的保护元件,以便通过规定其输入端的电位来将其功能定义为断开或闭合的开关。
附图说明
下面参考附图并借助实施例来阐述本发明。其中:
图1示出了本发明的电路装置,以及
图2示出了用于保护元件的实施例。
具体实施方式
图1所示的电路装置示出了功能块FB1...FBn,它们直接或通过连接元件SFF1...SFFm彼此相连。在此,功能块同一个或多个其它的功能块相连。而且此处的连接可直接或通过连接元件来实现。所述连接元件SFF1...SFFm通常被构造为特殊的触发器-所谓的扫描触发器。
此外,连接元件SFF1...SFFm还可通过激活线路“扫描允许”从正常工作状态切换到测试工作状态,在所述正常工作状态下,连接元件负责将功能块的输出端接通到下一功能块的输入端。该连接元件为测试工作状态还设有另一输入和输出端。通过该另一输入和输出端,所述连接元件借助划线示出的数据线路段DL1...DL1被相互连接到写寄存器上。因此,在测试状态下,数据能够通过写寄存器的输入端“扫描输入”而装入到连接元件SSF1...SSFm之中,以便通过切换至正常工作状态、并借助单个的时钟脉冲给功能块FB1...FBn加上事先装在写寄存器内的数据。功能块FB1...FBn的输出数据被装载到后接在每个功能块上的连接元件之中,通过切换至测试模式,这些数据可以通过写寄存器及其输出端“扫描输出”被读出。利用这种扫描电路,每个功能块FB1...FBn都可置为任何一种状态,并单个进行测试。
在本发明的方法中,在激活线路“扫描允许”和接有连接元件SSF1...SSFm的数据线路DL1...DL1内均装设有保护元件SE。如图2所示,这些保护元件可实施为断路保护器“熔断器”,或实施为可生成的连接“反熔断器”,后者譬如可以作用为短路接地,或将线路固定地与供电电压相连,作为另外一种具有该性能的可能性,所述保护元件也可以与逻辑门联系在一起,以便联锁成固定的功能。这些保护元件SE分散地分布在整个芯片面上,在测试之后,它们可简单地断开或短路掉激活线路“扫描允许”及数据线路段D1...D1,并由此断开或短路掉所述的扫描电路。

Claims (5)

1.具有若干功能块(FB1...FBn)的电路装置,其中,每个功能块均与至少一个其它功能块相连,而且该连接至少有一部分分别通过一个联锁元件(SFF1...SFFm)来实现,所述联锁元件可通过激活线路(扫描允许)从正常模式切换到测试模式,并具有另一数据输入和输出端,该另一数据输入和输出端借助数据线路段(DL1...DL1)如此地相互连接,使得所述联锁元件(SFF1...SFFm)形成一种实现扫描电路的写寄存器,
其特征在于:
沿着所述的激活线路(扫描允许)和/或数据线路段(DL1...DL1)至少布置一种可电编程的保护元件(SE),该保护元件将其所在的激活线路和/或数据线路段断开,或将其所在的激活线路和/或数据线路段与一个确定的电位相连。
2.如权利要求1所述的电路装置,其特征在于:至少一个保护元件(SE)为电可断的线路段(熔断器),且被布置在所述保护元件所在的激活线路和/或数据线路段之中。
3.如权利要求1或2所述的电路装置,其特征在于:至少一个保护元件(SE)为电可生成的线路段(反熔断器),并被布置在所述保护元件所在的激活线路和/或数据线路段和所述的确定电位之间。
4.如权利要求1或2所述的电路装置,其特征在于:至少一个保护元件(SE)是利用一种布置在所述保护元件所在的激活线路和/或数据线路段中的逻辑门组成,且该逻辑门的第二个输入端可以借助电可断或电可生成的线路段被不可逆地置为一个确定的电位,由此禁止该逻辑门。
5.如权利要求3所述的电路装置,其特征在于:至少一个保护元件(SE)是利用一种布置在所述保护元件所在的激活线路和/或数据线路段中的逻辑门组成,且该逻辑门的第二个输入端可以借助电可断或电可生成的线路段被不可逆地置为一个确定的电位,由此禁止该逻辑门。
CNB998114537A 1998-09-28 1999-09-28 具有可去活的扫描电路的电路装置 Expired - Lifetime CN1145039C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP98118302A EP0992809A1 (de) 1998-09-28 1998-09-28 Schaltungsanordnung mit deaktivierbarem Scanpfad
EP98118302.3 1998-09-28

Publications (2)

Publication Number Publication Date
CN1320214A CN1320214A (zh) 2001-10-31
CN1145039C true CN1145039C (zh) 2004-04-07

Family

ID=8232706

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB998114537A Expired - Lifetime CN1145039C (zh) 1998-09-28 1999-09-28 具有可去活的扫描电路的电路装置

Country Status (12)

Country Link
US (1) US6601202B2 (zh)
EP (2) EP0992809A1 (zh)
JP (1) JP3605361B2 (zh)
KR (1) KR100408123B1 (zh)
CN (1) CN1145039C (zh)
AT (1) ATE234472T1 (zh)
BR (1) BR9914083A (zh)
DE (1) DE59904556D1 (zh)
ES (1) ES2195616T3 (zh)
RU (1) RU2211457C2 (zh)
UA (1) UA55561C2 (zh)
WO (1) WO2000019224A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100414314C (zh) * 2002-05-22 2008-08-27 Nxp股份有限公司 具有固定电压输出的单元的集成电路

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10056591A1 (de) * 2000-11-15 2002-05-23 Philips Corp Intellectual Pty Verfahren zum Schutz einer Schaltungsanordnung zum Verarbeiten von Daten
DE10162306A1 (de) 2001-12-19 2003-07-03 Philips Intellectual Property Verfahren und Anordnung zur Verifikation von NV-Fuses sowie ein entsprechendes Computerprogrammprodukt und ein entsprechendes computerlesbares Speichermedium
EP1439398A1 (en) * 2003-01-16 2004-07-21 STMicroelectronics Limited Scan chain arrangement
WO2005029105A1 (en) * 2003-09-19 2005-03-31 Koninklijke Philips Electronics N.V. Electronic circuit comprising a secret sub-module
US20060117122A1 (en) * 2004-11-04 2006-06-01 Intel Corporation Method and apparatus for conditionally obfuscating bus communications
KR100972540B1 (ko) * 2005-02-07 2010-07-28 쌘디스크 코포레이션 라이프 사이클 단계들을 가진 보안 메모리 카드
US8108691B2 (en) 2005-02-07 2012-01-31 Sandisk Technologies Inc. Methods used in a secure memory card with life cycle phases
US8321686B2 (en) 2005-02-07 2012-11-27 Sandisk Technologies Inc. Secure memory card with life cycle phases
US8423788B2 (en) 2005-02-07 2013-04-16 Sandisk Technologies Inc. Secure memory card with life cycle phases
FR2881836A1 (fr) * 2005-02-08 2006-08-11 St Microelectronics Sa Securisation du mode de test d'un circuit integre
US7748031B2 (en) 2005-07-08 2010-06-29 Sandisk Corporation Mass storage device with automated credentials loading
US9041411B2 (en) * 2005-08-10 2015-05-26 Nxp B.V. Testing of an integrated circuit that contains secret information
US7934049B2 (en) 2005-09-14 2011-04-26 Sandisk Corporation Methods used in a secure yet flexible system architecture for secure devices with flash mass storage memory
US7536540B2 (en) 2005-09-14 2009-05-19 Sandisk Corporation Method of hardware driver integrity check of memory card controller firmware
US20080005634A1 (en) * 2006-06-29 2008-01-03 Grise Gary D Scan chain circuitry that enables scan testing at functional clock speed
US20080072058A1 (en) * 2006-08-24 2008-03-20 Yoram Cedar Methods in a reader for one time password generating device
US8423794B2 (en) 2006-12-28 2013-04-16 Sandisk Technologies Inc. Method and apparatus for upgrading a memory card that has security mechanisms for preventing copying of secure content and applications
US7987331B2 (en) 2007-11-15 2011-07-26 Infineon Technologies Ag Method and circuit for protection of sensitive data in scan mode
BRPI1011007A2 (pt) * 2009-06-09 2016-08-09 Sharp Kk dispositivo eletrônico
CN102253305B (zh) * 2011-05-04 2013-09-18 北京荣科恒阳整流技术有限公司 一种大电流整流器设备的熔断器状态检测方法
JP5793978B2 (ja) * 2011-06-13 2015-10-14 富士通セミコンダクター株式会社 半導体装置
CN103454577A (zh) * 2012-05-31 2013-12-18 国际商业机器公司 扫描链结构和扫描链诊断的方法和设备

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761695A (en) 1972-10-16 1973-09-25 Ibm Method of level sensitive testing a functional logic system
DE2738113C2 (de) 1976-09-06 1998-07-16 Gao Ges Automation Org Vorrichtung zur Durchführung von Bearbeitungsvorgängen mit einem Identifikanden
US4534028A (en) 1983-12-01 1985-08-06 Siemens Corporate Research & Support, Inc. Random testing using scan path technique
US5039939A (en) * 1988-12-29 1991-08-13 International Business Machines Corporation Calculating AC chip performance using the LSSD scan path
US5198759A (en) * 1990-11-27 1993-03-30 Alcatel N.V. Test apparatus and method for testing digital system
US5530753A (en) * 1994-08-15 1996-06-25 International Business Machines Corporation Methods and apparatus for secure hardware configuration
US5627478A (en) * 1995-07-06 1997-05-06 Micron Technology, Inc. Apparatus for disabling and re-enabling access to IC test functions
US5659508A (en) * 1995-12-06 1997-08-19 International Business Machine Corporation Special mode enable transparent to normal mode operation
US5760719A (en) * 1995-12-29 1998-06-02 Cypress Semiconductor Corp. Programmable I/O cell with data conversion capability
DE19604776A1 (de) 1996-02-09 1997-08-14 Siemens Ag Auftrennbare Verbindungsbrücke (Fuse) und verbindbare Leitungsunterbrechung (Anti-Fuse), sowie Verfahren zur Herstellung und Aktivierung einer Fuse und einer Anti-Fuse
JPH09281186A (ja) * 1996-04-12 1997-10-31 Nec Corp 遅延時間特性測定回路
US5898776A (en) * 1996-11-21 1999-04-27 Quicklogic Corporation Security antifuse that prevents readout of some but not other information from a programmed field programmable gate array
DE19711478A1 (de) 1997-03-19 1998-10-01 Siemens Ag Integrierte Schaltung und Verfahren zum Testen der integrierten Schaltung
US6499124B1 (en) * 1999-05-06 2002-12-24 Xilinx, Inc. Intest security circuit for boundary-scan architecture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100414314C (zh) * 2002-05-22 2008-08-27 Nxp股份有限公司 具有固定电压输出的单元的集成电路

Also Published As

Publication number Publication date
DE59904556D1 (de) 2003-04-17
JP2002525888A (ja) 2002-08-13
EP0992809A1 (de) 2000-04-12
UA55561C2 (uk) 2003-04-15
KR20010075423A (ko) 2001-08-09
US20010025355A1 (en) 2001-09-27
RU2211457C2 (ru) 2003-08-27
WO2000019224A1 (de) 2000-04-06
BR9914083A (pt) 2001-07-24
US6601202B2 (en) 2003-07-29
JP3605361B2 (ja) 2004-12-22
EP1116042A1 (de) 2001-07-18
CN1320214A (zh) 2001-10-31
ES2195616T3 (es) 2003-12-01
ATE234472T1 (de) 2003-03-15
EP1116042B1 (de) 2003-03-12
KR100408123B1 (ko) 2003-12-18

Similar Documents

Publication Publication Date Title
CN1145039C (zh) 具有可去活的扫描电路的电路装置
CN1790290B (zh) 防止对ic装置内的专有信息的非授权访问的方法和系统
KR100508891B1 (ko) 집적 회로에 대한 어택을 검출하기 위한 회로 장치 및 방법
EP1917535B1 (en) Testing of an integrated circuit that contains secret information
EP1915632B1 (en) Testing of an integrated circuit that contains secret information
CN106556792B (zh) 能够进行安全扫描的集成电路
US7620864B2 (en) Method and apparatus for controlling access to and/or exit from a portion of scan chain
CN1617654B (zh) 一种抗干扰的电路板设计及相关的程序和存储媒体
US20110031982A1 (en) Tamper-resistant electronic circuit and module incorporating electrically conductive nano-structures
CN101971183B (zh) 用于测试密码电路的方法、能够被测试的保密密码电路和该电路的接线方法
RU2001111894A (ru) Схемная компоновка с деактивируемой цепью сканирования
CN104715121B (zh) 基于三模冗余的防御硬件木马威胁的电路安全性设计方法
CN1292111A (zh) 具有模糊功耗的数据载体
US20080244749A1 (en) Integrated circuits including reverse engineering detection using differences in signals
US8195995B2 (en) Integrated circuit and method of protecting a circuit part of an integrated circuit
KR20100053501A (ko) 집적 회로 보호 및 검출 그리드
CN1714508A (zh) 用于修复集成电路设计缺陷的备用单元结构
CN114814531A (zh) 一种芯片安全测试电路及逻辑芯片
CN104346583B (zh) 用于保护可编程器件的配置扫描链的方法和装置
KR20080055074A (ko) 스마트 정션박스를 이용한 이중 전원시스템 및 그의 라인쇼트 감지방법
CN112052484B (zh) 自检电路及自检方法、安全芯片和电子卡
CN100371727C (zh) 电子电路和用于测试的方法
US6720785B2 (en) Integrated circuit with test mode, and test configuration for testing an integrated circuit
CN100559203C (zh) 包括秘密的子模块的电子电路
EP1734371A1 (en) Frequency sensor and semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term

Granted publication date: 20040407

CX01 Expiry of patent term