CN1155083C - 电子组件与其制造方法及其所用的引线架 - Google Patents

电子组件与其制造方法及其所用的引线架 Download PDF

Info

Publication number
CN1155083C
CN1155083C CNB971029261A CN97102926A CN1155083C CN 1155083 C CN1155083 C CN 1155083C CN B971029261 A CNB971029261 A CN B971029261A CN 97102926 A CN97102926 A CN 97102926A CN 1155083 C CN1155083 C CN 1155083C
Authority
CN
China
Prior art keywords
mentioned
resin
lead
building brick
electronic building
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB971029261A
Other languages
English (en)
Other versions
CN1163478A (zh
Inventor
高田广文
谷田忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Craib Innovations Ltd
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=12845745&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CN1155083(C) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of CN1163478A publication Critical patent/CN1163478A/zh
Application granted granted Critical
Publication of CN1155083C publication Critical patent/CN1155083C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads

Abstract

本发明采用具有厚度0.2mm的厚壁部和厚度0.1mm的薄片部的引线。为防止从密封树脂拔出引线，因而所形成的薄片部比厚壁部宽度宽。半导体芯片使用导电性粘合剂固定在薄片部上。通过与树脂的一侧面同时在该树脂侧面的下端部一起切断而形成厚壁部的侧面，并以该树脂侧面为等同面露出。为满足引线隔开标准，厚壁部的底面从树脂底面突出仅0.03mm～0.05mm。用Au线与半导体芯片连接的其它引线的厚壁部，同样也在树脂侧面露出。

Description

电子组件与其制造方法 及其所用的引线架
技术领域
本发明涉及一种树脂密封封装型的电子组件，特别是，涉及适合于表面组装技术的电子组件。
背景技术
表面组装型的电子组件为大家所熟知。图22表示出了内装半导体芯片(电子元件)的现有表面组装型电子组件的外形。图22的电子组件70是一种具有薄而细长的第1-第3引线71、72、73的组件。这3条引线71、72、73由密封半导体芯片的长方形状树脂74的相对两侧分别沿水平方向伸出，并且施行曲折加工弯曲成L字型。树脂74的底面尺寸为1.6mm×0.8mm，从树脂74的3条引线71、72、73的水平方向突出尺寸各为0.4～0.6mm。引线隔开标准，应能防止给印刷线路板组装电子组件70时的引线71、72、73焊接不良(不附着焊料)，并要求树脂74的底面到印刷线路板只剩余0-0.1mm。
图23是上述电子组件70制造中使用的现有引线架的平面图。图23的引线架80由有均匀厚度的矩形金属板构成，并由框架82包围引线形成部81。连结框架82的相对两边形成连接部83，并且多组的引线71、72、73分别自框架82的相对两边伸出。该多组的引线71、72、73沿引线架80的长度方向以3.0-4.0mm间距作一维配置。
上述电子组件70的制造方法，也就是工艺过程包括：小片焊接工序、引线焊接工序、模制密封工序、切飞边工序、被覆处理工序、修整工序和成形工序。在小片焊接工序中，在图23的引线架80之中的各个第1引线71的前端部上，使用导电性粘合剂固定半导体芯片。在引线焊接工序中，各个半导体芯片上的2个电极同第2与第3引线72、73各自前端部之间，用Au线(金细线)进行电连接。在模制密封工序中，利用传递模制的金属模，用树脂74把各个半导体芯片、Au线、引线71、72、73的前端部密封成整体。在该模制密封工序中，沿引线架80的长度方向一维配置，并互相隔绝上模与下模间所形成的多个模槽。就是，由共通的浇道通过各自的浇口向各模槽注入树脂。图24表示出模制密封工序完成后的引线架80。在切飞边工序中，在模制密封工序中由于金属模与引线架80有细微间隙，在引线71、72、73上溢出的树脂飞边要除去。在被覆工序中，对由各树脂74伸出的引线71、72、73施行焊料电镀处理。此前工序的切飞边是为光滑地进行焊料电镀处理所不可缺少的。在修整工序中，切断引线71、72和73，以分开各个电子组件70。在成形工序中，如图22所示，对各个引线71、72、73施行所需的弯曲加工。
上述电子组件70具有了从树脂74的侧面伸出的细长引线71、72和73。而且，各个电子组件70与半导体芯片(电子器件)相比，占相当大的面积，结果，存在着印刷线路板的组装密度不怎么高的问题。另外，由树脂74伸出的引线71、72、73因很脆弱，当把电子组件70组装到印刷线路板上时，发生意外的引线变形，其结果也发生焊接不良问题。
上述现有的电子组件70的制造方法需要切飞边工序和成形工序。切飞边工序由于对产品并不产生任何附加价值，所以是希望省略的工序。在成形工序中，由于从树脂74伸出的引线71、72、73很脆弱，存在着预料不到的引线变形，或引线中断发生的问题。并且，在成形工序中，往往难以满足引线隔开标准，成品率降低就成为问题了。
上述的现有引线架80，因为以较大的间距，按一维方式配置多个引线71、72、73，所以由一块引线架80所能制取的电子组件70的数量不多，而且，还存在构成引线架80的金属材料的利用率低的问题。
上述现有的金属模，由于在上模与下模之间，按与上述引线架80相对应的大间距，形成以一维配置的多个模槽，因而在一次模制密封工序所制取的电子组件70数量少，同样存在生产性差的问题。
发明内容
本发明的目的在于，提供一种与以往比能实现印刷线路板高密度组装，而且组装时不易发生引线变形的树脂密封封装型的电子组件。
本发明的另一目的在于提供一种可以省出切飞边工序和成形工序的、生产性高的树脂密封型电子组件的制造方法。
本发明的另一个目的在于，改进树脂密封封装型电子组件制造用的引线架，与便与以往比能以高效率制取多个电子组件
本发明的再一个目的在于，提高树脂密封封装型电子组件的制造用金属模的生产性。
为达到上述的目的，本发明的电子组件，具备：电子元件、与该电子元件电连接的引线和密封电子元件和引线的树脂，并采用下述的结构，即：上述引线的侧面与切断树脂侧面同时形成在该树脂侧面的下端部，从而露出在与该树脂侧面的等同面上。根据该结构，由切断形成的引线侧面露出于树脂侧面的下端部。就是，本发明的电子组件在印刷线路板上占据的面积与树脂的底面积等同。根据本发明的电子组件，与细长的引线从树脂的侧面伸出的现有的电子组件相比，可提高给印刷线路板的组装密度。并且，组装到印刷线路板上时也不会发生引线变形。若稍微使引线底面从树脂底面伸出，就很容易满足引线隔开的标准。
具体地说，本发明一种树脂密封封装型的电子组件，其特征在于包括：电子元件，与上述电子元件电连接的引线，和密封上述电子元件和上述引线的树脂；上述引线具备与上述电子元件电连接的薄片部和为能在底面侧有台阶，形成得比上述薄片部要厚的厚壁部；上述引线的侧面在与上述树脂侧面的切断同时、通过在该树脂侧面的下端部一起切断而形成，并在与该树脂侧面等同的面上露出；以及上述引线的至少一部分底面从上述树脂的底面露出。根据此结构，对印刷线路板高密度组装时，由引线厚壁部的侧面和底面构成的角部提供与外部连接。若使厚壁部的底面从树脂底面伸出的尺寸比引线薄片部与厚壁部的厚度差小，能在保持引线薄片部与印刷线路板之间的绝缘的同时，还能很容易满足引线隔开标准。另外，如果把薄片部的顶面做成比厚壁部宽度大，并在薄片部设置切口，则可防止从树脂内拉出引线。电子元件被固定于引线薄片部的上边。
本发明的电子组件的制造方法用于制造树脂密封封装型的多个电子组件，其特征在于包括下列工序：在具有栅格状形成的连接部和各自向通过该连接部沿纵横二维配置的多个栅格空间伸出的多组引线部的片状引线架上，把多个电子元件分别固定在各个上述多个栅格空间中的各相应栅格空间内；把上述多个电子元件分别与上述多组引线部中的对应引线部进行电连接；用树脂部分密封上述多个电子元件和上述多组引线部，同时用附加的树脂部分密封所述连接部，使得所述树脂部分通过共通浇口被树脂连结起来，以及在隔着上述附加的树脂部分至相邻接的所述树脂部分之间进行切断，以便从上述连接部分别切开上述引线架的上述多组引线部，以及在所述树脂部分和所述附加树脂部分之间的树脂上形成各自顶部宽度比底部宽度大的沟，上述沟在所述切断工序中引导划片用的刀刃。根据本发明的制造方法，所以可省去切飞边工序。并且，由于不需要对细长的引线施行曲折加工的成形工序，所以成品率提高。
本发明还提供了一种用于制造树脂密封封装型的电子组件的板状引线架，包括：矩形的框架，上述框架的一组相对的两边和另一组相对的两边分别连结起来形成栅格状的连接部，以及通过上述连接部向沿纵横二维配置的多个栅格空间中各自延伸的多组引线部，其特征在于：构成上述多组引线部的各引线部具有：与上述框架和上述连接部具有同样厚度的厚壁部，和以比上述厚壁部宽的宽度、且能在底面侧形成台阶的比上述厚壁部薄的薄片部。根据此结构，在一块引线架上可紧密地二维配置多组引线部。于是，由一块引线架所能制取的电子组件的数量增加，并使构成引线架的金属材料的利用率提高。
附图说明
图1是有关本发明的电子组件的平面图。
图2是图1的电子组件的正面图。
图3是图1的III-III断面图。
图4是图1的IV-IV断面图。
图5是图1的电子组件制造用引线架的平面图。
图6是表示图5中的引线形成部的详细放大平面图。
图7是图6的VII-VII断面图。
图8是图6的VIII-VIII断面图。
图9是图5的引线架模制密封工序完成后的平面图。
图10是表示图9中的模制部的详细放大平面图。
图11是图10的XI-XI断面图。
图12是图10的XII-XII断面图。
图13是有关本发明的另一个电子组件的正面图。
图14是有关本发明的又另一个电子组件的正面图。
图15是有关本发明的又另一个电子组件的底面图。
图16是有关本发明的又另一个电子组件的底面图。
图17是有关本发明的又另一个电子组件的正面图。
图18是图17的XVIII-XVIII断面图。
图19是图17的XIX-XIX断面图。
图20是与图11相对应的，有关图17的电子组件的断面图。
图21是与图12相对应的，有关图17的电子组件的断面图。
图22是现有的电子组件的斜视图。
图23是现有的引线架的平面图。
图24是图23的引线架的模制密封工序完成后的平面图。
具体实施方式
下面，一边参照附图，一边详细说明本发明的具体实施例。
图1-图4表示有关本发明的表面组装型电子组件的外形和内部构造图。图1是平面图、图2是正面图、图3是III-III断面图及图4是IV-IV断面图。图1-图4的电子组件10为具有第1-第3引线11、12和13、半导体芯片(电子元件)15以及树脂18。长方体状的树脂18的底面尺寸是1.6mm×0.8mm；第1-第3引线11、12、13的长度无论哪一条引线都是0.65mm。
第1引线11配备长0.15mm、宽0.2mm、厚0.2mm的厚壁部11a和长0.5mm、宽0.5mm、厚0.1mm的薄片部11b。在第1引线11的底面侧形成0.1mm的台阶；该第1引线11顶面则是平坦的。为了防止从树脂18拔出第1引线11，形成薄片部11b的顶面(0.5mm×0.5mm)要比厚壁部11a幅度宽，而且，具有比半导体芯片15大的面积。半导体芯片15用导电性粘合剂14固定在薄片部11b上。因此，半导体芯片15的背面与第1引线11进行电连接。通过与切断树脂18的一侧面的同时对该树脂侧面的下端部一起切断，从而形成厚壁部11a的侧面(0.2mm×0.2mm)，并在以该树脂侧面为等同面上露出。
第2引线12配备长0.15mm、宽0.2mm、厚0.2mm的厚壁部12a和长0.5mm、宽0.3mm、厚0.1mm的薄片部12b。第3引线13同样也配备长0.15mm、宽0.2mm、厚0.2mm的厚壁部13a和长0.5mm、宽0.3mm、厚0.1mm的薄片部13b。在第2和第3引线12、13的底面侧，分别形成0.1mm的台阶；该第2和第3引线12、13顶面则是平坦的。为了防止从树脂18拔出第2和第3引线12和13，所以形成第2和第3引线的各自薄片部12b、13b的顶面要比厚壁部12a、13a幅度宽，而且，薄片部12b和13b分别具有切口12c和13c，作为防止引线从树脂18拔出的装置。两个切口12c和13c的深度为0.8mm。通过与切断树脂18的另一侧面的同时，对该树脂侧面的下端部一起切断而形成厚壁部12a和13a的侧面(0.2mm×0.2mm)，并分别在以该树脂侧面为等同面上露出。另外，半导体芯片15上的2个电极和第2与第3引线的各自薄片部12b与13b之间用Au线16、17进行电连接。还有，第1-第3引线11、12、13都是由容易切断的柔软材料，例如FeNi合金、Cu、Al之中的任何一种材料构成。
树脂18密封第1-第3引线11、12、13的大部分、半导体芯片15和Au线16、17。对树脂顶面的周缘部18a施行倒棱成形。并且，在树脂顶面的一角形成直径0.2-0.3mm的凹部，作为极性标记18b。第1-第3引线的各厚壁部11a、12a、13a的底面(0.15mm×0.2mm)都从树脂底面18c露出，而且，满足引线隔开标准，仅突出0.03-0.05mm。由于该突出尺寸比各自引线的厚壁部11a、12a、13a与薄片部11b、12b、13b的厚度差，即，比0.1mm还要小，所以第1-第3引线的各薄片部11b、12b、13b的底面完全为树脂18所覆盖。还有，对第1-第3引线11、12、13的各露出面施行焊料电镀处理。焊料的镀膜厚度以4-15μm为合适。
若采用上述的电子组件10，当组装到印刷线路板上时，由各个引线的厚壁部11a、12a、13a的侧面与底面构成的角部提供与外部连接。因为对该角部施行焊料电镀处理，所以组装时的焊料沾润性好。并且，该电子组件10在印刷线路板上占有的面积与树脂底面18c的面积相等。从而，可提高印刷线路板的组装密度。而且，组装时也不用担心发生引线变形。
图5-图8表示上述电子组件10制造中所使用的引线架。图5是平面图、图6是放大平面图、图7是VII-VII断面图和图8是VIII-VIII断面图。图5-图8的引线架30是由矩形的金属板构成，并以框架32包围引线形成部31。框架32的尺寸是纵20mm、横50mm、厚0.2mm。框架32，如图5所示，在四角配备直径1mm的决定位置用的孔33，并在一长边配备直径2mm的7个传送孔34。
引线形成部31，详细情况如图6-图8所示，它具备连接框架32的上下两长边的纵连部35和连接框架32的左右两短边的横连部36。纵连部35和横连部36的尺寸都是宽0.2mm、厚0.2mm。该纵连部35和横连部36，按11行20列形成二维配置的220个栅格空间。栅格空间的间距是纵1.3mm和横2.1mm。第1-第3引线11、12、13分别伸向该220个的各栅格空间。就是，220组的引线11、12、13以纵1.3mm、横2.1mm的间距而成二维配置。这样的间距是现有间距的1/2-1/3。第1引线部11是从框架32和横连部36向下方、第2和第3引线部12和13是从框架32和横连部36向上方，各自伸出0.8mm。
各个第1引线11都具备长0.3mm、宽0.2mm、厚0.2mm的基端部11a和长0.5mm、宽0.5mm、厚0.1mm的前端部11b。在第1引线部11的底面侧形成0.1mm的台阶。形成前端部11b的顶面(0.5mm×0.5mm)比基端部11a的顶面宽度要宽。
各个第2引线部12配备长0.3mm、宽0.2mm、厚0.2mm的基端部12a和长0.5mm、宽0.3mm、厚0.1mm的前端部12b。各个第3引线13同样也配备长0.3mm、宽0.2mm、厚0.2mm的基端部13a和长0.5mm、宽0.3mm、厚0.1mm的前端部13b。在第2和第3引线部12和13的底面侧，分别形成0.1mm的台阶。形成第2和第3引线部的各前端部12b和13b的顶面，比基端部12a和13a的顶面宽度要宽。而且，第2和第3引线部的各前端部12b和13b，分别具有深度为0.08mm的切口12c和13c。
上述第1-第3引线部11、12、13的底面侧台阶，可通过压印、刻蚀或冲压形成。上述的7个传送孔34，设置于与11行20列的栅格空间的自左起第2、5、8、11、13、16和19个列对应的位置(参照图5)。
若采用上述引线架30的结构，在一块引线架30上可紧密地二维配置220组引线部11、12和13。从而，与以往相比增加了用一块引线架30所能制取的电子组件10的数量，并且提高了制成引线架30的金属材料的利用率。
上述电子组件10的制造方法，即，组装工艺过程包括：小片焊接工序、引线焊接工序、模制密封工序、切割工序(切断工序)以及被覆工序。在小片焊接工序中，用导电性粘合剂14，把半导体芯片15固定在上述引线架30之中的第1引线部11的前端部11b上。在引线焊接工序中，半导体芯片15上的2个电极和第2和第3引线部12和13的各自前端部12b与13b之间，用Au线16、17进行电连接。在这些小片焊接工序和引线焊接工序中，为了在一块引线架30上装配220个半导体芯片15，利用设置于该引线架的框架32上的传送孔34进行传送。在模制密封工序中，使用用于传递模制的金属模，用树脂18整体密封引线部11、12与13的大部分、半导体芯片15和Au线16与17。
图9-图12表示上述引线架30的模制密封工序完成后的状态图。图9是平面图、图10是放大平面图、图11是XI-XI断面图和图12是XII-XII断面图。在图9中，41表示用于注入树脂的10个共通浇口；42表示由上下的金属模成形的模制部。把10个共通浇口41设置在与引线架30的11行20列的栅格空间，从左起第1、3、5、7、9、12、14、16、18和20个列对应的位置。
在模制部42中，详细情况如图10-图12所示，在各个栅格空间形成密封引线部11、12、13的大部分、半导体芯片15和Au线16、17的树脂18，与此同时，在纵连部35和横连部36上形成附加的树脂43、44和45。附加的树脂43、44和45具有与密封树脂18同样的高度。通过附加的树脂43、44和45，纵横互相连接着各个密封树脂18，并对周缘部18a施行倒棱成形，而且在顶平面的一角形成直径0.2-0.3mm的极性标记18b。纵连部35上作为凸条而形成的附加树脂43，对周缘部进行倒棱成形，且顶平面的宽度成为与纵连部35的宽度(0.2mm)一致。也就是，夹着附加的树脂43，在互相邻接的2个树脂18之间，沿纵连部35，形成各自具有比沟底宽度要宽的沟顶宽度的2条沟。横连部36上作为凸条而形成的附加树脂44，同样也对周缘部进行倒棱成形，而且顶平面的宽度变成与横连部36的宽度(0.2mm)一致。也就是，夹着附加的树脂44，在互相邻接的2个树脂18之间，沿横连部36，形成各自具有比沟底宽度要宽的沟顶宽度的2条沟。纵连部35和横连部36的交叉处所形成的附加树脂45，对周缘部进行倒棱成形，并且顶平面的尺寸变成0.2mm×0.2mm。还有，图10-图12表示出，在引线架的框架32上，也成形一连串的附加的树脂43、44和45。
图11和图12表示出模制密封工序所用的上模51和下模52。下模52安置装配了纵横二维配置的220个半导体芯片15的引线架30。为使第1-第3引线部的各个基端部11a、12a、13a的底面(0.3mm×0.2mm)、框架32、纵连部35和横连部36的各个底面都能从树脂底面18c突出0.03-0.05mm，因而在该下模52的成形面设置多个凹部。在上模与下模之间，形成用于树脂成形的纵横二维配置的220个模槽和用于附加树脂43、44、45成形的具有与该模槽同样高度的空间。通过该空间，使220个模槽纵横互相连结。上模51的成形面上设置多个凹部，该凹部分别具有可形成各个模槽的大部分和该模槽连接空间的大部分的深度。从共通的浇道，通过上述10个共通浇口41，注入的树脂很容易充填到所有模槽和该模槽连接的空间里。每个共通浇口41角度为30°，尺寸为0.4mm×0.2mm。还有，至少上模51和下模52的一方配备有可嵌入引线架的框架32上所设置的决定位置用的孔33的销钉(图未示)。因而，可防止金属模具与引线架30的位置错动。
根据上述金属模具的结构，一次可给220个半导体芯片15与220组的第1-第3引线部11、12、13进行树脂密封。因而，在一次模制密封工序中，所制取的电子组件10的数量比以往增加，提高了生产性。还有，只要更换上模51，便可随意改变大部分密封树脂18的外形。
在切割工序中，当在与互相邻接的2个半导体芯片15对应的2个电子组件10各自的封装侧面上同时形成树脂切断面和引线切断面时，可用一把宽为0.5mm的刀刃，将引线架30与树脂18、43、44和45同时切断。刀刃的宽度比引线架的纵连部35和横连部36的宽度(0.2mm)宽0.3mm。图10-图12中的W1和W2表示出0.5mm的切割宽度。设置于引线架的框架32上的决定位置用的孔33，用于识别切割位置。另外，附加的树脂43、44、45的各个顶面(宽度0.2mm)位于切断宽度W1与W2的中心，由于倒棱而形成纵横的沟以刀刃的行进方向引导用于切割的刀刃。其结果，可分开备有1.6mm×0.8mm的底面尺寸的长方体状的树脂18和具备长度各为0.65mm的第1-第3引线11、12和13的各个电子组件10。这时，在引线架30中，各个引线部的基端部11a、12a和13a之中的长度为0.15mm的基部分别被切除。因而，在树脂18的一侧面的下端部，第1引线11的切断面(0.2mm×0.2mm)作为与该侧面的等同面露出，并且，在该树脂18的相对侧面的下端部，第2和第3引线12和13的各切断面(0.2mm×0.2mm)露出在以该相对侧面为等同面上。另外，在封装的底面，分别形成第1-第3引线11、12、13的各自突出面(0.15mm×0.2mm)。还有，如果在含有第1-第3引线部11、12、13的引线架30中，采用上述那种容易切断的柔性材料，则可减轻切割刀刃的磨损，结果，可抑制切断宽度的变动和切断速度的下降。
在被覆工序中，对第1-第3引线11、12、13的各露出面施加膜厚4-15μm的焊料电镀处理。其结果，在封装侧面上已形成的第1-第3引线11、12、13的各切断面(0.2mm×0.2mm)上和在封装底面已形成的第1-第3引线11、12、13的各突出面(0.15mm×0.2mm)上，分别形成焊料膜。还有，采用其它种类的镀覆处理方法，来代替焊料电镀处理也是可以的。另外，根据引线架30的材料性质，还可省去电镀处理。
若采用上述电子组件10的制造方法，因为在封装侧面上同时形成树脂切断面和引线切断面，所以可省去切飞边工序。另外，与以往不同，由于不再需要对细长的引线进行曲折加工的成形工序，从而提高成品率。
图13和图14表示出有关本发明的其它表面组装型电子组件的外形图。图13的电子组件20是在树脂顶面的周缘部18a设置台阶，而不是倒棱。如上述，在模制密封工序中，只更换上模51，就可随意变更树脂18的外形。图14的电子组件21把树脂18制成完全长方体形状，而且，在以树脂底面18c为等同面上，分别露出各引线的厚壁部11a、12a、13a的底面。在这种情况下，下模52的成形面可以是平坦的。即使在图14的结构中，若对第1-第3引线11、12、13的各露出面施行膜厚为4-15μm的焊料电镀处理，也能满足引线隔开标准。但是，若采用图1-图4的电子组件10或图13的电子组件20，因为在树脂顶面的周缘部18a设置倒棱或台阶，所以在切断树脂18的4个侧面之际，与图14的电子组件21的情况比较，切断总树脂厚度较小，切断也方便。
并且，例如图14的电子组件21，使引线厚壁部11a、12a、13a的底面以树脂底面18c为等同面而露出时，特别是在引线架的中央部存在着在模制密封工序中所注入的树脂侵入下模的平坦的成形面与引线厚壁部11a、12a、13a的底面之间的危险。图15和图16表示出该解决方案的实例。图15的电子组件22是在树脂底面18c设置T字状沟18d。图16的电子组件23是在树脂底面18c设置3个U字状沟18e、18f、18g。这些沟18e、18f和18g分别形成以包围各引线厚壁部11a、12a、13a的露出底面。若采用这些实例，在模制密封工序中，与沟18d、18e、18f和18g各自相应的下模凸条降低了树脂压力，所以能防止上述树脂的侵入。
图17-图19表示出有关本发明的又另一个表面组装型电子组件的外形和内部结构图。图17是正面图；图18是XVIII-XVIII断面图；图19是XIX-XIX断面图。图17-图19的电子组件24，对树脂顶面的周缘部18a施行倒棱，而且，在与树脂底面18c等同面上，分别露出各个引线的厚壁部11a、12a、13a的底面。本电子组件24的树脂侧面，是由在切割工序中在该树脂侧面的下端部与引线切断面同时形成的切断面18x，和在模制密封工序中形成的非切割面18y构成。树脂侧面的切断面18x与树脂底面18c垂直，而且其中的另一部分是共通浇口切断面18z。共通浇口切断面18z位于第2和第3引线厚壁部12a、13a的各自切断侧面之间。为使密封树脂18容易从金属模具内取出，树脂侧面的非切断面18y与树脂底面18c至少有3°的倾斜角。还有，对第1-第3引线11、12、13的各个露出面都进行焊料电镀处理。图5-图8的引线架30也可用于本电子组件24的制造。
图20和图21表示出有关上述电子组件24的模制密封工序完成后的状态，并分别与图11和图12相对应。在图20和图21中，分别表示出：51为上模、52为下模及41为树脂注入的共通浇口。在上模51与下模52之间，形成用于密封树脂18成形的，成纵横二维配置的220个模槽。但是，这些模槽，通过共通浇口41，只在列方向互相进行连接。共通浇口41设置在与11行20列的模槽的各列相对应的位置。而且，由于下模52的成形面是平坦的，所以为了防止注入树脂的侵入并保护引线底面，将弹性片53夹入下模52与引线架之间。这时，在离开共通浇口41的位置，通过上模51，压紧各个电子组件的第2和第3引线部的基端部12a和13a。因而，根据树脂压力大小如何，即使不使用弹性片53，也能防止注入树脂的侵入。
在上述电子组件24中，在树脂18的一个侧面的下端部，以树脂切断面18x为等同面，露出第1引线11的切断面，而且，在树脂18的相对侧面的下端部，则以树脂切断面18x为等同面，露出第2和第3引线12、13的各自切断面。此外，进行模制密封，以便以树脂底面18c为等同面，露出第1-第3引线11、12、13的各底面。并且，各引线11、12、13的露出切断面与露出底面是连接着的，在这里，形成与外部连接的引线角部。从而，上述电子组件24是表面组装技术里最佳的超小型组件。
还有，在上述各实施例中，半导体芯片(电子元件)15和第2和第3引线12与13的电连接，不限于用Au线16与17做连接。使用在绝缘性基片上刻制成同样的引线图形的，而不用板状的引线架30，也是可行的。又在上述各实施例中，仅对第1-第3引线11、12、13各自的露出底面施行焊料电镀处理也可。
并且，引线的数量不限于上述的实施例。可将任何电子元件安装在本发明的电子组件10、20、21、22、23及24内，而不是装半导体芯片15。

Claims (27)

1、一种树脂密封封装型的电子组件，其特征在于包括：
电子元件，
与上述电子元件电连接的引线，和
密封上述电子元件和上述引线的树脂；
上述引线具备与上述电子元件电连接的薄片部和为能在底面侧有高低差而形成得比上述薄片部厚的厚壁部；
上述引线的侧面在切断上述树脂侧面的同时、通过在该树脂侧面的下端部一起切断而形成，并在与该树脂侧面等同的面上露出；以及
上述引线的至少一部分底面从上述树脂的底面露出。
2、根据权利要求1所述的电子组件，其特征在于：
上述引线的露出底面从上述树脂的底面突出的尺寸小于所述厚壁部和所述薄片部的厚度的差。
3、根据权利要求1所述的电子组件，其特征在于：
上述树脂的底面，在上述引线的露出底面周围具有沟。
4、根据权利要求1所述的电子组件，其特征在于：
上述树脂的顶面，在周缘部具有倒棱或台阶。
5、根据权利要求1所述的电子组件，其特征在于：
上述树脂的侧面具有切断上述引线时形成的切断面和上述密封之际形成的非切断面。
6、根据权利要求5所述的电子组件，其特征在于：
上述树脂侧面的的切断面与该树脂的底面垂直，并且上述树脂侧面的非切断面相对于该树脂的底面倾斜。
7、根据权利要求5所述的电子组件，其特征在于：
在上述树脂的侧面下端部，该树脂侧面的切断面是与该树脂的底面垂直形成的。
8、根据权利要求5所述的电子组件，其特征在于：
上述树脂的四个侧面下端部，任何一个都是通过切断，与该树脂的底面垂直形成的。
9、根据权利要求1所述的电子组件，其特征在于：
上述厚壁部的露出底面从上述树脂的底面突出的尺寸比上述薄片部和上述厚壁部的厚度差还小。
10、根据权利要求1所述的电子组件，其特征在于：
上述薄片部的顶面比上述厚壁部的顶面宽度要宽。
11、根据权利要求1所述的电子组件，其特征在于：
所述引线由第1引线以及至少一根第2引线构成；
所述第1引线的薄片部的顶面具有比所述电子元件要大的面积，而且，把上述电子元件固定在上述第1引线的薄片部上。
12、根据权利要求11所述的电子组件，其特征在于：
上述第2引线的薄片部具有防止引线从上述树脂拔出的切口。
13、一种电子组件的制造方法，用于制造树脂密封封装型的多个电子组件，其特征在于包括下列工序：
在具有栅格状形成的连接部和各自向通过该连接部沿纵横二维配置的多个栅格空间伸出的多组引线部的片状引线架上，把多个电子元件分别固定在各个上述多个栅格空间中的各相应栅格空间内；
把上述多个电子元件分别与上述多组引线部中的对应引线部进行电连接；
用树脂部分密封上述多个电子元件和上述多组引线部，同时用附加的树脂部分密封所述连接部，使得所述树脂部分通过共通浇口被树脂连结起来，以及
隔着上述附加的树脂部分、在互相邻接的所述树脂部分之间进行切断，以便从上述连接部分别切开上述引线架的上述多组引线部，
其中，在所述树脂部分和所述附加树脂部分之间的树脂上形成各自顶部宽度比底部宽度大的沟，上述沟在所述切断工序中引导划片用的刀刃。
14、根据权利要求13所述的电子组件的制造方法，其特征在于上述密封工序包括：
在离开上述共通浇口的位置通过上模压紧上述引线架之中的上述引线部的工序。
15、根据权利要求13所述的电子组件的制造方法，其特征在于上述密封工序包括：
密封上述多组引线部以使上述多组引线部的各底面从上述树脂的底面露出的工序。
16、根据权利要求13所述的电子组件的制造方法，其特征在于：
至少在上述多个电子元件的上述树脂切断面和引线切断面同时形成的位置上形成上述多个沟。
17、根据权利要求13所述的电子组件的制造方法，其特征在于：
上述多个沟是沿上述引线架的连接部成纵横形成的。
18、根据权利要求13所述的电子组件的制造方法，其特征在于：
上述多个沟分别是至少2条互相平行的细沟。
19、根据权利要求13所述的电子组件的制造方法，其特征在于包括：
沿上述引线架的连接部，在上述树脂的表面上形成用于决定在上述切断工序中的刀刃位置的多个凸条的工序。
20、根据权利要求19所述的电子组件的制造方法，其特征在于：
上述多个凸条是沿上述引线架的连接部成纵横形成的。
21、根据权利要求19所述的电子组件的制造方法，其特征在于：
上述多个凸条对周缘部进行倒棱成形，且其顶面宽度与上述连接部的宽度相等。
22、根据权利要求13所述的电子组件的制造方法，其特征在于，上述切断工序包括：
用宽度大于上述引线架的连接部宽度的一片刀刃，把上述引线架与上述树脂一起切断的工序。
23、一种用于制造树脂密封封装型的电子组件的板状引线架，包括：
矩形的框架，
上述框架的一组相对的两边和另一组相对的两边分别连结起来形成栅格状的连接部，以及
通过上述连接部向沿纵横二维配置的多个栅格空间中各自延伸的多组引线部，其特征在于：
构成上述多组引线部的各引线部具有：
与上述框架和上述连接部具有同样厚度的厚壁部，和
以比上述厚壁部宽的宽度、且能在底面侧形成台阶的比上述厚壁部薄的薄片部。
24、根据权利要求23所述的引线架，其特征在于：
上述多组引线部之中的特定引线部的薄片部的顶面大于其上所固定的电子元件的面积。
25、根据权利要求23所述的引线架，其特征在于：
上述多组引线部之中的特定引线部的薄片部的顶面形成得比所述厚壁部宽、且具有切口。
26、根据权利要求23所述的引线架，其特征在于：
上述框架在四个角配备树脂密封和上述多组引线部切断时使用的决定位置用的孔。
27、根据权利要求23所述的引线架，其特征在于：
上述框架一边配备多个传送孔。
CNB971029261A 1996-03-07 1997-03-06 电子组件与其制造方法及其所用的引线架 Expired - Lifetime CN1155083C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP4996596 1996-03-07
JP049965/1996 1996-03-07
JP049965/96 1996-03-07

Publications (2)

Publication Number Publication Date
CN1163478A CN1163478A (zh) 1997-10-29
CN1155083C true CN1155083C (zh) 2004-06-23

Family

ID=12845745

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB971029261A Expired - Lifetime CN1155083C (zh) 1996-03-07 1997-03-06 电子组件与其制造方法及其所用的引线架

Country Status (3)

Country Link
US (2) US5977613A (zh)
EP (3) EP1517372A2 (zh)
CN (1) CN1155083C (zh)

Families Citing this family (180)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5677566A (en) * 1995-05-08 1997-10-14 Micron Technology, Inc. Semiconductor chip package
US6821821B2 (en) * 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
JP3877401B2 (ja) * 1997-03-10 2007-02-07 三洋電機株式会社 半導体装置の製造方法
US6201292B1 (en) * 1997-04-02 2001-03-13 Dai Nippon Insatsu Kabushiki Kaisha Resin-sealed semiconductor device, circuit member used therefor
US6130473A (en) * 1998-04-02 2000-10-10 National Semiconductor Corporation Lead frame chip scale package
JP3862410B2 (ja) * 1998-05-12 2006-12-27 三菱電機株式会社 半導体装置の製造方法及びその構造
JP3562311B2 (ja) * 1998-05-27 2004-09-08 松下電器産業株式会社 リードフレームおよび樹脂封止型半導体装置の製造方法
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
JP2000022044A (ja) * 1998-07-02 2000-01-21 Mitsubishi Electric Corp 半導体装置とその製造方法
US6281568B1 (en) 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
US6448633B1 (en) * 1998-11-20 2002-09-10 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
NL1011929C2 (nl) * 1999-04-29 2000-10-31 3P Licensing Bv Werkwijze voor het inkapselen van elektronische componenten, in het bijzonder geintegreerde schakelingen.
US6274927B1 (en) 1999-06-03 2001-08-14 Amkor Technology, Inc. Plastic package for an optical integrated circuit device and method of making
KR200309906Y1 (ko) 1999-06-30 2003-04-14 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조용 리드프레임
US6247229B1 (en) * 1999-08-25 2001-06-19 Ankor Technology, Inc. Method of forming an integrated circuit device package using a plastic tape as a base
US20020100165A1 (en) 2000-02-14 2002-08-01 Amkor Technology, Inc. Method of forming an integrated circuit device package using a temporary substrate
KR100364978B1 (ko) 1999-10-15 2002-12-16 앰코 테크놀로지 코리아 주식회사 반도체패키지의 와이어 본딩용 클램프 및 히트블록
KR100526844B1 (ko) 1999-10-15 2005-11-08 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
KR100403142B1 (ko) 1999-10-15 2003-10-30 앰코 테크놀로지 코리아 주식회사 반도체패키지
KR20010056618A (ko) 1999-12-16 2001-07-04 프랑크 제이. 마르쿠치 반도체패키지
KR100355796B1 (ko) 1999-10-15 2002-10-19 앰코 테크놀로지 코리아 주식회사 반도체패키지용 리드프레임 및 이를 봉지하기 위한 금형 구조
KR20010037247A (ko) 1999-10-15 2001-05-07 마이클 디. 오브라이언 반도체패키지
KR20010037252A (ko) 1999-10-15 2001-05-07 마이클 디. 오브라이언 반도체패키지 제조용 금형
KR20010037254A (ko) 1999-10-15 2001-05-07 마이클 디. 오브라이언 반도체패키지
US6525406B1 (en) 1999-10-15 2003-02-25 Amkor Technology, Inc. Semiconductor device having increased moisture path and increased solder joint strength
KR100355794B1 (ko) 1999-10-15 2002-10-19 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지
KR100355795B1 (ko) 1999-10-15 2002-10-19 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조 방법
US6580159B1 (en) 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6847103B1 (en) 1999-11-09 2005-01-25 Amkor Technology, Inc. Semiconductor package with exposed die pad and body-locking leadframe
US6476478B1 (en) 1999-11-12 2002-11-05 Amkor Technology, Inc. Cavity semiconductor package with exposed leads and die pad
US6415505B1 (en) * 1999-11-15 2002-07-09 Amkor Technology, Inc. Micromachine package fabrication method
US6459147B1 (en) * 2000-03-27 2002-10-01 Amkor Technology, Inc. Attaching semiconductor dies to substrates with conductive straps
TW432557B (en) * 1999-12-14 2001-05-01 Siliconware Precision Industries Co Ltd Chip-scale package and its manufacturing method
KR100421774B1 (ko) 1999-12-16 2004-03-10 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조 방법
US6639308B1 (en) 1999-12-16 2003-10-28 Amkor Technology, Inc. Near chip size semiconductor package
KR100426494B1 (ko) 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
US6198171B1 (en) * 1999-12-30 2001-03-06 Siliconware Precision Industries Co., Ltd. Thermally enhanced quad flat non-lead package of semiconductor
KR20010058583A (ko) 1999-12-30 2001-07-06 마이클 디. 오브라이언 리드 엔드 그리드 어레이 반도체패키지
US6342730B1 (en) * 2000-01-28 2002-01-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
DE10004410A1 (de) * 2000-02-02 2001-08-16 Infineon Technologies Ag Halbleiterbauelement mit an der Unterseite befindlichen Kontakten und Verfahren zur Herstellung
KR100583494B1 (ko) * 2000-03-25 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지
KR100559664B1 (ko) 2000-03-25 2006-03-10 앰코 테크놀로지 코리아 주식회사 반도체패키지
US7042068B2 (en) 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US6424031B1 (en) 2000-05-08 2002-07-23 Amkor Technology, Inc. Stackable package with heat sink
US6518659B1 (en) 2000-05-08 2003-02-11 Amkor Technology, Inc. Stackable package having a cavity and a lid for an electronic device
JP2001326295A (ja) * 2000-05-15 2001-11-22 Rohm Co Ltd 半導体装置および半導体装置製造用フレーム
US6667544B1 (en) 2000-06-30 2003-12-23 Amkor Technology, Inc. Stackable package having clips for fastening package and tool for opening clips
JP3660861B2 (ja) * 2000-08-18 2005-06-15 株式会社ルネサステクノロジ 半導体装置の製造方法
KR20020058209A (ko) 2000-12-29 2002-07-12 마이클 디. 오브라이언 반도체패키지
US6740950B2 (en) 2001-01-15 2004-05-25 Amkor Technology, Inc. Optical device packages having improved conductor efficiency, optical coupling and thermal transfer
KR100731007B1 (ko) * 2001-01-15 2007-06-22 앰코 테크놀로지 코리아 주식회사 적층형 반도체 패키지
KR100394030B1 (ko) * 2001-01-15 2003-08-06 앰코 테크놀로지 코리아 주식회사 적층형 반도체 패키지
JP4731021B2 (ja) * 2001-01-25 2011-07-20 ローム株式会社 半導体装置の製造方法および半導体装置
JP3628971B2 (ja) * 2001-02-15 2005-03-16 松下電器産業株式会社 リードフレーム及びそれを用いた樹脂封止型半導体装置の製造方法
US6605865B2 (en) 2001-03-19 2003-08-12 Amkor Technology, Inc. Semiconductor package with optimized leadframe bonding strength
US6545345B1 (en) 2001-03-20 2003-04-08 Amkor Technology, Inc. Mounting for a package containing a chip
KR100369393B1 (ko) 2001-03-27 2003-02-05 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법
KR100393448B1 (ko) 2001-03-27 2003-08-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US6469398B1 (en) * 2001-03-29 2002-10-22 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
US6756658B1 (en) 2001-04-06 2004-06-29 Amkor Technology, Inc. Making two lead surface mounting high power microleadframe semiconductor packages
US6614102B1 (en) 2001-05-04 2003-09-02 Amkor Technology, Inc. Shielded semiconductor leadframe package
JP2003023134A (ja) * 2001-07-09 2003-01-24 Hitachi Ltd 半導体装置およびその製造方法
US20030032874A1 (en) * 2001-07-27 2003-02-13 Dexcom, Inc. Sensor head for use with implantable devices
US7102216B1 (en) 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making
US20080169541A1 (en) * 2001-09-19 2008-07-17 Jeffrey Alan Miks Enhanced durability multimedia card
US6611047B2 (en) 2001-10-12 2003-08-26 Amkor Technology, Inc. Semiconductor package with singulation crease
US6630726B1 (en) 2001-11-07 2003-10-07 Amkor Technology, Inc. Power semiconductor package with strap
US6686651B1 (en) 2001-11-27 2004-02-03 Amkor Technology, Inc. Multi-layer leadframe structure
JP3540793B2 (ja) * 2001-12-05 2004-07-07 松下電器産業株式会社 樹脂封止型半導体装置及びその製造方法
US6798046B1 (en) 2002-01-22 2004-09-28 Amkor Technology, Inc. Semiconductor package including ring structure connected to leads with vertically downset inner ends
JP3942457B2 (ja) * 2002-02-27 2007-07-11 Ｎｅｃエレクトロニクス株式会社 電子部品の製造方法
US6885086B1 (en) 2002-03-05 2005-04-26 Amkor Technology, Inc. Reduced copper lead frame for saw-singulated chip package
US20030183911A1 (en) * 2002-03-27 2003-10-02 International Business Machines Corporation Electronic package and method
US20040159931A1 (en) * 2002-03-27 2004-08-19 International Business Machines Corporation Electronic package, heater block and method
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US6627977B1 (en) 2002-05-09 2003-09-30 Amkor Technology, Inc. Semiconductor package including isolated ring structure
WO2003105223A2 (en) * 2002-06-06 2003-12-18 Philips Intellectual Property & Standards Gmbh Quad flat non-leaded package comprising a semiconductor device
US6841414B1 (en) 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
TW558810B (en) * 2002-07-05 2003-10-21 Siliconware Precision Industries Co Ltd Semiconductor package with lead frame as chip carrier and fabrication method thereof
US6867071B1 (en) 2002-07-12 2005-03-15 Amkor Technology, Inc. Leadframe including corner leads and semiconductor package using same
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US6910635B1 (en) 2002-10-08 2005-06-28 Amkor Technology, Inc. Die down multi-media card and method of making same
US6905914B1 (en) 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
US6847099B1 (en) 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
JP3938067B2 (ja) * 2003-02-18 2007-06-27 株式会社日立製作所 電子回路装置
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US7095103B1 (en) 2003-05-01 2006-08-22 Amkor Technology, Inc. Leadframe based memory card
US6897550B1 (en) * 2003-06-11 2005-05-24 Amkor Technology, Inc. Fully-molded leadframe stand-off feature
US6911718B1 (en) 2003-07-03 2005-06-28 Amkor Technology, Inc. Double downset double dambar suspended leadframe
CN100413043C (zh) * 2003-08-29 2008-08-20 株式会社瑞萨科技 半导体器件的制造方法
JP3789443B2 (ja) * 2003-09-01 2006-06-21 Ｎｅｃエレクトロニクス株式会社 樹脂封止型半導体装置
US6977431B1 (en) 2003-11-05 2005-12-20 Amkor Technology, Inc. Stackable semiconductor package and manufacturing method thereof
US7633763B1 (en) 2004-01-28 2009-12-15 Amkor Technology, Inc. Double mold memory card and its manufacturing method
US7074654B1 (en) 2004-04-21 2006-07-11 Amkor Technology, Inc. Tape supported memory card leadframe structure
US7556986B1 (en) 2004-04-21 2009-07-07 Amkor Technology, Inc. Tape supported memory card leadframe structure
JP3994095B2 (ja) * 2004-06-23 2007-10-17 ローム株式会社 面実装型電子部品
US7201327B1 (en) 2004-10-18 2007-04-10 Amkor Technology, Inc. Memory card and its manufacturing method
US7193305B1 (en) 2004-11-03 2007-03-20 Amkor Technology, Inc. Memory card ESC substrate insert
US7112875B1 (en) 2005-02-17 2006-09-26 Amkor Technology, Inc. Secure digital memory card using land grid array structure
US7220915B1 (en) 2005-02-17 2007-05-22 Amkor Technology, Inc. Memory card and its manufacturing method
US7719845B1 (en) 2005-04-26 2010-05-18 Amkor Technology, Inc. Chamfered memory card module and method of making same
US20090021921A1 (en) * 2005-04-26 2009-01-22 Amkor Technology, Inc. Memory card and its manufacturing method
DE102005053842B4 (de) * 2005-11-09 2008-02-07 Infineon Technologies Ag Halbleiterbauelement mit Verbindungselementen und Verfahren zur Herstellung desselben
US7837120B1 (en) 2005-11-29 2010-11-23 Amkor Technology, Inc. Modular memory card and method of making same
US7507603B1 (en) 2005-12-02 2009-03-24 Amkor Technology, Inc. Etch singulated semiconductor package
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US7359204B1 (en) 2006-02-15 2008-04-15 Amkor Technology, Inc. Multiple cover memory card
US20070270040A1 (en) * 2006-05-05 2007-11-22 Jang Sang J Chamfered Memory Card
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7927923B2 (en) 2006-09-25 2011-04-19 Micron Technology, Inc. Method and apparatus for directing molding compound flow and resulting semiconductor device packages
US7687893B2 (en) 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7829990B1 (en) 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
TWM318792U (en) * 2007-01-23 2007-09-11 Lighthouse Technology Co Ltd Package structure
US9367712B1 (en) 2007-03-01 2016-06-14 Amkor Technology, Inc. High density memory card using folded flex
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US7763958B1 (en) * 2007-05-25 2010-07-27 National Semiconductor Corporation Leadframe panel for power packages
JP5368982B2 (ja) * 2007-06-14 2013-12-18 ローム株式会社 半導体発光装置
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7714418B2 (en) * 2007-07-23 2010-05-11 National Semiconductor Corporation Leadframe panel
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
JP2009170476A (ja) * 2008-01-11 2009-07-30 Panasonic Corp 半導体装置および半導体装置の製造方法
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US20170117214A1 (en) 2009-01-05 2017-04-27 Amkor Technology, Inc. Semiconductor device with through-mold via
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
JP4766162B2 (ja) * 2009-08-06 2011-09-07 オムロン株式会社 パワーモジュール
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
JP5010693B2 (ja) * 2010-01-29 2012-08-29 株式会社東芝 Ｌｅｄパッケージ
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US9418919B2 (en) * 2010-07-29 2016-08-16 Nxp B.V. Leadless chip carrier having improved mountability
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
JP2012114311A (ja) * 2010-11-26 2012-06-14 Toshiba Corp Ｌｅｄモジュール
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8674485B1 (en) 2010-12-08 2014-03-18 Amkor Technology, Inc. Semiconductor device including leadframe with downsets
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
TWI557183B (zh) 2015-12-16 2016-11-11 財團法人工業技術研究院 矽氧烷組成物、以及包含其之光電裝置
CN102756456B (zh) * 2011-04-27 2015-04-22 无锡华润安盛科技有限公司 用于预塑封引线框的模具以及封装结构
US8866278B1 (en) 2011-10-10 2014-10-21 Amkor Technology, Inc. Semiconductor device with increased I/O configuration
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
KR101486790B1 (ko) 2013-05-02 2015-01-28 앰코 테크놀로지 코리아 주식회사 강성보강부를 갖는 마이크로 리드프레임
KR101563911B1 (ko) 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지
WO2015083263A1 (ja) * 2013-12-05 2015-06-11 新電元工業株式会社 リードフレーム、金型、実装部品付きリードフレームの製造方法
JP2015144188A (ja) * 2014-01-31 2015-08-06 株式会社東芝 半導体装置及びその製造方法
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
CN107710901B (zh) * 2015-06-30 2020-04-28 株式会社村田制作所 高频模块及其制造方法
US10508935B2 (en) 2015-10-15 2019-12-17 Advanced Semiconductor Engineering, Inc. Optical module and manufacturing process thereof
US10867894B2 (en) * 2018-10-11 2020-12-15 Asahi Kasei Microdevices Corporation Semiconductor element including encapsulated lead frames
JP6634655B1 (ja) * 2019-03-28 2020-01-22 株式会社ケーヒン パワーモジュール

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1187065A (en) * 1981-12-14 1985-05-14 Thomas L. Peters Process for etching glass capillaries for chromatography
JPS5890751A (ja) * 1982-11-15 1983-05-30 Hitachi Ltd リ−ドフレ−ムの製法
JPS59208755A (ja) * 1983-05-12 1984-11-27 Sony Corp 半導体装置のパツケ−ジ及びその製造方法
JPH0795580B2 (ja) * 1984-11-27 1995-10-11 松下電子工業株式会社 半導体装置
FR2584862B1 (fr) * 1985-07-12 1988-05-20 Eurotechnique Sa Procede de fabrication en continu de micromodules pour cartes contenant des composants, bande continue de micromodules et micromodules realises selon un tel procede
JPH0793338B2 (ja) * 1985-11-11 1995-10-09 スタンレー電気株式会社 ミニモールド型ｌｅｄの製造方法
JPH01179332A (ja) * 1987-12-31 1989-07-17 Sanken Electric Co Ltd 樹脂封止型電子装置の製造方法
US4999684A (en) * 1988-05-06 1991-03-12 General Electric Company Symmetrical blocking high voltage breakdown semiconducotr device
EP0355955A3 (en) * 1988-07-25 1991-12-27 Hitachi, Ltd. Connection for semiconductor devices or integrated circuits by coated wires and method of manufacturing the same
EP0408904A3 (en) * 1989-07-21 1992-01-02 Motorola Inc. Surface mounting semiconductor device and method
US5075759A (en) * 1989-07-21 1991-12-24 Motorola, Inc. Surface mounting semiconductor device and method
US5172214A (en) * 1991-02-06 1992-12-15 Motorola, Inc. Leadless semiconductor device and method for making the same
JP2934357B2 (ja) * 1992-10-20 1999-08-16 富士通株式会社 半導体装置
US5521429A (en) * 1993-11-25 1996-05-28 Sanyo Electric Co., Ltd. Surface-mount flat package semiconductor device
SG50009A1 (en) * 1996-03-14 1998-06-15 Towa Corp Method of sealing electronic component with molded resin

Also Published As

Publication number Publication date
EP0794572A2 (en) 1997-09-10
CN1163478A (zh) 1997-10-29
EP1517371A2 (en) 2005-03-23
US6187614B1 (en) 2001-02-13
EP0794572A3 (en) 2003-09-03
EP1517372A2 (en) 2005-03-23
US5977613A (en) 1999-11-02
EP1517371A3 (en) 2006-07-12

Similar Documents

Publication Publication Date Title
CN1155083C (zh) 电子组件与其制造方法及其所用的引线架
CN1146044C (zh) 具有弯成j-型引线端子的半导体器件
JP3209696B2 (ja) 電子部品の製造方法
CN1956157A (zh) 形成引脚模块阵列封装的方法
CN1771599A (zh) 面装配型电子部件及其制造方法
CN1309071C (zh) 引线框架以及制造该引线框架的方法
CN1457094A (zh) 半导体器件及其制造方法
CN1842915A (zh) 面装配型电子部件及其制造方法
CN103227115B (zh) 引线框及其制造方法和半导体装置及其制造方法
CN1191629C (zh) 引线框、半导体装置及其制造方法、电路基板和电子装置
CN1767185A (zh) 引线框及使用该引线框的树脂密封型半导体装置制造方法
CN1208831C (zh) 半导体用引线架
CN200944402Y (zh) 一种集成电路封装用载带
CN1184678C (zh) 半导体器件及其制造方法、电路衬底及电子仪器
CN1212535C (zh) 液晶显示装置及用于液晶显示装置的半导体芯片制作方法
JP2010021374A (ja) 半導体パッケージ
CN2718782Y (zh) 半导体封装及其引线框架
CN1427473A (zh) 导线架带和制造使用导线架带的半导体封装的方法
CN1697204A (zh) 一种发光二极管支架及其制作方法
CN1182284A (zh) 引线框和使用该引线框的半导体装置
CN1559085A (zh) 半导体装置及其制造方法
CN1606141A (zh) 引线框的制造方法、半导体装置的制造方法及半导体装置
CN1192420C (zh) 半导体器件及其制造方法、电路基板及电子装置
CN1435882A (zh) 半导体装置及其制造方法
CN103489794A (zh) 提高qfn封装引线框架制备工艺中引线框架硬度的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: KELAIBO INNOVATION CO., LTD.

Free format text: FORMER OWNER: MATSUSHITA ELECTRIC INDUSTRIAL CO, LTD.

Effective date: 20141209

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20141209

Address after: American California

Patentee after: Craib Innovations Ltd

Address before: Osaka

Patentee before: Matsushita Electric Industrial Co., Ltd.

CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20040623