CN1156978C - 固态继电器 - Google Patents

固态继电器 Download PDF

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Publication number
CN1156978C
CN1156978C CNB981026826A CN98102682A CN1156978C CN 1156978 C CN1156978 C CN 1156978C CN B981026826 A CNB981026826 A CN B981026826A CN 98102682 A CN98102682 A CN 98102682A CN 1156978 C CN1156978 C CN 1156978C
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China
Prior art keywords
source
region
drain
state relay
well region
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Expired - Fee Related
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CNB981026826A
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English (en)
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CN1222789A (zh
Inventor
铃村正彦
·
高野仁路
铃木裕二
岸田贵司
早崎嘉城
ʷ
白井良史
吉田岳司
宫本靖典
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Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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Priority claimed from JP31402997A external-priority patent/JP3319999B2/ja
Priority claimed from JP35257697A external-priority patent/JP3513851B2/ja
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Publication of CN1222789A publication Critical patent/CN1222789A/zh
Application granted granted Critical
Publication of CN1156978C publication Critical patent/CN1156978C/zh
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Abstract

一种由一对LDMOSFET串联组成的固态继电器具有最小的输出电容。每一LDMOSFET都是SOI(绝缘体上硅)的结构，它由设在支撑板上的硅衬底、硅衬底上的埋入氧化层以及埋入氧化层上的硅层组成。在硅层全深度扩散的阱区有与埋入氧化层接触的底，使阱区只在邻近沟道的小区处与硅层形成P-N界面。由于缩小了P-N界面以及埋入氧化层与硅层相比表现出很低的电容，因而就有可能为降低非导通条件下继电器的输出电容而大量降低漏-源电容。

Description

固态继电器
技术领域
本发明涉及一种固态继电器，尤其是涉及一种具有一对横向双扩散金属-氧化物-半导体场效应晶体管(LDMOSFET)的固态继电器，它以LDMOSFET的漏极作输出端用以与受继电器控制的负载相连。
背景技术
固态继电器由于包含有微小型结构、低能耗以及高速开关性能等许多优点已被广泛利用于取代机械继电器。由于有上述优点，固态继电器能够成功地组装在诸如测试大规模集成电路(LSI)芯片的自动测试设备之类的小型装置当中。当用作这类测量时，继电器就被设计成提供一系列输出信号作为测试信号。当输出信号的频率变高时，要求继电器在输出信号的断开期(即在此期内输出端处于非导通状态)在继电器的输出端之间跨接有较低的输出电容，此外还要在输出信号的导通期使输出端之间的通态电阻减至最小。输出电容为在继电器输出端处于非导通状态下漏-源电容和栅-漏电容的总量。
日本专利公开No.9-312392披露了一种固态继电器，它利用LDMOSFET作为开关元件想使输出电容减小。LDMOSFET的结构以其在一阱区的界限内扩散源区而在一漂移区的界限内扩散漏区在硅层的顶面内扩散有一阱区和一漂移区。然而，由于在硅层的顶面内形成漂移区和阱区，就形成了包括漂移区和阱区底部扩展区的一个P-N界面。这种加大的P-N界面区导致LDMOSFET的源极和漏极之间电容的增大。因此，这种结构的LDMOSFET无法满足缩小继电器输出端之间的输出电容。
发明内容
本发明克服了以上所考虑的不足，提供一种有一对与受控制的负载相连接的输出端的固态继电器，它包括：一控制装置，它根据接收一输入信号给出电能；一对横向双扩散金属-氧化物-半导体场效应晶体管(LDMOSFET)，所述晶体管各自的栅极共同连接成接收用以驱动的所述电能，各自的源极相互连接，各自的漏极分别连接到所述输出端；至少在一块导电材料的支撑板上安装着所述的晶体管；每一所述的晶体管包括：一层有顶面和底面的第一导电类型的硅层，一所述第一导电类型的漏区，它扩散在所述硅层顶面内以确定晶体管的所述漏极；一第二导电类型的阱区，它以与所述漏区横向间隔的关系扩散在所述硅层内；一第一导电类型的源区，它扩散在所述阱区内沿着所述硅层顶面确定在所述源区和所面对的一所述阱区边缘之间伸展的一沟道，所述源区确定晶体管的所述源极；一设在所述漏区上并与其电连接的漏电极；一与一导电材料的栅层电连接的栅电极，所述栅层经一层介质层设在所述沟道的上面以确定所述的栅极；以及一设在所述源区上并与其电连接的源电极；其特征在于：每一个所述晶体管是绝缘体上硅薄膜的结构，它包括一块硅衬底、一层形成在所述硅衬底上的埋入的氧化层、以及形成在所述埋入的氧化层上的所述的硅层，所述的硅衬底被安装在所述的支撑板上，而且其中所述的阱区伸展在所述硅层的全部深度并有一与所述埋入的氧化层邻接的底部，绝缘柱从所述埋入的氧化层通过所述漏区的中心延伸，伸向所述硅层的顶面，以便在围绕所述绝缘柱的环行形状中露出所述漏区，所述漏电极利用与环行形状的所述漏区电连接的漏电极的外围部分在所述绝缘柱上延伸。
由于阱区在硅层的全部深度上扩散，使其底部靠着埋入的氧化层，第一导电类型的阱区只是在邻近沟道的一小部分处与第二导电类型的硅层形成P-N界面。也就是说，只有横向面对漏区的一段阱区侧边形成P-N界面。由于这样缩小了P-N界面而且还由于埋入的氧化层比硅层表现有很低的电容，因而它就有可能为缩小非通导条件下的继电器输出电容而大量降低漏-源电容。缩小P-N界面面积还能减少输出端非导通条件下的泄漏电流。而且，SOI结构能为在支撑板上安装LDMOSFET确保充分的适应性，按照特定的需要，既可以将漏极和源极中的一个与支撑板电连接也可以是电绝缘。
使源区和漏区中的一个构建成在硅层平面内包围着另外一个。这种包围设计能使源区在硅层平面内的一延伸线上面对漏区，从而缩小了继电器输出端之间的开态电阻。于是，继电器就能享有低输出电容和低开态电阻的优化组合。尽管存在着开态电阻愈小输出电容就变大的事实关系，当要求将开态电阻降至一可接收的范围时，上述缩小P-N界面面积的结构对于缩小输出电容仍是很有效的。最好是将源区构建成包围漏区。
此外，本发明注视着减小由于有埋入的氧化层而在源和漏之间或是在栅和源之间建立起来的一附加电容的效应，特别是当利用单块支撑板安装一对LDMOSFET使它们的源极电连接时或是当利用两块分开的支撑板各安装LDMOSFET使漏极与继电器的输出端互连时就更要予以重视。为了便于判明本发明的几项优点，引进了“原始漏-源电容”和“次生漏-源电容”两词。原始漏-源电容基本上是用于表示建立在漏区和源区之间的一部分硅层上的电容，而次生漏-源电容则为由源区沿垂直途径经埋入的氧化层至与漏极保持同一电位的支撑板或是由漏区至与源极同一电位的支撑板所建立起来的一附加电容。
硅层有一设于阱区横向外面的周边区，并通过阱区与漏区电隔离。最好是将周边区和漏区电连接共同接到支撑板上。这样周边区包围着阱区能够保持与漏区处于同一电位，从而消除了在周边区和硅衬底之间经埋入的氧化层建立一电容的额外途径。否则，此额外途径就会不可避免地在阱区底部和支撑板之间经埋入的氧化层建立起一个与次生漏-源电源并联的电容，从而在源和漏之间引起过大的并联电容。
此外，在周边区内可以形成一介质材料的隔环以使阱区与周边区电隔离的方式紧围住阱区。这样，就有可能避免在阱区和周边区之间建立起过高的电容，从而缩小了当漏极和周边区与支撑板电连接时的整个漏-源电容。
此外，可以在阱区外面的硅层内以相互分隔的关系至少扩散有一块第二导电类型的隔岛。源电极和栅电极中至少有一个以与相应的源和沟道中的一个分隔的关系伸展在隔岛上，用以形成与一互补电路单元连线的布线焊点。采用这种在隔岛上设置焊线点的设计，还可以减少由于提供焊点以及相应减小整个源-漏或栅-漏电容而产生的附加电容。
另一种办法是，可以在阱区内至少扩散有一个第一导电类型的隔岛，以与源区电隔离的关系在硅层的全部深度伸展。源电极和栅电极中至少有一个以与相应源和沟道中的一个相互隔开的关系伸展在隔区上面，用以形成与一互补电路单元连线的焊线点，实现按以上讨论的方式缩小整个源-漏或栅-漏电容的目的。
当将漏区构建成包围阱区并用支撑板使两个LDMOSFET的源电连接时，最好将漏区外面的周边区与支撑板电连接。这样，漏区外面的周边区就不能经埋入的氧化层的相应部分建立附加的电容，从而降低了源-漏电容。在此结构中，还可用一介质隔环紧围着漏区。隔环形成在硅层内，使漏区与硅层的周边区隔离，以便在缩小的源-漏电容之外在漏和源之间产生最佳的介电强度。
当源或漏与支撑板电连接时，为了通过在源或漏区与支撑板之间插入空腔或沟槽以进一步降低漏-源电容，硅衬底最好形成有与相应漏区或阱区伸展的空腔或沟槽。
还有一种型式是，形成一电绝缘柱从埋入的氧化层起经漏区的中心伸展至硅层的顶面突起，以这种方式露出围绕绝缘柱的环状漏区。将所关联的漏电极安排成伸展在绝缘柱上并以漏电极的周边区与环状漏区电连接。绝缘柱和漏电极的组合能够有效地降低漏-源电容同时为漏电极确保了足够的尺寸。
硅衬底可以包括一对相反导电型号的半导体层，它们在相互间的P-N界面处建立一层耗尽层。所形成的耗尽层产生一附加的电容，它对埋入氧化层的次生漏-源电容增加串连的电容连接，从而减小了所有的漏-源电容。
为了进一步降低次生的漏-源电容，本发明的继电器还可以包括一层与所述埋入的氧化层相对的在硅衬底的底而上的介质层。
在本发明的另一型式中，打算将两个LDMOSFET集成在单个器件结构中。在此结构中，在单层硅层中的整个深度上形成阱区，使在其中形成有一对横向隔离的第一和第二有源区。一对第一和第二源区在阱区内扩散并分别包围着第一和第二有源区并自第一和第二源区起确定伸展在阱区内的第一和第二沟道，以分别面对第一和第二有源区的边界。在第一和第二有源区内分别扩散第一和第二漏区，使得通过阱区使其相互隔离。第一和第二漏电极按其电连接关系分别设在第一和第二漏区上。至少有一个栅电极与第一和第二栅层电连接，这些栅层分别经介电层设在第一和第二沟道上并分别确定两个LDMOSFET的第一和第二栅极。设置一共用的源电极跨接在第一和第二源区上并与其电连接。硅衬底经埋入氧化层承载硅层安装在支撑架上，并使输出端分别与第一和第二漏极电连接。这样，两个LDMOSFET就能以单一的器件结构实现，并能方便地组装成固态继电器，同时保持着最小的漏-源电容。
在此共用单层硅层实现两个LDMOSFET的结构中，支撑板可以与共用的源极以及与第一和第二漏极电隔离，而输出端则与支撑板分开形成以使其与第一和第二漏极电连接。
附图说明
从以下结合附图所作的实施例说明中将会更加明白本发明的这些和其它目的和优点。
图1为本发明固态继电器的电路图；
图2为绘示以上本发明第一实施例继电器的连接的典型设计示意图；
图3为在第一实施例的继电器中利用的一个SOI-LDMOSFET的部分垂直剖面图；
图4绘示图3的SOI-MOSFET的阱、源、漏区的平面设计；
图5绘示以上SOI-MOSFET的栅、漏、和源电极及其分别焊接点的平面设计；
图6为绘示本发明第二实施例以上继电器的电连接的典型设计示意图；
图7为在第二实施例的继电器中利用的一个SOI-LDMOSFET的部分垂直剖面图；
图8绘示图7的SOI-MOSFET的阱、源、漏区的平面设计；
图9绘示以上SOI-MOSFET的栅、漏、和源电极及其分别焊接点的平面设计；
图10为在本发明第三实施例的继电器中利用的一个SOI-LDMOSFET的部分垂直剖面图；
图11绘示图10的SOI-MOSFET的阱、源、漏区的平面设计；
图12绘示以上SOI-MOSFET的栅、漏、和源电极及其分别焊接点的平面设计；
图13为在本发明第四实施例的继电器中利用的一个SOI-LDMOSFET的部分垂直剖面图；
图14绘示图13的SOI-MOSFET的阱、源、漏区的平面设计；
图15绘示以上SOI-MOSFET的栅、漏、和源电极及其分别焊接点的平面设计。
具体实施方式
如图1中所示，本发明的固态继电器包括一对LDMOSFET(横向双扩散金属-氧化物-半导体场效应晶体管)T串联连接在输出端2之间，输出端2用于跨接在要由继电器控制的一负载上。LDMOSFET(此后有时简称为FET)受一控制部件3驱动转换开和关，控制部件3根据接收到的一输入信号给出一个电能。控制部件3的组成包括一个连接成根据输入端1之间导通而关断发光的发光二极管4、一个根据从发光二极管4接收的一光信号产生光生电压的光生伏特电池5、以及一个在电路中连接成由光生伏特电压建立控制电压并将此控制电压加到分别的FET的栅上的驱动器6。控制部件3设置成单块芯片8的形式，它和FET的芯片一起装在图2中所示的一块导电材料的支撑板9上。
两个FETT的源S经支撑板9相互连接，而两个FET的栅G则共同与控制部件3的相应电极连接。两个FET的漏D分别与支撑板9分开形成的输出端2相连。另一种方法是，可以将两个FET和控制部件3的芯片8分别安装在分开的支撑板上。两个FET和控制部件3的芯片与所关联的一个或多个支撑板一起封入模制的继电器壳中。
现在参阅图3和4，那里示出了设置在一SOI(绝缘体上的硅)结构中的LDMOSFET，SOI结构包括一层硅层10、一层埋入的SiO2氧化层20以及一块硅衬底30。硅层10属于第一导电类型，一般为N型，其中的阱区11属于第二导电类型即P型扩散成围绕着硅层10的周边伸展。阱区11沿硅层的全部深度伸展直至使其底面达到埋入的氧化层20。向阱区11顶面扩散的是一N型源区12，它以闭合环的形式伸展确定FET的源并在源区12和面对的阱区11内周边之间确定一环形沟道13。在阱区11的一限定范围内的硅层10的顶面中央扩散一N型漏区14，以横向相互间隔的关系确定FET的漏。经硅层10并经漏区14中央伸展的是一绝缘柱15，它是用LOCOS(硅的局部氧化)技术形成的并有其从硅层10的顶面上部突起的顶部和与埋入氧化层20集合一体的底部。
硅层10的顶面复盖-层SiO2场氧化层40，它有一层掺杂多晶硅的栅层41、一层铝制的栅电极43、一层铝制的源电极42、以及一层铝制的漏电极44。栅层41伸展在沟道13上，以相互间隔的关系确定FET的栅并与栅电极44连接。源电极42穿透场氧化层40达到硅层10顶部上的源区12和阱区11上的搭接部位，而漏电极44则在绝缘柱15上穿透硅层10与围绕绝缘柱15的一环形漏区接触。如图5中所示，源电极42是在水平面内的一闭合环的构形并设有一方形焊点52用以与支撑板9连线。其上形成的漏电极44有一似方状的焊点54用以与相应的输出端2连线。栅电极43由环状栅层41向外横向伸展达到一伸展部位，在其上形成与控制部件3的相应元件连线的类似焊点53。
返回到图3，硅衬底30包含一层N型的上层31和一层P型的下层32，它们经一层介质层35设在支撑板9上，介质层35可以是与硅衬底30形成于一体的氧化层、氮化层或未掺杂的硅层，也可以是一层分开形成的介质层。上层31包括一空腔33，它形成在与埋入氧化层20相接的界面上，以与硅层10从漏区14至阱区11的内周边范围的部位相对的关系伸展。
在上述结构中，原始漏一源电容建立在漏源区14和阱区11之间的横向路径中。然而，由于阱区11的底部与埋入的氧化层直接接触，不像经一硅层10的部位与埋入氧化层接触那样具有固有的大于氧化层20的特定电容。因而建立在原始垂直路径中的原始漏-源电容被大量降低。
利用支撑板9与源电连接的结果是，在沿着从漏区14或漏极44经埋入氧化层20、硅衬底30和介质层35的相应部位至支撑板9的垂直路径建立起一个次生漏-源电容。尽管由于有小的特定电容的埋入氧化层20的插入，次生电容要比原始电容小，但次生电容是与原始电容并联连接的，它增加了并联的电容总量。因而，这就要求尽可能地降低次生电容。通过设置绝缘柱15、介质层35、硅衬底30中的P-N结、以及硅衬底30中的空腔33能够降低次生电容。首先，绝缘柱15能够缩小与支撑板9引起次生电容的漏区14的有效面积，同时在漏电极44上又确保有足够的尺寸设置焊点54，从而降低了沿垂直路径建立的次生电容。其次，插入介质层35将会增加与埋入氧化层电容的电容性串联连接的电容，从而降低了次生电容。第三，形成在硅衬底30中即上层31和下层32之间的P-N结将建立一耗尽层，它建立与埋入氧化层20的电容串联连接的电容，降低了次生电容。此外，在埋入氧化层20与硅衬底30之间的界面处的空腔33能够增加与埋入氧化层20的电容串联连接的电容，降低了次生电容。因而，能使所有的漏-源电容降低得很多，从而使继电器的输出端2之间的输出电容降至最低。要注意到在这种连接中尽管最好设置绝缘柱15、介质层35、硅衬底30中的P-N结、以及硅衬底30中的空腔33使次生漏-源电容以致所有的漏-源电容得到降低，但没有任何这类部件也能充分地降低所有的漏-源电容。
图6绘示本发明第二实施例的一固态继电器，其中的两个MOSFETT各安装在一块分开的导电材料的支撑板9A上，而其栅极则与安装在一分开的框架7上的类似的控制部件芯片3A相连。每-FET的漏极与每一和一输出端2A一起形成为一整体部件的支撑板9A电连接。
如图7和8所示，FET还是SOI的结构，有一层N型硅层10A、一层埋入的氧化层20A、以及一块硅衬底30A。在硅层10A内的整个深度扩散一闭合环状构形的P型阱区11A，留下周围的边缘隔离区16。在阱区11A的顶面中以象P型阱区11A那样的方式扩散一闭合环构形的N型源区12A，以确定FET的源极而且还确定源区12A与所面对的阱区11A的内边缘之间的一沟道13A。在阱区11A的一限定范围内的硅层10A顶面中央扩散一N型漏区14A，以确定FET的漏极。紧围着阱区11A伸展的是一层用LOCOS法形成的二氧化硅介质分隔环17，它有达到埋入的氧化硅层20A的底部。分隔环17在硅层10A的上面突起并与复盖硅层10A顶面的场氧化层40A合并。场氧化层40A包含一层掺杂多晶硅的栅层41A，它以相间隔的关系在沟道13A上沿一闭合环伸展，以确定FET的栅极。栅层41A与栅电极43A电连接。漏电极44A和源电极42A是穿透场氧化层40A形成的，用以与漏区14A及源区12A和阱区11A的搭接部位分别进行电连接。源电极42A与栅电极43A在分隔环17上横向伸展，确定如图9中所示用以与所联结的电路元件连线的方块构形的分别焊点52A和53A。一个似方块的焊点54A形成在漏电极44A上的中央，用以与输出端连线。
在此实施例中，周边区16和漏极一起与支撑板9A电连接，以与漏极保持在同一电位上。采用这种设计，与周边区16对应的埋入氧化层20A不会产生任何增加电容的作用，这种增加是由与原始漏-源电容以及还与沿阱区11A的底部和支撑板9A的垂直路径形成的次生电容并联有电容引起的。按此意义，所有的漏-源电容即使在有周边区16的情况下也能降低得很多。此外，分隔环17能够延伸从阱区11A至周边16的水平路径，从而减少了它们之间的电容，因而用于缩小所有的漏-源电容。
还有在此实施例中，硅衬底30A由经一层介质层35A设于支撑板9A上的一层N型上层31A和一层P型下层32A组成。上层31A包括一沿水平平面环状构形的空腔33A，它形成在与埋入氧化层邻接的界面处，以与复盖阱区11A和分隔环17的硅层10A的部位相对的关系水平伸展。参照第一实施例的说明，空腔33A、层31A和32A之间的P-N界面、以及介质层35A以同一方式起着降低所有漏-源电容的作用。
图10至12绘示本发明第三实施例SOI-LDMOSFET的另一种结构。所绘示结构的FET用于图6中所示的电路结构，并包括一层N型硅层10B、埋入的氧化层20B、以及一块硅衬底30B。在硅层10B中的全部深度上扩散一闭合环状构形的P型阱区11B，留下周围的边缘隔离区16B。在阱区11B的顶面内扩散一闭合环状的P型源区12B，在源区12B与所面对的阱区11B的内周边之间确定一沟道13B。在阱区11B的一限定范围内的硅层10B顶面内的中央扩散一N型漏区14B。在周边区16B中局部扩散的是一对P型岛18，它们伸展到硅层10B的全部深度，并在一水平面内安排成相互完全对立的位置。硅层10B的顶面被设有掺杂多晶硅栅层41B的一层场氧化层40A复盖住，掺杂多晶硅栅层41B以分隔的关系伸展在沟道13B上并与栅电极43B电连接。漏电极44B和源电极42B是穿透场氧化层40B形成的，用以与漏区14B以及源区12B和阱区11B的一搭接部位分别进行电连接。源电极42B和栅电极43B在P型岛18上横向伸展，如图12中所示，确定在那里的分别的方块结构形成的焊点52B和53B，用以与所关联的电路元件进行连线。在漏电极44B上的中央形成一方块状焊点54B，用于与输出端连接。
同样在此实施例中，周边区16B和漏极一起与支撑板9B电连接，以保持与漏极处于同一电平，用以根据第二实施例中说明的同一原因降低所有的漏-源电容。在源和栅电极42B和43B的焊点52B和53B的下面设置岛18，每一岛将与周边区16B的P-N结产生的与由焊点引起的场氧化层40B的电容串联连接的电容增加到自身的电容上，从而降低了建立在各焊点至周边区16B之间的电容。否则，场氧化层40B的电容就会单独与不可避免的漏-源和漏-栅电容并联连接，以致最终增加了所有的漏-源和栅-漏电容。
N型硅衬底30B在一水平平而内形成有一一环状的沟槽34，它沿硅衬底30B的整个深度伸展。沟槽34复盖从阱区11B向外至岛18B的横向范围的硅层10B的部位，这样，就在支撑板9B和阱区11B以及焊点52B和53B之间形成一电容性元件。所形成的电容与包括由设置焊点所引起的电容在内的不可避免的漏-源和栅-漏电容串联连接，从而降低了所有的漏-源和栅-漏电容。在支撑板9B上设有一层类似的介质层35B，用于前述实施例中所讨论的同一目的。
代替在硅层10B中设岛18，同样有可能在阱区11B内设置类似的N型岛，以与源区12B横向隔离的关系降低由于设置源和栅电极焊点而产生的漏-源和栅-漏电容。
要注意到，尽管在以上所绘示的实施例公开的构形中漏区是被阱区包围，但它同样也有可能提供一种构形，其中在硅层内中心处形成一类似的阱区并被一类似的漏区包围。在这种修改中，围绕漏区的周边区与源区一起与类似的支撑板电连接。同样，可以围绕源区形成一类似的分隔环使漏区与周边区电隔离。
参阅图13至15，那里示出了本发明第四实施例的一个固态继电容。继电器包括集成在一SOI结构的单个器件中的一对LDMOSFET，SOI结构由一层N型硅层100、一层埋入的氧化层200、以及一块硅衬底300组成。单个器件安装在一导电材料的支撑板9上，并有一层介质层350插入其间。在硅层100内的全部深度上扩散一P型阱区111，以形成一对横向隔离的椭圆构形的第一和第二有源区101和102。分别围绕第一和第二有源区101和102形成的是N型第一和第二源区121和122，它们是闭合的环状构形并扩散在阱区111的顶面内以确定FET分别的源。第一和第二源区121和122还在分别的源区与朝内对面的第一和第二有源区101和102的周边之间的阱区内确定闭合环的第一和第二沟道131和132。第一和第二N型漏区141和142则在第一和第二有源区101和102内分别扩散在硅层100的顶面中，以与阱区111横向相隔的关系确定FET分别的漏。用LOCOS技术形成第一和第二绝缘柱151和152，它们由埋入的氧化层200分别经过第一和第二漏区141和142的中央在硅层100上面突起。
硅层100的顶面复盖着一层SiO2场氧化层400，它有一对掺杂多晶硅的第一和第二栅层411和412、一栅电极431、一源电极421、以及一漏电极441。第一和第二栅层411和412分别以隔开的关系伸展在第一和第二沟道131和132上以确定FET个别的栅并共同与栅电极431相连。源电极421穿透场氧化层400达到硅层100上的一搭接部位，该搭接部位在第一和第二源区121和122上并经阱区111形成在其间用以连接两FET的源。第一和第二漏电极441和442在绝缘柱151和152上穿透硅层100与围绕着绝缘柱体的第一和第二漏区141和142的环形接触。如图15中所示，栅电极431设有一焊线点531用于与所关联的电路元件即如图1中所示的控制部件连线。第一和第二漏电极441和442分别设有焊线点541和542，用于与继电器的输出端连线。源电极421则设有一单个焊点521用于与支撑板9连线。源就不必与支撑板9相连。
在以上的结构中，阱区111在硅层100的全部深度伸展，使得在埋入的氧化层200上形成两个隔离的有源区101和102，使其能以单个的SOI结构形成两个FET，而且此外由于减少了阱区111横向面对漏区141、142的面积以及还由于埋入氧化层200比硅层100有更低的专用电容而降低了漏-源电容。
尽管埋入的氧化层200有低的专用感应电容，特别当源与支撑板9电连接时它将会产生一次生电容。此次生电容基本上建立在从漏区141与142经埋入的氧化层200至支撑板9的垂直路径中，它与基本上建立在从漏区至阱区的横向路径中的原始漏-源电容并联连接而使电容增加。为了还要尽可能大量消除次生电容的影响，使N型硅衬底形成有一对横向间隔沟槽341和342，并经介质层350置于支撑板9上。
每一沟槽341和342在硅衬底300的全部深度伸展，并在水平平面中有一椭圆形构形，使其包括由每一第一和第二源区121、122界定的并包含第一和第二漏区141、142的一硅层100的部位。沟槽341和342以及电介质层350产生的分别的电容以串联连接与埋入氧化层的漏-源电容相加，使整个次生漏-源电容下降，从而使所有漏-源电容以至输出电容降至最低。
要注意在这种连接中支撑板可以与每一FET的源以及漏电隔离，同时又保证了大量降低漏-源电容。在这一修改中，就不要求硅衬底有沟槽或空腔，甚至连介质层350也可以取消。
此外，要在本发明的概念范围内组合各个实施例的特征，使经埋入氧化层建立的次生源-漏电容降低。这些特征包括经漏区14设置绝缘柱15(典型地示于图3中)、在支撑板9和硅衬底30之间插入介质层35(典型地示于图3中)、设置空腔33或沟槽34(典型地示于图3和10中)、以及设置相反型号的层31和32作为在其间形成P-N结的硅衬底30(典型地示于图3中)。

Claims (24)

1、一种有一对与受控制的负载相连接的输出端的固态继电器，它包括：
一控制装置(3)，它根据接收一输入信号给出电能；
一对横向双扩散金属-氧化物-半导体场效应晶体管(LDMOSFET)，所述晶体管各自的栅极共同连接成接收用以驱动的所述电能，各自的源极相互连接，各自的漏极分别连接到所述输出端(2)；
至少在一块导电材料的支撑板(9；9A；9B)上安装着所述的晶体管；
每一所述的晶体管包括：
一层有顶面和底面的第一导电类型的硅层(10；10A；10B，100)，
一所述第一导电类型的漏区(14；14A；14B；141，142)，它扩散在所述硅层顶面内以确定晶体管的所述漏极；
一第二导电类型的阱区(11；11A；11B；111，它以与所述漏区横向间隔的关系扩散在所述硅层内；
一第一导电类型的源区(12；12A；12B；121，122)，它扩散在所述阱区内沿着所述硅层顶面确定在所述源区和所面对的一所述阱区边缘之间伸展的一沟道，所述源区确定晶体管的所述源极；
一设在所述漏区上并与其电连接的漏电极(44；44A；44B；441，442)；
一与一导电材料的栅层(41；41A；41B；411，412)电连接的栅电极，所述栅层经一层介质层设在所述沟道的上面以确定所述的栅极；以及
一设在所述源区上并与其电连接的源电极(42；42A；42B；421)；
其特征在于：
每一个所述晶体管是绝缘体上硅薄膜的结构，它包括一块硅衬底(30；30A；30B，300)、一层形成在所述硅衬底上的埋入的氧化层(20；20A；20B；200)、以及形成在所述埋入的氧化层上的所述的硅层(10；10A；10B；100)，所述的硅衬底被安装在所述的支撑板上，而且其中所述的阱区伸展在所述硅层的全部深度并有一与所述埋入的氧化层邻接的底部，
绝缘柱(15；151；152)从所述埋入的氧化层(20；200)通过所述漏区(14；141；142)的中心延伸，伸向所述硅层的顶面，以便在围绕所述绝缘柱的环行形状中露出所述漏区，所述漏电极利用与环行形状的所述漏区电连接的漏电极的外围部分在所述绝缘柱上延伸。
2、按照权利要求1所述的固态继电器，其特征在于，所述源区和所述漏区中的一个构建成在所述硅层的一平面内包围着所述源区和所述漏区中的另一个。
3、按照权利要求2所述的固态继电器，其特征在于，所述源区构建成包围着所述的漏区。
4、按照权利要求3所述的固态继电器，其特征在于，所述硅层形成有位于所述阱区之外并经所述阱区与所述漏区隔离的一周边区(16；16B)，所述周边区与所述漏区被共同连接到所述支撑板上。
5、按照权利要求3所述的固态继电器，其特征在于，有一介质材料的分隔环(17)紧密围绕所述阱区，所述分隔环形成在所述硅层内使所述阱区与所述硅层的一周边区隔离，所述周边区与所述漏区被共同连接到所述支撑板上。
6、按照权利要求5所述的固态继电器，其特征在于，所述源电极和所述栅电极中至少有一个从所述阱区上面横向伸展在所述分隔环(17)的所述上部的上面。
7、按照权利要求4所述的固态继电器，其特征在于，至少有一个第二导电类型的分隔岛(18)以与所述阱区相间隔的关系在所述阱区外面的所述硅层内横向地扩散，所述源电极和所述栅电极中至少有一个伸展在隔开相应的所述源和所述沟道中的一个的所述至少一个分隔岛上面，在那里确定一个与互补电路的元件连接的连线焊点(52B；53B)。
8、按照权利要求4所述的固态继电器，其特征在于，在所述阱区内扩散有一第一导电类型的分隔岛(18)以与所述源区电隔离的关系伸展到所述硅层的全部深度，在所述源电极和所述栅电极中至少有一个伸展在隔开相应的所述源和所述沟道中的一个的所述分隔岛上面，在那里确定一个与互补电路的元件连接的连线焊点。
9、按照权利要求2所述的固态继电器，其特征在于，所述源区和所述漏区中的一个围绕着所述源区和所述漏区中的另一个是将导电材料的所述支撑板电连接成使所述支撑板具有与所述阱区和所述漏区之一的同一电位。
10、按照权利要求2所述的固态继电器，其特征在于，所述漏区构建成包围所述阱区。
11、按照权利要求10所述的固态继电器，其特征在于，所述硅层形成有一位于所述漏区外面的周边区(16；16B)，所述周边区与所述源区共同电连接至所述支撑板。
12、按照权利要求10所述的固态继电器，其特征在于，有一介质分隔环(17)紧密围绕着所述的漏区，所述分隔环形成在所述硅层中使所述漏区与所述硅层的一周边区隔离，所述周边区与所述源区共同电连接至所述支撑板。
13、按照权利要求1所述的固态继电器，其特征在于，所述源区(12)与所述支撑板(9)电连接。
14、按照权利要求13所述的固态继电器，其特征在于，所述的硅衬底(30)形成有一伸展在与所述埋入的氧化层相接的界面处并有覆盖所述漏区的宽度的空腔(33)。
15、按照权利要求13所述的固态继电器，其特征在于，所述的硅衬底(30B)形成有一由所述埋入的氧化层确定底部并有覆盖所述漏区的宽度的沟槽(34)。
16、按照权利要求7所述的固态继电器，其特征在于，所述的支撑板是与所述的输出端分开形成的。
17、按照权利要求1所述的固态继电器，其特征在于，所述漏区(14A；14B)是与所述支撑板(9A；9B)电连接的。
18、按照权利要求17所述的固态继电器，其特征在于，所述硅衬底(30A)形成有一伸展在与所述埋入的氧化层(20A)相接的界面处并有复盖所述源的宽度的空腔(33A)。
19、按照权利要求17所述的固态继电器，其特征在于，所述硅衬底(300)形成有一由所述埋入的氧化层(200)确定底部并有复盖所述源区(121、122)的宽度的沟槽(341，342)。
20、按照权利要求17所述的固态继电器，其特征在于，所述支撑板(9A)形成有作为其整体件的所述输出端(2A)。
21、按照权利要求1所述的固态继电器，其特征在于，所述硅衬底(30；30A)包括一对导电型号相反的半导体层(31，32；31A，32A)。
22、按照权利要求1所述的固态继电器，其特征在于，其中有一层介质层(35；35A；35B；350)形成在所述埋入的氧化层对面的硅衬底的底部上。
23、按照权利要求1所述的固态继电器，其特征在于，所述阱区(111)形成在所述硅层内的全部深度上，使在阱区中形成有一对横向隔离的第一和第二有源区(101，102)，围绕着它们有一对第一和第二源区(121，122)分别形成在所述阱区内，并且有一对第一和第二漏区分别形成在所述第一和第二有源区内，以实现单一器件结构中的两个所述晶体管，
所述第一和第二源区(121，122)分别扩散在所述阱区(111)内，使其相互间横向隔开，并确定第一和第二沟道(131，132)各沿所述硅层的顶面在每一所述第一和第二源区至所面对的所述第一和第二有源区中相应一个的每一边缘之间伸展，所述第一和第二源区分别确定两个晶体管的第一和第二源极；
所述第一和第二漏区(141，142)分别扩散在所述第一和第二有源区内以所述阱区使其相互隔离并分别确定两个所述晶体管的漏极；
第一和第二漏电极(441，442)以电连接的关系分别设置在所述第一和第二漏区上；
至少有一个栅电极(431)与第一和第二栅层(411，412)电连接，第一和第二栅层经介质层分别设置在所述第一和第二沟道上面并分别确定所述两个晶体管的第一和第二栅极；
一共用的源电极(421)搭接在所述第一和第二源区上面开使其电连接；
所述第一漏极(141)与所述第一栅极(411)及所述第一源极(121)协同形成所述晶体管中的一个，而所述第二漏极(142)与所述第二栅极(412)及所述第二源极(122)则协同形成所述晶体管中的另一个，以及
通过所述埋入的氧化层承载所述硅层的所述硅衬底以所述输出端分别与所述第一和第二漏极电连接安装在所述支撑架上。
24、按照权利要求23所述的固态继电器，其特征在于，所述硅衬底与所述第一和第二源极以及所述第一和第二漏极电隔离，所述输出端与所述支撑板分开形成。
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