CN1163480A - 芯片载体及使用它的半导体装置 - Google Patents

芯片载体及使用它的半导体装置 Download PDF

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CN1163480A
CN1163480A CN97103066.9A CN97103066A CN1163480A CN 1163480 A CN1163480 A CN 1163480A CN 97103066 A CN97103066 A CN 97103066A CN 1163480 A CN1163480 A CN 1163480A
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substrate
pressure welding
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CN1085891C (zh
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本胜秀
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Panasonic Holdings Corp
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Abstract

载体基板由用芳香族聚酰胺纤维作为加强材料形成的柔性绝缘基板、在上述柔性绝缘基板的一侧表面上形成的第1连接压焊区、以及在上述柔性绝缘基板的另一侧表面上形成的第2连接压焊区构成,上述第1连接压焊区和上述第2连接压焊区通过在上述柔性绝缘基板上开设的通路孔进行电气连接。而且,由采用热胀系数比上述载体基板的热胀系数大的材料形成的周边加强构件和上述载体基板构成芯片载体,LSI芯片被安装在该芯片载体的凹部。

Description

芯片载体及使用它的半导体装置
本发明涉及半导体装置,详细地说,涉及安装半导体芯片(以下也称"LSI芯片")用的载体基板及将半导体芯片装在它上面的半导体装置。
当前,半导体封装体的主流是从封装体的四个侧面引出输入输出引线的塑料QFP(四方扁平封装体)。该塑料QFP伴随与各个领域中的电子设备的多功能化、高性能化对应的LSI的大规模化的进展,其输入输出端子数增加,QFP的封装体形状也变大。因此,为了防止该封装体形状的大型化,在推进半导体芯片的设计原则的超精细化的同时,通过使其引线间距变窄,来适应多种电子设备的小型化。
可是,如果LSI的规模超过400个插脚时,由于焊接量大等问题,使得窄间距化受到限制,不能充分地适应小型化等。
作为将半导体封装体安装在主印刷电路板上时的问题是两者所具有的热胀系数不同。将这种具有不同的热胀系数的半导体封装体的许多微细的输入输出引线和印刷电路板上的许多微细的电极端子精确地连接起来是极其困难的。
多插脚化的半导体封装体由于塑料QFP的形状的大型化造成的长引线插脚,使得信号的传送慢,不能进行高速信号处理。
为了解决这种塑料QFP所带有的许多问题,最近采用下述结构代替QFP,即将球状的连接端子呈2维阵列状配置在半导体封装体背面的称为BGA(Ball Grid Array,球格子阵列)的结构或将许多平电极压焊区配置在半导体封装体背面的称为LGA(Land Grid Array,焊接区格子阵列)的结构。
这些BGA及LGA随着载体基板材料的不同而被称为CBGA(陶瓷球格子阵列)、PBGA(塑料球格子阵列)、TBGA(球带格子阵列)、或TLGA(带状焊接区格子阵列)。作为载体基板,PBGA采用由玻璃纤维加强的树脂基板(例如玻璃环氧树脂基板),与其它种类的载体基板相比,价格便宜,开始广泛普及。TBGA或TLGA是在具有通孔的双面柔性载体基板的一面的周边上固定着支撑柔性基板的周边加强构件,将半导体芯片安装在被该周边加强构件包围的凹部,并进行模制处理。在TBGA的情况下,将焊球等设在载体基板的另一面,在TLGA的情况下,不设焊球。
可是,在CBGA的情况下,作为载体基板用的陶瓷价格贵、且其热胀系数比主基板即玻璃环氧树脂的热胀系数小很多,因此存在由热胀系数的不同引起断线等造成连接的可靠性不好的问题。在PBGA的情况下,基板中由于加进了玻璃纤维,所以弯曲变形增大,存在制造时或往主基板上安装时合格率下降的问题。称为TBGA、TLGA的封装体使用价格高的双面柔性基板作为载体基板,虽然具有柔性,但不易保持平面,存在难以进行合格率高的制造的问题。
基于上述情况,现有的BGA及LGA由于价格高带来的问题、以及柔性基板的热胀系数比半导体芯片的热胀系数大很多,所以存在半导体芯片和载体基板的连接及往玻璃环氧树脂主基板上安装时连接的可靠性不好的问题。
本发明就是为了解决这些课题而进行的,目的在于在容易制造的和在各种电子设备中使用的半导体装置中提供一种不会由于LSI芯片和芯片载体、芯片载体和主基板的热胀系数的不同而引起的破坏或断线等的连接可靠性好的芯片载体及使用它的半导体装置。
为了达到上述目的,本发明的芯片载体备有载体基板和周边加强构件,上述载体基板由用芳香族聚酰胺纤维作为加强材料形成的柔性绝缘基板、在上述柔性绝缘基板的一侧表面上形成的第1连接压焊区、以及在上述柔性绝缘基板的另一侧表面上形成的第2连接压焊区构成,上述第1连接压焊区和上述第2连接压焊区通过在上述柔性绝缘基板上开设的通路孔进行电气连接,上述周边加强构件采用热胀系数比上述载体基板的热胀系数大的材料形成,且设置在上述载体基板的外周部。如果采用本发明的芯片载体,则在安装时或实验时等情况下即使被放置在高温状态下,也不会发生由上述加强构件加在上述载体基板上的张力引起的变形,上述载体基板能保持平面状态。因此,能提高安装时的合格率。另外,由于载体基板使用芳香族聚酰胺纤维作为加强材料,所以热胀系数不象现有的采用聚酰亚胺薄膜的柔性基板和硅半导体芯片之间相差那么大,所以即使在可靠性试验时进行的热循环等也几乎没引起破坏。再者,由于上述载体基板的热胀系数比用玻璃环氧树脂构成的主基板的热胀系数小,而且上述载体基板比主基板具有更大的挠性,所以焊接的可靠性好。就是说,在高温时载体基板及主基板中的树脂变软,所以应力不易加在焊接部分。另外,在低温时由于载体基板的热胀系数比主基板的小,因此主基板一侧收缩得大,而载体基板变得松弛。这样一来,应力仍然不易加在焊接部分。
在上述本发明的芯片载体中,上述周边加强构件最好由满足上述条件的金属构成。如果采用这种优选例,则将半导体芯片装在芯片载体上后安装到电子设备中工作时,能有效地放散由半导体芯片产生的热。
在上述本发明的芯片载体中,上述周边加强构件最好呈锯齿状。如果采用这种优选例,则能有效地放散由半导体芯片产生的热。
在上述本发明的芯片载体中,上述载体基板最好是上述通路孔的开口端不在上述柔性绝缘基板的表面上露出的内通路树脂多层基板。如果采用这种优选例,则与使用通路孔的柔性基板相比,能提高连接压焊区排列设计的自由度。
在上述本发明的芯片载体中,上述第1连接压焊区和上述第2连接压焊区最好按不同的图形形成。如果采用这种优选例,则能对应于主印刷电路板上的布线图形自由地设定上述第2连接压焊区的位置,进行高密度布线时很有效。
在上述本发明的芯片载体中,在上述第2连接压焊区上最好备有焊球。这种优选例中的焊球是进行电气连接用的软钎焊焊球等。如果采用这种优选例,则容易焊接。
本发明的半导体装置备有载体基板、周边加强构件和半导体芯片,上述载体基板由用芳香族聚酰胺纤维作为加强材料形成的柔性绝缘基板、在上述柔性绝缘基板的一侧表面上形成的第1连接压焊区、以及在上述柔性绝缘基板的另一侧表面上形成的第2连接压焊区构成,上述第1连接压焊区和上述第2连接压焊区通过在上述柔性绝缘基板上开设的通路孔进行电气连接,上述周边加强构件采用热胀系数比上述载体基板的热胀系数大的材料形成,且设置在上述载体基板的外周部,上述半导体芯片被安装在由上述载体基板和上述周边加强构件形成的凹部。如果采用本发明的半导体装置,则将上述半导体装置安装在主基板上时即使处于高温下,但由于上述周边加强构件的热胀系数比上述载体基板的热胀系数大,所以拉伸应力作用于载体基板上而能保持平面状态,因而芯片载体不会发生弯曲。因此,能有效地防止由于热胀系数的差异引起的半导体装置的破坏或连接不良等。
在上述本发明的半导体装置中,上述周边加强构件最好由满足上述条件的金属构成。如果采用这种优选例,则将半导体芯片装在芯片载体上后安装到电子设备中工作时,能有效地放散由半导体芯片产生的热。另外,在上述本发明的半导体装置中,上述周边加强构件最好呈锯齿状。如果采用这种优选例,则能有效地放散由半导体芯片产生的热。另外,在上述本发明的半导体装置中,上述载体基板最好是上述通路孔的开口端不在上述柔性绝绝基板的表面上露出的内通路树脂多层基板。如果采用这种优选例,则与使用通路孔的柔性基板相比,能提高连接压焊区排列设计的自由度。另外,在上述本发明的半导体装置中,上述第1连接压焊区和上述第2连接压焊区最好按不同的图形形成。如果采用这种优选例,则能对应于主印刷电路板上的布线图形自由地设定上述第2连接压焊区的位置,进行高密度布线时很有效。另外,在上述本发明的半导体装置中,在上述第2连接压焊区上最好备有焊球。这种优选例中的焊球是进行电气连接用的软钎焊球等。如果采用这种优选例,则容易焊接。
在上述本发明的半导体装置中,上述周边加强构件的厚度最好比上述半导体芯片薄。如果采用这种优选例,则上述周边加强构件不限制半导体装置的厚度,因此能使上述半导体装置具有与上述半导体芯片的厚度对应的厚度。
在上述本发明的半导体装置中,上述半导体芯片最好安装成倒装片。如果采用这种优选例,则能使从上述半导体芯片内的元件到封装体的连接压焊区(第2连接压焊区)的距离最短化,可使附属的电容和电感比其它电容和电感小,因此能提高电气特性。
在上述本发明的半导体装置中,上述半导体芯片最好有区阵列型端子电极。如果采用这种优选例,则能提高电气特性。
在上述本发明的半导体装置中,最好在上述半导体芯片的上表面备有散热板,另外,最好将散热板覆盖在上述半导体芯片的上表面及上述芯片载体的周边部。如果采用这种优选例,则能有效地放散半导体装置工作时产生的热,能提高半导体装置和电子设备的可靠性。
图1是本发明的实施形态的芯片载体的断面图。
图2是本发明的实施形态的芯片载体的斜视图。
图3是本发明的实施形态的芯片载体的作为载体基板用的内通路树脂多层基板的断面图。
图4是本发明的第1实施例的半导体装置的断面图。
图5是本发明的第2实施例的半导体装置的断面图。
图6是本发明的第3实施例的半导体装置的断面图。
图7是本发明的第3实施例中使用的周边加强构件的略图。
图8是本发明的第4实施例的半导体装置的断面图。
图9是本发明的第5实施例的半导体装置的断面图。
图10是本发明的第6实施例的半导体装置的断面图。
以下根据附图及实施例说明本发明的实施形态。
图1及图2分别是本发明的实施形态的断面图及斜视图。在图1以及图2中,芯片载体由载体基板108和周边加强构件106构成,载体基板108由将芳香族聚酰胺纤维作为加强材料的柔性绝缘基板101、在柔性绝缘基板101的一侧表面上设的第1连接压焊区102、在另一侧表面上设的第2连接压焊区105、以及埋入了导电体104的通路孔103构成。
作为将芳香族聚酰胺纤维作为加强材料的柔性绝缘基板101,可例举出例如有浸渍了环氧树脂的芳香族聚酰胺纤维的纺织物或非纺织物。第1连接压焊区102和第2连接压焊区105例如由铜箔形成。第1连接压焊区102和第2连接压焊区105利用埋置在通路孔103中的导电体104进行导电性连接。导电体104采用将铜粉混合在环氧树脂中制成的导体。
如上构成的载体基板108已知有内通路树脂多层基板[例如ALIVH(登记商标:ALⅣH松下电器产业(株)制造,参考文献:"电子材料"1995,10月号P50~58)]。
具有口字形的由玻璃环氧树脂(以玻璃纤维作为加强材料且浸渍了环氧树脂的复合体)等形成的周边加强构件106利用粘接剂107安装在载体基板108的周边部。载体基板108和周边加强构件106用粘接剂107粘接起来的状态最好比紧固稍松一些。作为这种用途的粘接剂例如有市售的两面胶带、硅系列或环氧系列的可柔性粘接剂等。
第1连接压焊区102的排列方法与安装在该载体基板108上的半导体芯片的端子电极的排列方法及其连接方法相适应。半导体芯片的端子电极的配置形式为周边型时,在安装下述的倒装片的情况下,第1连接压焊区102的排列形式配置成半导体芯片载体的端子电极的倒装形式。另外,在半导体芯片的端子电极分布在芯片的整个背面的情况下(称为区域压焊型或区域阵列型),仍然倒装,呈阵列状。在用焊丝键合将半导体芯片和载体基板108接合起来的情况下,第1连接压焊区102的排列形式呈包围着半导体芯片的外周的排列形式。
在本实施形态中,周边加强构件106由玻璃环氧树脂形成,其热胀系数为15ppm/℃。由铜箔、芳香族聚酰胺纤维和树脂构成的复合体即载体基板108的热胀系数与铜箔的含铜率有关,在此情况下为6~10ppm/℃。即周边加强构件106的热胀系数设计成比载体基板108的热胀系数大。在这里,周边加强构件的热膨胀系数比载体基板108的热膨胀系数约大3~20ppm/℃是较为理想的,更为理想的是约大5~10ppm/℃。在这样设计的本实施形态中,在高温下用树脂将半导体芯片安装粘接在芯片载体上的情况下,利用作用在载体基板108上的拉伸应力,载体基板108能经常保持平面状态,不变形。因此提高了成品合格率。
如上所述,用芯片载体和半导体芯片构成的半导体装置由于利用周边加强构件106保持平面状态,所以在将该半导体装置安装在主基板上时,也能保持平面性,因此容易安装,而且还能提高安装时的连接可靠性。即使在被焊接在玻璃环氧树脂主基板上后,接合的可靠性也高。在高温下(~200℃)焊接后被接合起来的载体基板和主基板与冷却的同时逐渐收缩,由于载体基板的热胀系数小而成松弛的结果,由于载体基板有柔性,所以经受得住应力的作用。即使在比常温更低的温度下也能保持这种关系。
另一方面,在使用以聚酰亚胺带等为基本材料的载体基板构成的半导体装置的情况下,热胀系数远远大于玻璃环氧树脂(30~40ppm/℃),所以在焊接后冷却时存在很强的张力作用。在低温下有更强的应力作用,冷热循环时接合部会破坏。
在制造图1所示的载体基板时,可以单独制作,而在批量生产时,也可制成带状。另外,周边加强构件的材料能选择的范围很大,例如有金属、陶瓷、树脂等。再者,图1中说明的载体基板是双面2层基板,但本发明不受此限,也可以采用多层基板。
图3表示内通路树脂多层基板的断面放大图。如该图所示,第1连接压焊区102和第2连接压焊区105通过在构成各层的绝缘基板101a、101b、101c上开的孔103(在该通路孔103中填充了导电性糊剂等导电体104a、104b、104c)进行层间连接,在最外层表面上设有通路孔103的开口端不露出的第1连接压焊区102。这时,内通路树脂多层基板(载体基板108)的第1连接压焊区102对应于安装在它上面的LSI芯片的端子电极的图形设置,第2连接压焊区105的图形可以通过内通路多层基板的内层部分的布线图形,对应于主印刷电路板的布线图形设置成各不相同的图形。
在使用上述的内通路多层基板作为载体基板108的情况下,通过在内层布线部设置盖、电源层,能防止电磁辐射和噪声等的影响。另外,使用内通路多层基板,能以更细的间距进行连接,能制作小型的半导体装置。
在以上说明中,说明了使用2层基板及内通路多层基板作为载体基板的情况,但本发明不受此限,也可以使用普通贯通的通孔多层基板。
如上所述,在本实施形态中,构成载体基板时,采用芳香族聚酰胺纤维作为加强材料很重要。虽然其它材料也能满足热胀系数方面的关系,但作为绝对值接近半导体芯片的(硅的)热胀系数的基板材料,将芳香族聚酰胺纤维作为加强材料的载体基板最适合,如上所述,能获得比使用聚酰亚胺薄膜的载体基板更好的结果。
在本实施形态中,如BGA、TBGA、PBGA那样,可将焊球设在安装时的载体基板的主基板侧即第2连接压焊区上。采用这种结构容易焊接。焊球的材质一般为软钎焊球,最近也有使用铜焊球的。
其次,说明使用本实施形态的芯片载体的半导体装置。
图4表示使用本发明的实施形态的芯片载体的半导体装置的第1实施例。在该第1实施例中,使用由芳香族聚酰胺纤维的非纺织物-环氧树脂构成的内通路两面基板(ALIVH)作为构成载体基板108的柔性绝缘基板101。第2连接压焊区105是铜箔,其表面镀Au/Ni。
如图4所示,本实施例是将LSI芯片201安装在图1所示的芯片载体的呈口字形的周边加强构件106的凹部构成半导体装置的实施例。在LSI芯片201的表面上形成保护膜203,在设置于该保护膜的窗口部分形成由铝薄膜构成的端子电极202。然后在端子电极202上利用焊丝键合装置形成凸点204。使LSI芯片朝下,使端子电极和载体基板的第1连接压焊区的位置重合,夹入导电性粘接剂206安装在载体基板上。在120℃的温度下使导电性粘接剂固化,使密封材料205流入载体基板和半导体芯片之间,使其在150℃的温度下固化。在此期间载体基板保持平面状态,安装LSI芯片时不会引起变形等不良情况。该半导体芯片的安
装方法采用通常所知的柱状凸点倒装片安装方法。
具有区域阵列型的半导体芯片采用上述的倒装片安装法安装的话,能显著地提高本发明的电气特性。这是因为能使从上述半导体芯片内的元件到封装体的连接压焊区(第2连接压焊区)的距离最短化,可使附属的电容和电感比其它电容和电感小所致。因此在处理高速信号的半导体芯片的情况下,该安装方法能形成最佳封装体形态。
如果采用该第1实施例,由于能使用0.1mm左右的薄基板作为载体基板108,所以能使半导体装置的总体厚度在0.6mm以下。另外,为了使外周的周边加强构件不限制厚度,只要使周边加强构件的厚度比半导体芯片薄即可。另外,本实施例的半导体装置的半导体芯片(LSI芯片)的背面呈裸露状态,所以容易放热。也可以直接接触放热板。如果采用这样的结构,则由于可使LSI芯片的背面直接裸露,所以不用花费模制费用,且没有额外的变形。所以提高了可靠性。
本发明不限于倒装片安装方式,也可以采用将LSI芯片朝上安装在载体基板上、熔丝焊接法将LSI芯片上的端子电极和载体基板上的第1连接压焊区连接起来的安装方法。这时必须对表面进行模制。
图5表示使用本发明的实施形态的芯片载体的半导体装置的第2实施例。该第2实施例是将周边加强构件106围在半导体芯片201附近设置,这是为了实现半导体装置的小型化。这时将密封材料205填充在半导体芯片201和周边加强构件106之间。
图6表示使用本发明的实施形态的芯片载体的半导体装置的第3实施例。该第3实施例是用导热性能好的金属制作上述第2实施例的半导体装置中的周边加强构件106,提高了放热特性。表示第3实施例的图6与用图5说明的第2实施例相似,但周边加强构件106的材料和形状不同。材料最好是金属,铝和铜等导热性能好的金属合适,但其它金属也可以。而形状最好是能促使放热的形状,在本实施例中,如图7所示,为了容易放热,采用将表面积增大了的锯齿形状。该金属制的锯齿形状的周边加强构件106具有调整由载体基板108和该周边加强构件106之间的热膨胀差引起的加在载体基板上的张力的作用。
图8表示使用本发明的实施形态的芯片载体的半导体装置的第4实施例。该第4实施例是用导热性能好的粘接剂602将铝等导热性能好的放热板601安装在第1实施例中的LSI芯片的上表面上的实施例。这样一来,即使安装发热量大的半导体芯片,也能容易地进行散热。另外,由于将放热板直接装在半导体芯片的背面,所以放热特性特别好。
图9表示使用本发明的实施形态的芯片载体的半导体装置的第5实施例。该第5实施例是用导热性能好的粘接剂602将铝等导热性能好的放热板601安装在第2实施例及第3实施例中的LSI芯片的上表面上的实施例。在本实施例中也一样,由于这样处理,即使安装发热量大的半导体芯片,也能容易地进行散热,由于将放热板直接装在半导体芯片的背面,所以放热特性特别好。
图10表示使用本发明的实施形态的芯片载体的半导体装置的第6实施例。该第6实施例如上述第5实施例所示,不仅将放热板设在构成半导体装置的LSI芯片201的上表面上,而且用粘接剂702将放热板(冠状放热板)701包围在周边加强构件106的外周部设置。如果采用本实施例,由于这样设置冠状放热板701,即使使用更大功率的半导体芯片封装体,这时也能有效地放散产生的热。
在上述各实施例中,说明了采用柱状凸点倒装片安装方式连接半导体芯片和载体基板的情况,但本发明不受此限,例如也可以使用软钎焊焊球的连接方法(称为C4方式)。
在上述各实施例中,说明了安装的半导体芯片是1个的情况,但本发明不受此限,也可以安装多个半导体芯片作为MCM(多芯片模块)。
另外,不仅裸半导体芯片,也可以安装封装好的的半导体芯片即用于SMT(表面安装技术)的QFP,制成复合MCM之类的半导体芯片,同时还可以安装电容和电阻等无源元件。
如上所述,如果采用本发明,即使在高温下制造半导体装置,也能获得载体基板不变形等的芯片载体,所以产品的合格率高。另外,用该芯片载体构成半导体装置,能提高LSI芯片和载体基板的连接可靠性,同时往主基板上安装时也能获得可靠性高的连接。

Claims (17)

1.一种芯片载体,其特征在于备有:载体基板和周边加强构件,上述载体基板由用芳香族聚酰胺纤维作为加强材料形成的柔性绝缘基板、在上述柔性绝缘基板的一侧表面上形成的第1连接压焊区、以及在上述柔性绝缘基板的另一侧表面上形成的第2连接压焊区构成,上述第1连接压焊区和上述第2连接压焊区通过在上述柔性绝缘基板上开设的通路孔进行电气连接,上述周边加强构件采用热胀系数比上述载体基板的热胀系数大的材料形成,且设置在上述载体基板的外周部。
2.根据权利要求1所述的芯片载体,其特征在于:上述周边加强构件是金属。
3.根据权利要求1所述的芯片载体,其特征在于:上述周边加强构件呈锯齿状。
4.根据权利要求1所述的芯片载体,其特征在于:上述载体基板是上述通路孔的开口端不在上述柔性绝缘基板的表面上露出的内通路树脂多层基板。
5.根据权利要求1所述的芯片载体,其特征在于:上述第1连接压焊区和上述第2连接压焊区分别形成不同的图形。
6.根据权利要求1所述的芯片载体,其特征在于:在上述第2连接压焊区上备有焊球。
7.一种半导体装置,其特征在于备有:载体基板、周边加强构件和半导体芯片,上述载体基板由用芳香族聚酰胺纤维作为加强材料形成的柔性绝缘基板、在上述柔性绝缘基板的一侧表面上形成的第1连接压焊区、以及在上述柔性绝缘基板的另一侧表面上形成的第2连接压焊区构成,上述第1连接压焊区和上述第2连接压焊区通过在上述挠性绝缘基板上开设的通路孔进行电气连接,上述周边加强构件采用热胀系数比上述载体基板的热胀系数大的材料形成,且设置在上述载体基板的外周部,上述半导体芯片被安装在由上述载体基板和上述周边加强构件形成的凹部。
8.根据权利要求7所述的半导体装置,其特征在于:上述周边加强构件是金属。
9.根据权利要求7所述的半导体装置,其特征在于:上述周边加强构件呈锯齿状。
10.根据权利要求7所述的半导体装置,其特征在于:上述载体基板是上述通路孔的开口端不在上述柔性绝缘基板的表面上露出的内通路树脂多层基板。
11.根据权利要求7所述的半导体装置,其特征在于:上述第1连接压焊区和上述第2连接压焊区分别形成不同的图形。
12.根据权利要求7所述的半导体装置,其特征在于:在上述第2连接压焊区上备有焊球。
13.根据权利要求7所述的半导体装置,其特征在于:上述周边加强构件的厚度比上述半导体芯片薄。
14.根据权利要求7所述的半导体装置,其特征在于:上述半导体芯片被以倒装片方式安装。
15.根据权利要求14所述的半导体装置,其特征在于:上述半导体芯片有区域阵列型端子电极。
16.根据权利要求7所述的半导体装置,其特征在于:上述半导体芯片的上表面上备有放热板。
17.根据权利要求7所述的半导体装置,其特征在于:上述半导体芯片的上表面及上述芯片载体的周边部分覆盖着放热板。
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100334723C (zh) * 2003-04-24 2007-08-29 三洋电机株式会社 半导体装置及其制造方法
CN102376675A (zh) * 2010-08-04 2012-03-14 欣兴电子股份有限公司 嵌埋有半导体元件的封装结构及其制法
CN103632981A (zh) * 2012-08-24 2014-03-12 索尼公司 配线板及配线板的制造方法
CN104465534A (zh) * 2014-12-16 2015-03-25 南通富士通微电子股份有限公司 带支架的基板
CN106783789A (zh) * 2015-11-23 2017-05-31 三星电机株式会社 条状基板及其制造方法
CN111508946A (zh) * 2018-12-18 2020-08-07 联发科技股份有限公司 半导体封装结构
US11171113B2 (en) 2017-03-14 2021-11-09 Mediatek Inc. Semiconductor package structure having an annular frame with truncated corners
US11264337B2 (en) 2017-03-14 2022-03-01 Mediatek Inc. Semiconductor package structure
US11362044B2 (en) 2017-03-14 2022-06-14 Mediatek Inc. Semiconductor package structure
US11387176B2 (en) 2017-03-14 2022-07-12 Mediatek Inc. Semiconductor package structure
US11410936B2 (en) 2017-03-14 2022-08-09 Mediatek Inc. Semiconductor package structure

Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3597913B2 (ja) * 1995-07-20 2004-12-08 松下電器産業株式会社 半導体装置とその実装方法
US6093971A (en) * 1996-10-14 2000-07-25 Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. Chip module with conductor paths on the chip bonding side of a chip carrier
JP3173459B2 (ja) * 1998-04-21 2001-06-04 日本電気株式会社 半導体装置の製造方法
US6140707A (en) * 1998-05-07 2000-10-31 3M Innovative Properties Co. Laminated integrated circuit package
US6329713B1 (en) * 1998-10-21 2001-12-11 International Business Machines Corporation Integrated circuit chip carrier assembly comprising a stiffener attached to a dielectric substrate
TW460927B (en) 1999-01-18 2001-10-21 Toshiba Corp Semiconductor device, mounting method for semiconductor device and manufacturing method for semiconductor device
EP1030366B1 (en) * 1999-02-15 2005-10-19 Mitsubishi Gas Chemical Company, Inc. Printed wiring board for semiconductor plastic package
US6975021B1 (en) * 1999-09-03 2005-12-13 Micron Technology, Inc. Carrier for substrate film
JP3973340B2 (ja) * 1999-10-05 2007-09-12 Necエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
US6232151B1 (en) * 1999-11-01 2001-05-15 General Electric Company Power electronic module packaging
US6362525B1 (en) * 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
US6242815B1 (en) 1999-12-07 2001-06-05 Advanced Semiconductor Engineering, Inc. Flexible substrate based ball grid array (BGA) package
US6429385B1 (en) * 2000-08-08 2002-08-06 Micron Technology, Inc. Non-continuous conductive layer for laminated substrates
US6577018B1 (en) * 2000-08-25 2003-06-10 Micron Technology, Inc. Integrated circuit device having reduced bow and method for making same
US6399892B1 (en) 2000-09-19 2002-06-04 International Business Machines Corporation CTE compensated chip interposer
JP2002134650A (ja) * 2000-10-23 2002-05-10 Rohm Co Ltd 半導体装置およびその製造方法
US6964749B2 (en) * 2001-06-04 2005-11-15 Polymer Group, Inc. Three-dimensional nonwoven substrate for circuit board
US6528892B2 (en) * 2001-06-05 2003-03-04 International Business Machines Corporation Land grid array stiffener use with flexible chip carriers
US6903278B2 (en) * 2001-06-29 2005-06-07 Intel Corporation Arrangements to provide mechanical stiffening elements to a thin-core or coreless substrate
SG102637A1 (en) * 2001-09-10 2004-03-26 Micron Technology Inc Bow control in an electronic package
US6490161B1 (en) 2002-01-08 2002-12-03 International Business Machines Corporation Peripheral land grid array package with improved thermal performance
US7015616B2 (en) * 2002-04-01 2006-03-21 Honeywell International, Inc. System and method for providing coil retention in the rotor windings of a high speed generator
US6943056B2 (en) * 2002-04-16 2005-09-13 Renesas Technology Corp. Semiconductor device manufacturing method and electronic equipment using same
US7339276B2 (en) * 2002-11-04 2008-03-04 Intel Corporation Underfilling process in a molded matrix array package using flow front modifying solder resist
AU2003227213A1 (en) 2003-03-26 2004-10-18 Fujitsu Limited Semiconductor device
US7126228B2 (en) * 2003-04-23 2006-10-24 Micron Technology, Inc. Apparatus for processing semiconductor devices in a singulated form
TWI348748B (en) * 2003-10-07 2011-09-11 Rohm Co Ltd Semiconductor device and method of fabricating the same
US20050127484A1 (en) * 2003-12-16 2005-06-16 Texas Instruments Incorporated Die extender for protecting an integrated circuit die on a flip chip package
KR20070006885A (ko) * 2004-03-31 2007-01-11 어플라이드 머티어리얼스, 인코포레이티드 반도체 장치 제조과정 동안 전도성 부품을 운반하기 위한장치 및 방법
JP4342366B2 (ja) * 2004-04-09 2009-10-14 日本特殊陶業株式会社 配線基板の製造方法
US20050230821A1 (en) * 2004-04-15 2005-10-20 Kheng Lee T Semiconductor packages, and methods of forming semiconductor packages
US7259468B2 (en) * 2004-04-30 2007-08-21 Advanced Chip Engineering Technology Inc. Structure of package
US20060014309A1 (en) * 2004-07-13 2006-01-19 Sachdev Krishna G Temporary chip attach method using reworkable conductive adhesive interconnections
US20060051912A1 (en) * 2004-09-09 2006-03-09 Ati Technologies Inc. Method and apparatus for a stacked die configuration
US7745912B2 (en) * 2005-03-25 2010-06-29 Intel Corporation Stress absorption layer and cylinder solder joint method and apparatus
JP4631636B2 (ja) * 2005-09-22 2011-02-16 富士ゼロックス株式会社 アンテナ
CN101278393A (zh) * 2005-09-29 2008-10-01 日本电气株式会社 半导体封装、衬底、使用这种半导体封装或衬底的电子器件和用于校正半导体封装翘曲的方法
EP1988759A4 (en) * 2006-02-03 2012-10-31 Panasonic Corp PART AND CONNECTION STRUCTURE OF A PRINTED CARD
JP4714598B2 (ja) * 2006-02-22 2011-06-29 富士通株式会社 半導体装置及びその製造方法
US20080099910A1 (en) * 2006-08-31 2008-05-01 Ati Technologies Inc. Flip-Chip Semiconductor Package with Encapsulant Retaining Structure and Strip
US20080054490A1 (en) 2006-08-31 2008-03-06 Ati Technologies Inc. Flip-Chip Ball Grid Array Strip and Package
US7926173B2 (en) * 2007-07-05 2011-04-19 Occam Portfolio Llc Method of making a circuit assembly
US7893527B2 (en) * 2007-07-24 2011-02-22 Samsung Electro-Mechanics Co., Ltd. Semiconductor plastic package and fabricating method thereof
KR20090041936A (ko) * 2007-10-25 2009-04-29 주식회사 동부하이텍 반도체 소자의 금속 패드
US7843058B2 (en) * 2007-10-30 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Flip chip packages with spacers separating heat sinks and substrates
KR20090056077A (ko) * 2007-11-29 2009-06-03 엘지전자 주식회사 인쇄회로기판과 그 제조방법 및 인쇄회로기판 제조용 패널
US7968999B2 (en) * 2008-02-28 2011-06-28 Lsi Corporation Process of grounding heat spreader/stiffener to a flip chip package using solder and film adhesive
TW200943505A (en) * 2008-04-02 2009-10-16 Advanced Semiconductor Eng Reinforced package carrier and method for manufacturing the same as well as method for manufacturing semiconductor packages
KR101169686B1 (ko) * 2008-11-07 2012-08-06 에스케이하이닉스 주식회사 반도체 패키지용 기판 및 이의 제조 방법
CN102171815B (zh) * 2008-11-21 2014-11-05 先进封装技术私人有限公司 半导体封装件及其制造方法
US8400774B2 (en) * 2009-05-06 2013-03-19 Marvell World Trade Ltd. Packaging techniques and configurations
US8232138B2 (en) * 2010-04-14 2012-07-31 Advanced Micro Devices, Inc. Circuit board with notched stiffener frame
US8709874B2 (en) * 2010-08-31 2014-04-29 Advanpack Solutions Pte Ltd. Manufacturing method for semiconductor device carrier and semiconductor package using the same
US8810025B2 (en) 2011-03-17 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Reinforcement structure for flip-chip packaging
US8691624B2 (en) * 2011-11-28 2014-04-08 Infineon Technologies Ag Die fixing method and apparatus
KR102061342B1 (ko) * 2012-06-13 2020-01-02 에스케이하이닉스 주식회사 강화된 범프 체결 구조를 포함하는 전자 소자의 패키지 및 제조 방법
US9236366B2 (en) * 2012-12-20 2016-01-12 Intel Corporation High density organic bridge device and method
US20140233166A1 (en) * 2013-02-19 2014-08-21 Norman E. O'Shea Flexible powered cards and devices, and methods of manufacturing flexible powered cards and devices
US9287194B2 (en) 2013-03-06 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods for semiconductor devices
US9385091B2 (en) * 2013-03-08 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Reinforcement structure and method for controlling warpage of chip mounted on substrate
US10032692B2 (en) 2013-03-12 2018-07-24 Nvidia Corporation Semiconductor package structure
US9760132B2 (en) * 2013-09-19 2017-09-12 Nvidia Corporation Stiffening electronic packages by disposing a stiffener ring between substrate center area and conductive pad
US9282649B2 (en) * 2013-10-08 2016-03-08 Cisco Technology, Inc. Stand-off block
TWI518854B (zh) * 2013-12-30 2016-01-21 財團法人工業技術研究院 模封組件及模封材料
CN105722299B (zh) 2014-12-03 2018-08-31 恒劲科技股份有限公司 中介基板及其制法
JP2017113077A (ja) * 2015-12-21 2017-06-29 ソニー・オリンパスメディカルソリューションズ株式会社 内視鏡装置
CN108573875A (zh) * 2017-03-14 2018-09-25 兴讯科技股份有限公司 双面载放零件的电子芯片模块
US10424527B2 (en) 2017-11-14 2019-09-24 International Business Machines Corporation Electronic package with tapered pedestal
JP7203087B2 (ja) * 2018-03-30 2023-01-12 リンテック株式会社 保護膜形成用複合シート及びその製造方法
EP3799539B1 (de) * 2019-09-27 2022-03-16 Siemens Aktiengesellschaft Schaltungsträger, package und verfahren zu ihrer herstellung

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513603A (ja) * 1974-06-27 1976-01-13 Matsushita Electric Ind Co Ltd Teepuseigyosochi
US4318954A (en) * 1981-02-09 1982-03-09 Boeing Aerospace Company Printed wiring board substrates for ceramic chip carriers
JPH0287655A (ja) * 1988-09-26 1990-03-28 Nec Corp 半導体装置
US5067008A (en) * 1989-08-11 1991-11-19 Hitachi Maxell, Ltd. Ic package and ic card incorporating the same thereinto
US5067004A (en) * 1989-12-13 1991-11-19 Digital Equipment Corporation Module for interconnecting integrated circuits
JPH0513603A (ja) * 1991-07-02 1993-01-22 Hitachi Ltd 半導体集積回路装置
US5483421A (en) * 1992-03-09 1996-01-09 International Business Machines Corporation IC chip attachment
US5702985A (en) * 1992-06-26 1997-12-30 Staktek Corporation Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method
JPH07201855A (ja) * 1993-12-28 1995-08-04 Fujitsu Ltd 半導体装置
JP2531125B2 (ja) * 1994-04-11 1996-09-04 日本電気株式会社 Icチップキャリアモジュ―ル
US5661086A (en) * 1995-03-28 1997-08-26 Mitsui High-Tec, Inc. Process for manufacturing a plurality of strip lead frame semiconductor devices
JPH091855A (ja) * 1995-06-16 1997-01-07 Canon Inc 画像処理装置

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CN102376675A (zh) * 2010-08-04 2012-03-14 欣兴电子股份有限公司 嵌埋有半导体元件的封装结构及其制法
CN102376675B (zh) * 2010-08-04 2015-11-25 欣兴电子股份有限公司 嵌埋有半导体元件的封装结构及其制法
CN103632981A (zh) * 2012-08-24 2014-03-12 索尼公司 配线板及配线板的制造方法
CN103632981B (zh) * 2012-08-24 2017-09-22 索尼公司 配线板及配线板的制造方法
CN104465534A (zh) * 2014-12-16 2015-03-25 南通富士通微电子股份有限公司 带支架的基板
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US11171113B2 (en) 2017-03-14 2021-11-09 Mediatek Inc. Semiconductor package structure having an annular frame with truncated corners
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US11948895B2 (en) 2017-03-14 2024-04-02 Mediatek Inc. Semiconductor package structure
CN111508946A (zh) * 2018-12-18 2020-08-07 联发科技股份有限公司 半导体封装结构

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CN1085891C (zh) 2002-05-29
JP3437369B2 (ja) 2003-08-18
EP0797253B1 (en) 2004-06-30
DE69729673D1 (de) 2004-08-05
US5841194A (en) 1998-11-24
JPH09260527A (ja) 1997-10-03
EP0797253A3 (en) 1999-04-14
EP0797253A2 (en) 1997-09-24
DE69729673T2 (de) 2005-08-04

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