CN1175805A - 集成电路的时钟相位差最小化系统和方法 - Google Patents

集成电路的时钟相位差最小化系统和方法 Download PDF

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CN1175805A
CN1175805A CN97117154A CN97117154A CN1175805A CN 1175805 A CN1175805 A CN 1175805A CN 97117154 A CN97117154 A CN 97117154A CN 97117154 A CN97117154 A CN 97117154A CN 1175805 A CN1175805 A CN 1175805A
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chip
lead
solder joint
wire
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CN1110097C (zh
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费伦克·米克洛斯·博泽索
菲利普·乔治·埃玛
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International Business Machines Corp
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Abstract

在一个有源衬底上制作了一个精确而高度可控的时钟分配网络,以便借助于用倒装片技术将衬底面对面地连接在一起而以最小的相位差将时钟信号分配到另一有源衬底。由于时钟分配衬底是元件稀疏的,故在稀疏的衬底上制作了“静噪总线”以便在相当长的距离内高速传送数据。可在一个衬底上以最小的互连距离制作为另一衬底上的高功率逻辑(例如处理器)所用的低功率器件(例如DRAM)。

Description

集成电路的时钟相位差 最小化系统和方法
本发明涉及到集成电路封装，确切地说是涉及到使集成电路时钟相位差减为最小的封装系统和方法。
倒装片技术，有时称为可控折叠芯片连接(C4)技术是完全既成的并被颠倒地用来将芯片连接于二级封装件(衬底)。此技术通常涉及到将焊球置于芯片I/O焊点上、反转芯片并将其焊接到带有相同的焊点图形的衬底上以便在芯片与衬底之间形成互连。图1示意地示出了这类产品的一个例子。为了对焊球和C4技术进行讨论，可参见R.Tummala和E.Rymaszewski的《微电子学封装手册》(Von Nostrand Reinhold，1989)及“焊球连接技术”，IBM J.of Res.and Dev.，37，No.5，1993年9月，pp.581-676。
历史上，衬底仅仅是一个二极封装(亦即一个带有布线层的无源件)。这种衬底是陶瓷、玻璃陶瓷、甚至是硅。衬底的目的仅仅是在衬底上各芯片之间提供布线方法。
处理器包含许多与外部输入一起工作于当前状态以计算系统的下一状态的锁存器(保持系统的状态)和逻辑。理想情况下，时钟严格同时地作用于所有锁存器以便同时地完成向这一新计算状态的过渡。
实际上，时钟不可能准确地同时到达每一个锁存器，故不是所有的锁存器都在准确的同一时间开关。若第一锁存器的输出对第二锁存器的输入起作用(直接地或通过逻辑电路)，且时钟到达第二锁存器的时刻相对于时钟到达第一锁存器的时刻的误差为±x，则为了使第二锁存器提前x而获得数据就必须使标称周期时间(机器中的最坏情况延迟路径)增加x。由于第一锁存器可能在假设的时间之后x时获得有关的数据，故实际的标称周期时间须增加2x。这是时钟相位差对性能的一种影响，是一个加至处理器标称周期时间的因素，用来考虑时钟信号到达处理器不同部位的误差。
时钟信号是芯片的主要输入。它是一个振荡器脉冲。在一个实际的中央处理器(CP)芯片中，通常有数万个由这一时钟选通的锁存器。若典型门的输出端数为f，且有n个锁存器，则在原始时钟脉冲(芯片的主输入)与任一被此时钟选通的锁存器之间必须有logf(n)个中间级驱动器。在实际系统中可能多达10级。
由于树的各枝到源的距离不同，在输出端树型结构中提供的那些重驱动的级是不对称的，因而不能准确地驱动同样数目的锁存器。亦即布线长度不同，且负载不同。这些是对时钟相位差的主要贡献。而且当周期时间变得更快时，此问题更大。
由于微处理器中的大多数硅区是有源的，故重驱动的中间级不能置于理想位置；而只好置于“空白”位置。这就造成不对称。
在复合微处理器的习惯设计中，硅表面无法用常规图形“撒布”时钟重驱动级。时钟驱动电路的常规“撒布”可能干扰逻辑电路的物理数据流且可能有损于周期时间。亦即难以降低相位差，且在任何实际的单片处理器中不可能使其可忽略。
本发明的目的是用C4技术在有源衬底上提供一种精确而高度可控的时钟分配网络(以下称为副衬底或芯片)，并通过此网络以最小的相位差时钟信号分配到另一有源衬底(以下称为主衬底或芯片)。注意，通常主衬底元件密集且耗散大量功率，而副衬底元件稀少且消耗的功率明显较少。
本发明的另一目的是在元件稀少的副衬底上提供“静噪总线”，使数据更易于高速地传送到主衬底的各个点。
本发明的另一目的是在副衬底上提供为主衬底上较高功率逻辑(例如处理器)所用的其它低功率外围硬件(例如DRAM)。
本发明的又一目的是用同一C4技术提供第三(以及更高阶)衬底。
根据本发明的一种情况，二个有源芯片(即含有有源电路的二者)被连接在一起。为此有二个先决条件：
1.所有芯片产生的总热量不多于可移走的热量。
2.各芯片尺寸不同或彼此偏离地连接。其优点是使I/O焊点可用其它封装件的连接方法为偏芯片连接所接近。或芯片尺寸相同，且面对面地对准并连接，则I/O焊点无法接触。若一个小芯片连接于一个较大的芯片，或若尺寸相同的芯片偏离地连接在一起，芯片表面各部位可用引线焊接方法连接到另一衬底。实际上，若在第三表面上提供了接收较小芯片的沟槽，则用C4技术可将二芯片中较大芯片上的焊点焊接到一个更大的第三衬底。
本发明的另一种情况是将消耗明显功率的元件密集的复合逻辑电路焊接到消耗显著更少功率的元件稀少的有源芯片。
元件稀少的副芯片可用来以极为可控的方式分配时钟信号；用作可比主芯片表面上更高速地在静噪环境中工作的长的总线的静噪介质；以及用作其它类型的可选低功率器件(例如DRAM)。由于提供了较高性能的通信和较好的系统级的相位差控制并导致更价廉的封装件，故这是有用的。
本发明将参照下列附图进行解释，其中：
图1示出了用C4连接于副衬底的一个主衬底。
图2示出了一个分成256个方块(每块的中央有一个I/O焊点)的16mm×16mm的芯片。
图3示出了16mm×16mm网格上256个方块的时钟驱动和校正电路。
图4示出了以二元树形式实现的时钟网络的对称布线方式。
图5示出了根据本发明的静噪总线上的一个引线。
图6示出了根据本发明而构成的主封装件和副封装件的第一实施例。
图7示出了根据本发明而构成的主封装件和副封装件的第二实施例。
图8示出了根据本发明焊接的主芯片、副芯片和第三芯片。
图9示出了一个使时钟信号延迟一定时间量的时钟修整电路。
在现有的单片微处理器系统中，时钟分配网络是预置在处理器芯片本身之中。相反，在根据本发明的系统中，主衬底可以是一个不带时钟分配网络的微处理器芯片，而时钟分配网络提供在副衬底上。注意此电路以及与此二系统相关的功率是相同的，亦即本发明本身不发生功率或冷却问题。
而且，若除了时钟分配网络，副衬底上没有其它东西，则副衬底的有源区极为宽裕，故时钟树的重驱动节点可理想地分布。具体地说，重驱动级可安排在对称的位置，并在整个树中的所有引线长度和负载都是完全相同的。如上所述，这在带有集成在微处理器芯片中的时钟分配网络的任何实际的微处理器芯片中是不可能的。
在本发明中，元件密集的主衬底(例如微处理器)被想象地分割成大量的方块(例如1mm×1mm或更小)，且时钟I/O焊点位于各块的中央。方块中的所有锁存器由方块中央的时钟焊点驱动。此结构示于图2。
具体地说，图2示出了一个划分成16×16个块(每个块为1mm×1mm)的16mm×16mm的芯片。I/O焊点200示于各块的中央。此I/O焊点是一个本地时钟输入焊点并驱动此块中的所有锁存器。此图中由I/O焊点到锁存器的最坏情况Manhattan距离为1mm。
这些I/O焊点的时钟输入通过焊球连接被提供给含有用于主芯片逻辑的时钟分配电路的副衬底上完全相同地分布的I/O焊点。由于副衬底上的时钟分配网络稀疏，主时钟信号同时到达副衬底上的所有驱动器焊点，故对于主衬底上的所有块，可保证误差极小。这在现有的带集成时钟分配网络的微处理器中是不可能的。
而且，由于副衬底上的电路极为稀疏，为了更好地控制相位差，还可将时钟修整和校准电路预置于时钟分配网络中。这样，本发明就在通过消除相位差而改善周期时间的同时简化了时钟分配设计。
例如，图3示出了16mm×16mm芯片区各块中的50μm×400μm的矩形300。这些矩形代表与各块相关的时钟修整和校准电路所需的区域。这些矩形中的电路更适于提供健全的时钟修整和校正，且显然由图知所涉及的区域是无关紧要的。
图4示出了副衬底上构成二元树形式的时钟树的最佳布线布局。注意从主时钟输入402到每个叶节点400的距离准确地相同，且沿每一输出端节点方向的负载输出端数完全相同。位于每个叶节点处的是一个用来驱动该叶节点处的输出脚的驱动电路(未示出)。
时钟修整电路(或控制电路)包含只扫描控制锁存器，其状态在输出时钟信号之前引起电路将时钟边界相对于参考(输入时钟)信号向后移动。图3中的每个块具有其自身的状态控制锁存器，而且所有这些锁存器都被连接于副衬底上的同一扫描环。根据本发明，通过探测主(或副)衬底上发射的时钟信号，然后通过扫描环调节时钟边界，可进一步控制时钟相位差。这是一个标准技术。
图9的电路运行如下。一个待偏移的总的时钟信号到达图9修整电路的过程延迟电路903的输入901。过程延迟电路包含使输入信号延迟100ps的延迟元件。复用器905由控制锁存器900a控制而选择延迟了的或未延迟过的信号。复用器905的输出被提供给精细延迟电路904，904也包含使信号增加延迟25ps的延迟元件。复用器902被控制锁存器900b和900c控制而选取所需的输出信号。复用器902的输出是原来输入到电路904的信号被延迟25ps的整数倍之后的延迟信号。
由稀疏的副衬底引起的本发明的另一特点是能够用于副衬底上的“静噪总线”。由于主衬底上的金属层密集地利用，使环境噪声大得本技术无法工作，故在主衬底上无法实现这一静噪总线技术。
特别是，由于时钟分配网络只需要可用布线通道的不重要的一部分，故副衬底上的大多数布线通道(可能包括几个整个的金属层)可以接地，从而为实际通过副衬底的为数很少的信号提供一个高度屏蔽(静噪)环境。
图5示出了静噪总线上的一个信号引线。由于环境非常安静，可通过阻抗很高的预充电路500将引线预充电到一个中间电压电平。这一预充电电路恒定地漏电，但高的阻抗使漏电很低。由于耦合的噪声可很容易地沿随机方向推动预充电电路，故此电路在噪声环境中不能使用。
引线的输入是一个时钟通道门502，它获取一个静态输入的短样品，并使小取样在使总线到达其预充电状态附近的静态工作点之前迅速地将预充电的总线拉向恰当的方向。这引起其速度与引线的特征阻抗有关的行波。信号到达远端要比任何驱动电路取用此信号作为在噪声环境中的标准传输方法对引线充电要快得多。此小信号脉冲由远端处的标准驱动器504转换成静态信号。
在空间许可的情况下，倘若不会在任何静噪总线周围产生噪声环境，则可在副衬底上安置其它的低功率电路。越来越多的其中处理器芯片带有用作大型L2超高速存储器的专用DRAM的系统正被提出。在这些系统中，微处理器和L2是紧密地安装在多芯片组件(MCM)上的性质不同的芯片。
若二个芯片彼此邻接，则最坏情况下的信号传播距离约为三个芯片“间距”(一个芯片的三边)，并且用有效的设计有可能降到二个芯片间距。
然而，若L2是DRAM，则待用功率通常很小，而且根据本发明，DRAM可与副衬底集成并直接焊接到CP芯片上而不引起冷却问题。这种情况下的最坏情况距离决定于二个芯片间距，并可用有效的设计降为低于一个芯片间距。
借助于降低有限超高速存储器效应，本技术改善了系统性能。(“有限超高速存储器”对测得的处理器“单位指令的周期”(CPI)性能的是芯片上超高速存储器的遗漏率(单位指令遗漏)和与芯片外存储器分级结构相关的遗漏损失(单位遗漏的周期)的乘积。这种遗漏损失的一个组成是从CP芯片到L2之间的往返所引起的延迟。)也有可能使多周期延迟降为单周期，使干线排布得到改善从而有二阶性能获益。
图6-8示出了根据本发明的各种实施例。
在图6中，主副衬底的尺寸可比拟，但以偏离方式通过焊球600连接，从而为外部连接而暴露主衬底的I/O脚602和副衬底的I/O脚604。如上所述，主副衬底都带有有源电路。
在图6中，主衬底稍小于副衬底，以便为外部连接而暴露副衬底的I/O脚。主副衬底仍然都带有有源电路。
如图8所示，本发明可延伸到还包括一个第三(和更多)衬底。图8的实施例包括一个主衬底800、副衬底802和第三衬底804。主副衬底用位于相应I/O焊点的焊球806焊接在一起。副衬底的外部I/O焊点808用相同的C4(倒装片)技术焊接到第三衬底上的焊点。为了便于这一连接，在第三衬底中可提供沟槽以接纳主衬底。第三衬底的外部I/O脚810为外部连接而暴露。
本发明提供的另一好处是它导致廉价的封装件。在处理器/DRAM的情况下，用现有技术要求多芯片组件(二级封装件)，而这种二级封装件所要求的面积正比于三级封装件(例如卡)必须容纳的二个芯片。
在根据本发明而制造的处理器/DRAM系统中，由于DRAM副衬底是处理器主衬底的载体，故本身没有二极封装件。这种处理器/DRAM单封装体可用引线或C4直接焊接到第三级封装件，且所需的面积仅仅正比于副衬底的面积(即单个芯片的面积)。现今应用于这种系统中的同一个第三级封装件可容纳二倍的根据本发明所制造的系统。
虽然根据最佳实施例已描述了本发明，但显然可对所公布的实施例进行修改而不超越下列权利要求所定义的本发明的构思与范围。

Claims (33)

1.一种系统，它包含各具有有源元件的一个主芯片和一个副芯片，上述主芯片和副芯片彼此面对面地被连接，使至少副芯片上的I/O焊点对系统外的连接装置保持可接触。
2.根据权利要求1的系统，其特征是主副芯片通过焊球而连接。
3.根据权利要求1的系统，其特征是主芯片的面积小于副芯片的面积。
4.根据权利要求1的系统，其特征是主副芯片以偏离的方式面对面地连接。
5.根据权利要求1的系统，其特征是上述主芯片含有逻辑电路，而上述副芯片含有时钟分配网络。
6.根据权利要求5的系统，其特征是上述时钟分配网络是一个叶节点位于规格网格上的输出端树，每个上述叶节点含有一个I/O驱动电路，每个上述I/O驱动电路驱动一个位于对应于上述叶节点的上述网格点中心的I/O焊点，每个上述I/O焊点连接于主芯片上的相应I/O焊点，每个上述主芯片上的上述I/O焊点用作一个时钟输入，每个上述时钟输入用来选通此输入附近并连接于此输入的储存元件。
7.根据权利要求6的系统，其特征是至少一个上述I/O驱动电路还包含一个用来使时钟输入延迟一个一定的时间量的控制装置。
8.根据权利要求7的系统，其特征是上述控制装置储存将几个一定的时间量中的一个加以说明的状态信息，上述状态信息用由扫描操作设定的储存装置来保持。
9.根据权利要求1的系统，其特征是至少上述主副芯片中的一个在一个或更多个金属布线层上含有无源区和未被利用的布线的区域，其中多个上述布线中的引线被连接于公共地，以致上述布线中的某些引线被上述接地的引线所屏蔽。
10.根据权利要求9的系统，其特征是上述被屏蔽的引线被用来传输数据信号。
11.根据权利要求8的系统，其特征是还包含传输装置，它包括一个有源的高阻抗预充电电路和一个将输入信号选通到引线发送端的电路，上述预充电电路使引线的电压保持在逻辑电平0和1之间的电平，上述选通电路由时钟脉冲周期性地开关以对上述输入信号取样从而启动上述传输装置来在静噪环境下根据上述输入信号的状态而传输信号脉冲。
12.权利要求9的系统，其特征是上述副芯片含有上述被屏蔽了的引线。
13.根据权利要求12的系统，其特征是上述被屏蔽的引线被用来传输信号。
14.根据权利要求13的系统，其特征是还包含传输装置，它包括一个有源的高阻抗预充电电路和一个将输入信号选通到引线发送端的电路，上述预充电电路使引线的电压保持在逻辑电平0和1的中间电平，上述选通电路由时钟脉冲周期性地开关以对上述输入信号取样从而启动上述传输装置来在静噪环境下根据上述输入信号的状态而传输小信号脉冲。
15.根据权利要求14的系统，其特征是上述传输装置被用来在上述主芯片上的元件之间传输信号。
16.根据权利要求1的系统，其特征是上述副芯片含有DRAM。
17.权利要求1的系统，其特征是还包含带有接收主芯片的沟槽的一个第三芯片，且副芯片面对面地连接于第三芯片，从而保留上述第三芯片上的I/O焊点可与系统外面的连接装置接触。
18.权利要求1的系统，其特征是还包含第二主芯片，其中每个上述芯片面对面地连接于副芯片，使至少上述副芯片上的I/O焊点对上述芯片系统外面的连接装置保持可接触。
19.权利要求18的系统，其特征是还包含一个带有用来接收每上上述主芯片的沟槽的第三芯片，其中副芯片面对面地连接于第三芯片，使上述第三芯片上的I/O焊点对系统外面的连接装置保持可接触。
20.一种在分层中带有多于三层的分层连接的芯片系统，其中在分层结构的每一层中，在每个上述层中的芯片有一个用来接收较下层分层结构子系统的沟槽，且其中每个上述较下层分层结构中最高位的芯片被面对面地连接于上述层的芯片，使上述层的芯片的某些I/O焊点对多层结构的上述层以上的连接装置可连接。
21.一种集成电路芯片，它在一个或更多个金属布线层上包含无源区和未利用的布线区，其中布线中的多个引线被连接于公共地，使布线中的某些引线被接地的布线所屏蔽。
22.一种将时钟信号分配给芯片中多个接收点的方法，其中上述接收点处被接收的上述时钟信号的相位差被减到最小，上述方法包含下列步骤：
将上述接收点的I/O焊点置于主芯片表面上的规则网格上，
在副芯片上构建一个时钟分配网络，其中上述网格的输出是位于上述副芯片表面上规则网格上的1/O焊点，上述副芯片上的网格是主芯片上网格的镜象，
将上述主芯片面对面地焊接于上述副芯片。
23.权利要求22的方法，其特征是还包含将上述时钟分配网络做成沿上述副芯片上每一输出端点的每一方向具有相等的负载和引线长度的对称树，且上述I/O焊点是上述树的叶节点的步骤。
24.权利要求23的方法，其特征是还包含将一个驱动电路置于每个上述叶节点处的步骤。
25.权利要求24的方法，其特征是还包含为至少一个上述驱动电路提供响应状态输入的控制装置以便使上述驱动电路延迟一个由上述状态输入所确定的一定时间量的步骤。
26.权利要求25的方法，其特征是还包含提供用来保持用以控制上述驱动电路的状态输入信息的装置的步骤。
27.权利要求26的方法，其特征是还包含测量上述时钟信号在多个上述接收点处的到达，以及改变储存在上述状态保持装置中的状态，以便使上述驱动器响应改变其相对延迟所引起的上述改变了的状态，从而使上述多个接收点之间的上述时钟信号的相位差减为最小。
28.一种为芯片上信号引线产生低噪声环境的方法，它包含下列步骤：
使上述信号引线通过芯片上的无源表面区，
在同一布线平面内使接地的引线邻近上述信号引线，以及
在相邻的布线平面内使接地的引线邻近上述信号引线。
29.权利要求28的方法，其特征是还包含：
通过使小信号能够断续地干扰上述静态值的高阻抗电路，恒定而有源地将上述信号引线预充电到逻辑0和1电平之间有一个静态值，
断续地将小信号值选通到上述信号引线的发射端以响应数据输入而干扰上述静态值，以及
在上述信号引线的接收端接收此小信号。
30.权利要求29的方法，其特征是还包含：
提供一个带有第一和第二电路元件的主芯片；
将高速信号引线置于副芯片上；
将上述主芯片面对面地焊接到上述副芯片；
将上述信号通过上述焊球从上述主芯片上的上述第一元件驱动到上述副芯片上；
用上述副芯片上的上述高速信号引线顺利进行传输，以及
在上述副芯片上的上述高速信号引线的接收端处，通过上述主芯片上的上述焊球将上述信号驱动到上述主芯片上的上述第二元件。
31.一种使逻辑芯片与DRAM芯片之间的传输距离减到最小的方法，它包含用倒装片技术将上述逻辑芯片面对面地焊接到上述DRAM芯片上的步骤。
32.一种制作多芯片系统的方法，它包含下列步骤：
用倒装片技术，使第一芯片顶表面上的I/O焊点连接于第二芯片顶表面上的I/O焊点同时使第二芯片表面上的某些I/O焊点保持可接触于二芯片系统外面的连接，以这样的方式将第一芯片的顶表面焊接到第二芯片的顶表面而制作一个二芯片系统，
在第三芯片中提供一个大得足以接纳上述第一芯片的沟槽，以及
将上述第二芯片的顶表面焊接到上述第三芯片的顶表面，其中上述第一芯片被插入到上述第三芯片的上述沟槽中，上述焊接步骤采用倒装片技术以便将上述第二芯片顶表面上的上述可接触的I/O焊点连接到上述第三芯片顶表面上的I/O焊点，同时使上述第三芯片顶表面上的某些I/O焊点对此三芯片系统外面的连接保持可接触。
33.权利要求32的方法，其特征是还包含将第三芯片的顶表面焊接到第四芯片的顶表面，为了形成一个四芯片系统，第四芯片带有用来接纳第一和第二芯片的沟槽。
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TW357447B (en) 1999-05-01
SG53009A1 (en) 1998-09-28
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DE69715762T2 (de) 2003-04-24
JP3358171B2 (ja) 2002-12-16
CN1110097C (zh) 2003-05-28
US6040203A (en) 2000-03-21
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