CN1183648A - 半导体存储器件及其制造方法 - Google Patents

半导体存储器件及其制造方法 Download PDF

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CN1183648A
CN1183648A CN97121153A CN97121153A CN1183648A CN 1183648 A CN1183648 A CN 1183648A CN 97121153 A CN97121153 A CN 97121153A CN 97121153 A CN97121153 A CN 97121153A CN 1183648 A CN1183648 A CN 1183648A
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CN1099714C (zh
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高尧焕
崔珍赫
姜相元
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SK Hynix Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

Abstract

一种半导体存储器件,包括:元件分离膜,配置于一假想基准线上;第一接合区,配置于该假想基准线的上部,并被该元件分离膜所包围;柱状的沟道区,与该第一接合区相连接;第二接合区,设于该柱状的沟道区的上部;栅极绝缘膜与字元线,包围在该柱状的沟道区的侧壁;位元线,连接于该第二接合区;柱状的电荷存贮电极,配置于该假想基准线的下部,并与该第一接合区相连接;介电膜,覆盖于该柱状的电荷存贮电极的表面;及板状电极,覆盖于上述介电膜上。本发明还涉及其制造方法。

Description

半导体存储器件 及其制造方法
本发明涉及半导体存储器件及其制造方法。
由于半导体存储器件的高密集化，构成半导体存储器件的各元件的占有面积必须减小。特别是构成单位单元的晶体管的占有面积的减小，对于半导体存储器件的高密集化会产生重大影响。另外，在同一面积内确保较高的电容的电容器的开发，会成为决定今后半导体存储器件的密集度的要因。
通常，MOS晶体管的沟道被水平形成，所以占较多面积。为了减少这种MOS晶体管的占有面积，必须先改进光掩模工艺与蚀刻工艺。除了这种光掩模工艺与蚀刻工艺相关的研究之外，尚需进行应用现在的光掩模工艺与蚀刻工艺而能得到更高密集度的垂直沟道构造的MOS晶体管相关的研究和开发。且除了这种MOS晶体管外，能确保构成单位单元的电容器的充分电容的DRAM相关的研究和开发也必须同步进行。
本发明的目的是为获得高密集化，而提供一种具有垂直沟道型MOS晶体管与能确保充分的电容的电容器的半导体存储器件及其制造方法。
为了实现上述目的，根据本发明的一个方面，提供一种半导体存储器件，包括：元件分离膜，配置于一假想基准线上；第一接合区，配置于该假想基准线的上部，并被该元件分离膜所包围；柱状的沟道区，与该第一接合区相连接；第二接合区，设于该柱状的沟道区的上部；栅极绝缘膜与字元线，包围在该柱状的沟道区的侧壁；位元线，连接于该第二接合区；柱状的电荷存贮电极，配置于该假想基准线的下部，并与该第一接合区相连接；介电膜，覆盖于该柱状的电荷存贮电极的表面；及板状电极，覆盖于上述介电膜上。
根据本发明的另一方面，提供一种半导体存储器件的制造方法，包括如下步骤：在已形成有元件分离膜的第一半导体晶片的一侧表面形成第一接合区；形成连接于该第一接合区的柱状的电荷存贮电极；在该柱状的电荷存贮电极的表面形成介电膜；形成覆盖于已形成有该介电膜的整体构造上的板状电极；在已平坦化的该板状电极的表面形成粘接层；在该粘接层上粘接用以支持该第一半导体晶片的第二半导体晶片；将被除去一定厚度的该第一半导体晶片进行选择性蚀刻，而形成沟道区；形成包围于该沟道区的侧壁部分的栅绝缘膜与栅电极；在该沟道区的露出部分形成第二接合区；在已形成有第二接合区的整体构造的上部形成层间绝缘膜；以及贯通该层间绝缘膜形成接触于该第二接合区的位元线。
藉由使构成半导体存储器件的单位单元的MOS晶体管的占有面积减小，实现立体的电荷贮存电极，确保充分的电容的方式，可以制造出更高密集度的半导体存储器件。
以下结合附图来详述本发明的优选实施例。附图中：
图1A-1E表示根据本发明的一个优选实施例的DRAM的制造工艺的示意图。
以下参照图1A至1E，以说明本发明的实施方式。各实施方式间的共同部分，仅在该一部位附上相同的标号，而省略重复的说明。
首先，如图1A所示，在硅晶片1的既定部位形成元件分离膜2后，进行掺杂离子注入，而形成源极3。该源极3可驱动其后形成的电容器。接着，在整体构造的上部，蒸镀多晶硅膜，而形成用以限定电荷存贮电极的光致抗蚀剂图型。其后，以此作为蚀刻掩模将多晶硅膜予以蚀刻，形成电荷存贮电极4。接着，形成覆盖于电荷存贮电极4表面的介电膜5，在整体构造的上部，蒸镀多晶硅膜，而形成板状电极6。
其次，如图1B所示，藉由化学机械式抛光(Chemical MechanicalPolishing：CMP)步骤使板状电极6平坦化后，在其上部蒸镀以供粘接晶片(Wafer Bonding)用的氧化膜7，或称场氧化层，用作绝缘膜，在氧化膜7的上部再利用绝缘层上有硅(SOI)技术粘接一硅晶片8。硅晶片8在抛光步骤时，或其他物理的外力作用时，用以支持晶片的整体构造。
其次，如图1C所示，将整体构造翻转过来使硅晶片8位于下方，施行化学机械式抛光步骤，除去其一部分的厚度直至硅晶片1仅剩下0.1μm-1.0μm的厚度。其后，选择性地将硅晶片1予以蚀刻，使得能藉由元件分离膜2使其分离为各单位元件，亦即，可与源极3连结形成垂直沟道型单位MOS晶体管。接着，在整体构造的上部，形成栅极氧化膜9。
其次，如图1D所示，在整体构造的上部，蒸镀用以形成栅电极的多晶硅膜，将栅极氧化膜9予以全面性蚀刻，而形成包围于垂直沟道1a的栅电极10。此时，在用以形成周边电路用水平沟道型栅电极10a而蒸镀的多晶硅膜的上部涂敷光致抗蚀剂后，再于元件分离膜2的上部形成用以在有源区1b的上部形成周边电路用栅电极10a的光致抗蚀剂图形，而该有源区1b是为形成周边电路用晶体管而限定的。进而，以该光致抗蚀剂图形为蚀刻掩模对多晶硅膜进行干蚀刻。
接着，如图1E所示，对于为了形成垂直沟道1a与周边电路用晶体管而限定的有源区1b，进行杂质离子注入，而形成漏极11与周边电路用接合区11a。然后，在整体构造的上部，蒸镀层间绝缘膜亦即氧化膜12，对氧化膜12进行选择性地蚀刻，使漏极11与周边电路用接合区11a露出，形成接触孔。其后，在整体构造的上部，蒸镀用以形成位元线13及周边电路用电极13a的金属膜，将此予以选择性蚀刻。
本发明并非限定于实施例及图面所示内容，在不脱离本发明的技术构思的范畴内可作出各种替换与变更，本发明的范围应由后附权利要求来限定。

Claims (11)

1.一种半导体存储器件，包括：
元件分离膜，配置于一假想基准线上；
第一接合区，配置于该假想基准线的上部，并被该元件分离膜所包围；
柱状的沟道区，与该第一接合区相连接；
第二接合区，设于该柱状的沟道区的上部；
栅极绝缘膜与字元线，包围在该柱状的沟道区的侧壁；
位元线，连接于该第二接合区；
柱状的电荷存贮电极，配置于该假想基准线的下部，并与该第一接合区相连接；
介电膜，覆盖于该柱状的电荷存贮电极的表面；及
板状电极，覆盖于上述介电膜上。
2.根据权利要求1所述的半导体存储器件，其中，还包括设于该板状电极的下部的绝缘膜与支持基板。
3.根据权利要求1或2所述的半导体存储器件，其中，该第一接合区及第二接合区分别为源极与漏极。
4.根据权利要求1或2所述的半导体存储器件，其中，在周边电路区还具有水平沟道型MOS晶体管。
5.一种半导体存储器件的制造方法，包括如下步骤：
在已形成有元件分离膜的第一半导体晶片的一侧表面形成第一接合区；
形成连接于该第一接合区的柱状的电荷存贮电极；
在该柱状的电荷存贮电极的表面形成介电膜；
形成覆盖于已形成有该介电膜的整体构造上的板状电极；
在已平坦化的该板状电极的表面形成粘接层；
在该粘接层上粘接用以支持该第一半导体晶片的第二半导体晶片；
将被除去一定厚度的该第一半导体晶片进行选择性蚀刻，而形成沟道区；
形成包围于该沟道区的侧壁部分的栅绝缘膜与栅电极；
在该沟道区的露出部分形成第二接合区；
在已形成有第二接合区的整体构造的上部形成层间绝缘膜；以及
贯通该层间绝缘膜形成接触于该第二接合区的位元线。
6.根据权利要求5所述的半导体存储器件的制造方法，其中，该第一接合区及第二接合区分别为源极区与漏极区。
7.根据权利要求5所述的半导体存储器件的制造方法，其中，该板状电极的平坦化与该第一半导体晶片的一定厚度的除去是以化学机械式抛光步骤进行的。
8.根据权利要求5所述的半导体存储器件的制造方法，其中，在该形成沟道区的步骤，同时形成周边电路用水平沟道区。
9.根据权利要求7所述的半导体存储器件的制造方法，其中，已被除去一定厚度的该第一半导体晶片的厚度为0.1μm-1.0μm。
10.根据权利要求8所述的半导体存储器件的制造方法，其中，在该形成栅绝缘膜与栅电极的步骤，同时形成该周边电路用栅绝缘膜及水平沟道型栅电极。
11.根据权利要求10所述的半导体存储器件的制造方法，其中，在该形成第二接合区的步骤，同时在水平沟道区形成周边电路用接合区。
CN97121153A 1996-10-22 1997-10-22 半导体存储器件及其制造方法 Expired - Fee Related CN1099714C (zh)

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US6329239B2 (en) 2001-12-11
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KR100209212B1 (ko) 1999-07-15
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US5888864A (en) 1999-03-30
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DE19746448A1 (de) 1998-04-23
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GB2318909A (en) 1998-05-06
CN1099714C (zh) 2003-01-22

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