CN1188906C - 层叠芯片封装件的制造方法 - Google Patents

层叠芯片封装件的制造方法 Download PDF

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Publication number
CN1188906C
CN1188906C CNB021578087A CN02157808A CN1188906C CN 1188906 C CN1188906 C CN 1188906C CN B021578087 A CNB021578087 A CN B021578087A CN 02157808 A CN02157808 A CN 02157808A CN 1188906 C CN1188906 C CN 1188906C
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substrate
semiconductor chip
packaging part
stacked
platform
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CN1430251A (zh
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金芝连
文起一
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Abstract

本发明提供具有多个半导体芯片层叠构造的层叠半导体封装件的制造方法。该方法包括以下步骤：将具有第一中心窗口的第一基板附着在在中心部分配置有多个第一焊接焊盘的第一半导体芯片上的工序；形成使第一半导体芯片和第一基板连接的第一焊接引线的工序；将具有第二中心窗口的第二基板附着在在中心部分配置有多个第二焊接焊盘的第二半导体芯片上的工序；为了形成使第二半导体芯片和第二基板连接的第二焊接引线的工序；将完成上述工序的第一和第二半导体芯片的背面互相连接而使它所附着的工序；形成使第一基板和第二基板连接的第三焊接引线的工序；为了覆盖第一，第二，第三焊接引线而形成封装体工序；使导电性球附着在第一基板上的工序。

Description

层叠芯片封装件的制造方法
技术领域
本发明涉及半导体芯片封装件的制造方法，更详细地说，涉及具有将多个半导体芯片层叠的构造的层叠芯片封装件的制造方法。
背景技术
随着电子设备的轻量、薄型短小化的趋势，其核心元件的封装件的高密度、精细安装化成为重要的发展趋势，另外随电子计算机的存储量增大，大容量的随机存取存储器(Random Access Memory：RAM)和闪存器(FlashMemory)的芯片尺寸自然增大，而因上述原因使封装件的研究呈现小型化的趋势。
在此，作为减小封装件尺寸提出的各种方案有将多个芯片或封装件装在一起的层叠芯片封装件(Multi Chip Package：MCP)、层叠芯片模块(Multi ChipModule：MCM)等，由于主要是将半导体芯片和封装件用平面排列的方法附着在基板上，所以在制造时存在限制。
为了克服上述限制，提出了把多个相同存储电容的芯片形成为一体层叠封装件技术，这通常称为层叠芯片封装件(Stacked Chip package)。
现在所述的层叠芯片封装件技术用单纯化的工序可以使层叠芯片封装件的制造价格下降，利于大量生产，但存在由于芯片尺寸增大设计封装件内部的引线的空间不足的缺点。
图1是说明采用现有技术的层叠芯片封装件的剖面图。
如图1所示，现有技术的层叠半导体封装件100具有利用基板110将多个半导体芯片120、130、140平面附着后进行封装的构造。
借助于粘接剂114将所述的各半导体芯片120、130、140粘着在所述基板110的上面的附着区域，在相对粘着在基板110上的面的相反面上具有形成多个焊接焊盘122、132、142的结构。此时，所述各半导体芯片120、130、140层叠成台阶状配置。另外，所述焊接焊盘122、132、142在所述半导体芯片120、130、140上面边缘部形成多个。
所述焊接焊盘122、132、142通过在基板110上面形成的导电图形112和与之对应的焊接引线124、134、144实现电气连接。
然后，为保护半导体芯片120、130、140和基板110上面形成的电气连接部分而通过封装环氧系列的封装树脂形成封装体150。
所述基板110的导电图形112是用于使半导体芯片120、130、140与焊接球160连接的配线层。
半导体芯片120、130、140通过在基板110上面形成的电路模块实现相互电气连接，半导体芯片的焊接焊盘12、22、32在连接到导电图形112上的同时，通过与焊接引线124、134、144焊接电气连接。
发明内容
但是，现有技术中，由于层叠的半导体芯片的尺寸各不相同，在把焊接焊盘边缘排列的半导体芯片只在面朝上方向层叠，而在半导体芯片尺寸相同或焊接焊盘排列在半导体芯片的中央部分时就不适用了。
另外，现有技术中，为使层叠的半导体芯片引线数目不增加，将顶部的半导体芯片和底部的半导体芯片的CS插头(chip select pin)切开，由于通过一个与CS插头连接另一个与NC插头连接使用，而存在必须有NC插头的问题。
本发明针对上述现有技术的问题而提出解决方案，其目的在于提供一种层叠芯片封装件的制造方法，该方法在中央部分分别形成焊接焊盘，并把尺寸相同的半导体芯片采用面朝上和面朝下两种方式层叠。
为达到所述目的，本发明的层叠半导体封装件的制造方法包括以下工序：将具有第一中心窗口的第一基板附着在在中心配置有多个第一焊接焊盘的第一半导体芯片上的工序；在所述第一基板的背面上形成第一阻挡台的工序；形成使第一半导体芯片和第一基板连接的第一焊接引线的工序；将具有第二中心窗口的第二基板附着在在中心配置有多个第二焊接焊盘的第二半导体芯片上的工序；在所述第二基板的背面上形成第二阻挡台的工序；形成使第二半导体芯片和第二基板连接的第二焊接引线的工序；将完成上述工序的第一和第二半导体芯片的背面互相连接的附着工序；形成使第一基板和第二基板连接的第三焊接引线的工序；覆盖第一，第二，第三焊接引线形成封装体工序；把导电性球与第一基板连接的工序。
以上所述本发明的目的和其他的特征和优点从以下对本发明的优选实施例的说明可以会变得更加清楚。
附图说明
图1是说明现有技术的层叠半导体封装件的制造方法剖面图；
图2中的a到f是说明本发明第一实施例的层叠半导体封装件的制造方法工序剖面图；
图3中的a到e是说明本发明第二实施例的层叠半导体封装件的制造方法工序剖面图。
具体实施方式
以下参照附图详细说明本发明的优选的实施例。
图2a到图2f是说明本发明第一实施例的层叠半导体封装件的制造方法工序剖面图。
本发明第一实施例的层叠半导体封装件的制造方法，如图2a所示，首先将形成中心窗口13的第一基板12附着在在中心部分配置有多个第一焊接焊盘(图中未示出)的第一半导体芯片10上。然后利用第一焊接引线14使第一焊接焊盘和第一基板12连接。
接着，如图2b所示，将形成第二中心窗口23的第二基板22附着在在中心配置有多个第二焊接焊盘(图中未示出)的第二半导体芯片20上。然后利用第二焊接引线24使第二焊接焊盘和第二基板22连接。此时，所述第一半导体芯片10和所述第二半导体芯片20具有相同尺寸。
再接着，如图2c所示，使完成上述工序的第一半导体芯片和第二半导体芯片进行焊接。此时，所述焊接工序分别使第一半导体芯片和第二半导体芯片的背面(形成有电路的面的相反面)相互连接地附着。
接着，如图2d所示，利用第三焊接引线30连接所述第一基板12和第二基板22。此时，所述第一，第二和第三焊接引线14、24、30的材料由铝或金构成。
此后，如图2e所示，对完成上述工序后的组装件进行模塑工序，从而形成分别覆盖第一、第二和第三焊接引线14、24、30的模塑体32。
最后，如图2f所示，在第一基板12的底面的结合面上焊接导电球34。此时，所述结合面的直径为150～700μm左右。另外，所述导电性球34直径为100μm～1mm左右。所述导电性球34的主要成分为锡(Sn)再加上铅(Pa)、铟(In)、铋(Bi)、金(Au)、锌(Zn)、铜(Cu)或锑(Sb)中的一种物质而形成。
图3a到图3e是说明本发明第二实施例的层叠半导体封装件的制造方法的工序剖面图。
本发明第二实施例的层叠半导体封装件的制造方法，如图3a所示，利用粘接带等(图中未示)，将形成第一中心窗口103的第一基板102粘在在中心部分配置有多个第一焊接焊盘(图中未示出)的第一半导体芯片100上。
然后，在所述第一基板102上附着第一阻挡台106以后，利用焊接工序形成连接第一焊接焊盘和第一基板102的第一焊接引线104。此时，所述第一阻挡台106有防止在此后的封装工序时第一半导体芯片100的倾斜和露出的作用。
以后，如图3b所示，利用粘接带等，将形成第二中心窗口203的第一基板202粘着在在中心部分配置多个第二焊接焊盘(图中未示出)的第二半导体芯片200上。此后，在所述第二基板202上附着第二阻挡台206以后，利用焊接工序形成连接第二焊接焊盘和第二基板202的第二焊接引线204。此时所述第二阻挡台206有防止在此后的封装工序时第二半导体芯片200发生模塑溢料(mold flash)的功能。另外，所述第一阻挡台106及第二阻挡台206采用阻焊剂(solder resist)或绝缘物质，此时，所述第一和第二阻挡台106、206为防止此后工序的模塑化合物流动而要保持20μm～1mm的厚度。
接着，如图3c所示，使完成所述焊接工序后的第一和第二半导体芯片100，200的背面相互连接后地附着后，通过焊接工序形成使第一基板102与第二基板202连接的第三焊接引线230。
然后，如图3e所示，对完成上述工序后的组装件进行模塑工序，以便形成分别覆盖第一和第二半导体芯片100，200及第一，第二和第三焊接引线104，204，230的模塑体250。此时，所述模塑工序中，如图3d所示，上部和下部模塑压模262，260的表面与第一和第二阻挡台103，203连接，防止因在朝上面方向不希望的流动而引起的第一和第二半导体芯片100，200的倾斜和露出，抑制在朝上方向上生成模塑溢出。
所述下部模型压模260和第二阻挡台202的间隙非常小，由于在第二半导体芯片方向连接粘接带起缓冲作用，所以在第二半导体芯片不发生损伤的同时，还可以抑制模塑溢出的生成。
此后，第二基板的结合面(图中未示出)上连接导电性球252。此时，所述结合面的直径在150～700μm左右。另外，所述导电性球252在100μm～1mm左右。所述导电性球252的主要成分为锡(Sn)再加上铅(Pa)、铟(In)、铋(Bi)、金(Au)、锌(Zn)、铜(Cu)或锑(Sb)中的一种物质而形成。
在本发明的第一和第二实施例，在中央部分配置多个焊接焊盘，在使具有同一尺寸的各个第一和第二半导体芯片在背面相互连接地附着以后，进行焊接引线工序和封装工序。
综上所述，在本发明中通过把在中央部各个形成的焊接焊盘在背面和尺寸相同的各个半导体芯片相互连接层叠多个，可以实现在最小面积中增加存储密度。
另外，本发明可以在不脱离其宗旨的范围内进行多种多样的变化。
虽然以上是通过本发明的实施例说明本发明，但本发明不限于这些实施例。具有在本发明技术领域通常知识的专业人员只要不脱离本发明的思想和精神，可以对本发明进行修改和变更。

Claims (3)

1.一种层叠半导体封装件的制造方法，其特征在于：包括以下工序：将具有第一中心窗口的第一基板附着在在中心配置有多个第一焊接焊盘的第一半导体芯片上的工序；在所述第一基板的背面上形成第一阻挡台的工序；形成使第一半导体芯片和第一基板连接的第一焊接引线的工序；将具有第二中心窗口的第二基板附着在在中心配置有多个第二焊接焊盘的第二半导体芯片上的工序；在所述第二基板的背面上形成第二阻挡台的工序；形成使第二半导体芯片和第二基板连接的第二焊接引线的工序；使完成上述工序后的第一和第二半导体芯片的背面互相接合地附着的工序；形成使第一基板和第二基板连接的第三焊接引线的工序；为覆盖第一、第二和第三焊接引线形成模塑体的工序；把导电性球附着在第一基板上的工序。
2.如权利要求1所述的层叠半导体封装件的制造方法，其特征在于：所述第一和第二阻挡台采用阻焊剂。
3.如权利要求1所述的层叠半导体封装件的制造方法，其特征在于：所述第一和第二阻挡台以20μm～1mm的厚度形成。
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US20030124766A1 (en) 2003-07-03
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KR100480909B1 (ko) 2005-04-07
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