CN1190836C - 复层板、半导体装置用内插器以及它们的制造方法 - Google Patents
复层板、半导体装置用内插器以及它们的制造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 82
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 56
- 239000011889 copper foil Substances 0.000 claims abstract description 46
- 239000000463 material Substances 0.000 claims abstract description 42
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 34
- 239000004020 conductor Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000007747 plating Methods 0.000 claims abstract description 15
- 239000011248 coating agent Substances 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 13
- 238000002788 crimping Methods 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 238000005096 rolling process Methods 0.000 claims description 10
- 239000000203 mixture Substances 0.000 claims description 7
- 238000000992 sputter etching Methods 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 238000005097 cold rolling Methods 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 8
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- 238000009434 installation Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
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- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- 239000011888 foil Substances 0.000 description 1
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
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Abstract
提供一种可廉价制造且具有良好特性的用于形成半导体装置用内插器的复层板、半导体装置用内插器及其制造方法。该复层板的特征在于是通过把铜箔材料、和镍箔材料或在其单面或双面上镀镍的铜箔材料以0.1~3%的轧制率压接而制成的,且上述复层板是铜/镍/铜/镍/铜的五层结构。
Description
技术领域
本发明涉及用来形成用于作为搭载半导体芯片的衬底的半导体装置的内插器的复层板、用该复层材料制造的用于半导体装置的(interposer)内插器、以及它们的制造方法。
背景技术
近年来,随着电子器件的小型、轻质和高性能化,还要求搭载在其上的半导体封装装置的小型化,已经开发了小型的半导体封装装置。于是,提出了与芯片尺寸大体同样大小的半导体装置。
日本专利特开平10-74807号公报披露了这样了半导体装置的制造方法,其示意图示于图12。在内插器100(衬底)的一个表面上搭载半导体芯片101,与衬底上的布线图案102相连接。另外,布线通过在衬底厚度方向上形成的通孔103与安装衬底侧导通,在通孔的安装衬底侧形成外部连接用的焊点104。
在上述构成的半导体装置中,内插器的两个表面的导通是在通孔形成之后用电镀等填充导电物质而实现的。但是,有形成微小的通孔和向其电镀的工序,存在技术上的困难,而且由于进行比较厚的电镀,成本也增加的问题。
本发明正是鉴于上述问题而提出的,其目的在于提供可廉价制造且具有良好特性的形成半导体装置用内插器的复层板、用它制造的半导体装置用内插器以及它们的制造方法。
发明内容
本发明的典型方案可概括如下:
(1)一种用于形成半导体装置用内插器的复层板,其特征在于是通过把铜箔材料、和镍箔材料或在其单面或双面上镀镍的铜箔材料以0.1~3%的轧制率压接而制成的,且上述复层板是铜/镍/铜/镍/铜的五层结构。
(2)一种如(1)所述的用于形成半导体装置用内插器的复层板的制造方法,其特征在于:上述用于形成半导体装置用内插器的复层板是通过在真空槽内将上述铜箔和上述镍箔或镀镍层的接合面预先活性化处理之后,把上述铜箔和上述镍箔材料或镀镍层层叠起来并以0.1~3%的轧制率冷轧接合而成的,而且上述活性化处理如下进行,即,(1)在1×101~1×10-2Pa的极低压的不活泼气体气氛中;(2)以具有接合面的上述铜箔和上述镀镍层作为分别接地的电极A,并在它和另一被绝缘支撑的电极B之间施加1~50MHz的交流电,进行辉光放电;(3)在因上述辉光放电生成的等离子体中露出的电极的面积是电极B的面积的1/3以下;(4)进行溅射蚀刻处理。
(3)一种半导体装置用内插器,其特征在于:对如(1)所述的复层板从两面进行选择性蚀刻,分别形成与半导体芯片连接用的凸点、布线层,使用各向异性导电粘接剂实现半导体芯片与布线层的连接,借助于通过蚀刻形成的柱状导体实现内插器厚度方向上的导通。
(4)一种半导体装置用内插器的制造方法,其特征在于包括下列工序:形成用于形成半导体装置用内插器的复层板,该复层板是通过把形成导体层等的铜箔材料和形成蚀刻停止层的镍箔材料或镀镍层层叠起来并以0.1~3%的轧制率进行压接而形成的;从两面对该复层板选择性蚀刻,分别形成柱状导体;在该复层板的要与半导体芯片相连的一侧形成布线层;以及在与形成布线层的一侧相反的一侧上形成绝缘层,且使上述柱状导体露出,并在上述柱状导体上形成凸点。
附图说明
图1是根据本发明的一实施方案的半导体装置用内插器的制造方法的工序说明图;
图2是根据本发明的一实施方案的半导体装置用内插器的制造方法的工序说明图;
图3是根据本发明的一实施方案的半导体装置用内插器的制造方法的工序说明图;
图4是根据本发明的一实施方案的半导体装置用内插器的制造方法的工序说明图;
图5是根据本发明的一实施方案的半导体装置用内插器的制造方法的工序说明图;
图6是根据本发明的一实施方案的半导体装置用内插器的制造方法的工序说明图;
图7是根据本发明的一实施方案的半导体装置用内插器的制造方法的工序说明图;
图8是根据本发明的一实施方案的半导体装置用内插器的制造方法的工序说明图;
图9是根据本发明的一实施方案的半导体装置用内插器的制造方法的工序说明图;
图10是根据本发明的一实施方案的半导体装置用内插器的制造方法的工序说明图;
图11是复层板的制造装置的剖面正视图;
图12是现有的半导体装置用内插器的剖面图。
具体实施方式
下面,参照图1~10所示的一实施方案,详细说明本发明。首先,参照图10说明根据本发明的一实施方案的半导体装置的构造。
如图所示,在铜箔构成的布线层10(厚度优选为10~100μm)的两个表面上接合由镀镍层形成的蚀刻停止层11、12(厚度优选为0.1~0.3μm)。在布线层10的搭载半导体芯片1侧的前端形成与半导体芯片1连接用的凸点18(厚度优选为10~100μm)。在布线层的安装衬底侧形成绝缘树脂13,通过柱状导体17(厚度优选为10~100μm)与安装面导通,在安装面上形成焊点2。
然后,说明上述的半导体装置用内插器的制造方法。首先,在作为制造半导体装置用内插器时的内部导体层10的铜箔19(厚度优选为10~100μm)的两个表面上形成作为蚀刻停止层11、12的镀镍层20、21,制造镀镍的铜箔材料22(参见图1)。
然后,在图11所示的复层板制造装置中把镀镍的铜箔材料22卷在卷送辊23上。而且,把作为柱状导体17的铜箔材料24卷在卷送辊25上。从卷送辊23、25同时卷送镀镍的铜箔材料22和铜箔材料24,其一部分卷在在蚀刻停止层26内突出的电极辊27、28上,在蚀刻室26内进行溅射蚀刻处理而活性化。
此时,活性化处理可以象本发明人在在先的日本专利特开平1-224184号公报中公开的那样进行,即,(1)在1×101~1×10-2Pa的报低压的不活泼气体气氛中;(2)以具有接合面的镀镍的铜箔材料22和铜箔材24作为分别接地的电极A,并在它和另一被绝缘支撑的电极B之间施加1~50MHz的交流电,进行辉光放电;(3)在因上述辉光放电生成的等离子体中露出的电极的面积是电极B的面积的1/3以下;(4)进行溅射蚀刻处理。
然后,用设置在真空槽29内的轧制单元30进行冷轧接合,从卷送辊32上取出具有三层结构的用于形成半导体装置用内插器的复层板31。
接着,把该具有三层结构的用于形成半导体装置用内插器的复层板31再次卷到卷送辊23上。还把作为连接用凸点18的铜箔材料33(参见图1)也卷在卷送辊25上。从卷送辊23、25同时卷送镀镍的铜箔材料22和铜箔材料24,其一部分卷在在蚀刻停止层26内突出的电极辊27、28上,在蚀刻室26内进行溅射蚀刻处理而活性化。
此时,活性化处理可以象本发明人在在先的日本专利特开平1-224184号公报中公开的那样进行,即,(1)在1×101~1×10-2Pa的极低压的不活泼气体气氛中;(2)以具有接合面的复层板31和铜箔材料33作为分别接地的电极A,并在它和另一被绝缘支撑的电极B之间施加1~50MHz的交流电,进行辉光放电;(3)在因上述辉光放电生成的等离子体中露出的电极的面积是电极B的面积的1/3以下;(4)进行溅射蚀刻处理,如图1所示,制成具有五层结构的半导体装置用复层板34。
另外,虽然在上面以对在铜箔材料上预先镀镍的情况进行压接为例进行了说明,但是不用镀镍而是用上述设备把镍箔压接在铜箔材料上的情况也是可以的。此时也可采用在铜箔材料的两个表面上都压接镍箔的情况。
另外,通过使用上述设备反复进行压接,可以制造以铜层为表面层和背面层,以镍层为夹在中间的层的依次为铜/镍/铜/镍/铜的多层复层板。
而且,可以通过设置三个以上的上述卷送辊,把铜箔材料和镍箔材料等放在这些卷送辊上,从三个以上的卷送辊同时供给箔材,用一次压接制造多层结构的复层板。
按所期望的尺寸切断用于形成半导体装置用内插器的复层板34后,通过参见图2~9说明的以下工序,制造半导体装置用内插器。首先,如图2所示,在铜箔材料24的表面上形成光刻胶膜35,然后曝光、显影。
然后,如图3所示,对铜箔材料24进行选择性蚀刻,除去铜箔材料24,留下柱状导体17。作为蚀刻液,优选采用硫酸+过氧化氢水溶液、或过硫酸氨溶液等。
然后,如图4所示,通过选择蚀刻去除镍层20。作为蚀刻液,优选采用市场上销售的Ni蚀刻液(例如日本Mertech公司制造的MerstripN-950)。
然后,如图5所示,涂敷绝缘树脂39,作为绝缘树脂,优选采用环氧或聚酰亚胺树脂等。
接着,如图6所示,为了使树脂39的表面均匀,进行研磨,此时,柱状导体17的头部从表面上露出。另外,也可以不用上述研磨,而是用化学方法除去柱状导体上的树脂,使头部露出。
之后,如图7所示,对铜箔材料33进行选择性蚀刻,除去铜箔材料33,留下柱状导体18。作为蚀刻液,优选采用硫酸+过氧化氢水溶液、或过硫酸氨溶液等。
然后,如图8所示,通过选择蚀刻去除镍层21。作为蚀刻液,优选采用市场上销售的Ni蚀刻液(例如日本Mertech公司制造的MerstripN-950)。
之后,如图9所示,在铜箔材料的表面上形成光刻胶膜37,并曝光、显影,用氯化铁或硫酸+过氧化氢等对铜箔蚀刻处理。由此形成布线层。
如图10所示,通过含导电粒子3的各向异性导电粘接剂4把半导体芯片1连接在布线层的表面。并在与安装衬底侧的柱状导体17对应的位置形成焊点2。
产业上的可利用性
如上所述,在本发明的用于形成半导体装置用内插器的复层板中,以0.1~3%的低轧制率压接铜箔材料和镍箔材料,在单面或两面上镀镍的铜箔材料和其它铜箔材料或单面上镀镍的其它铜箔材料相层叠的状态下,以0.1~3%的低轧制率压接。由此,可以制造这样的用于形成半导体装置用内插器的复层板,即通过抑制接合界面的应力而可以保持接合界面的平坦度,而且,由于无需恢复加工性的热处理而在界面上不生成合金,其选择蚀刻性优良。
在本发明的半导体装置用内插器中,由于对上述用于形成半导体装置用内插器的复层板选择性蚀刻,形成与半导体芯片连接用的凸点、布线层,借助于通过蚀刻形成的柱状导体在内插器的厚度方向上导通,可以高效率且廉价地制造可与小型半导体装置对应的半导体装置用内插器。而且,由于通过使用含导电粒子的各向异性导电粘接剂的半导体芯片连接用凸点实现半导体芯片和布线层的连接,无需在半导体芯片上形成凸点,可望降低半导体装置的成本。
在本发明的半导体装置用内插器的制造方法中,由于通过形成把形成导体层的铜箔和形成蚀刻停止层的镍层一起层叠压接而成的半导体装置用复层板,对复层板选择性蚀刻形成柱状导体,在形成布线层的铜箔材料上形成绝缘层,在复层板的与柱状导体形成而相反一侧上形成半导体芯片连接用凸点和布线层,来制造半导体装置用内插器,可以高效率且廉价地制造可与小型半导体装置对应的半导体装置用内插器。
在本发明的用于形成半导体装置用内插器的复层板的制造方法中,由于通过在真空槽内对铜箔和镀镍层的接合面预先活性化处理,之后使铜箔和镀镍层层叠,以0.1~3%的低轧制率冷轧而形成复层板,由此,可以制造这样的用于形成半导体装置用内插器的复层板,即通过抑制接合界面的应力而可以保持接合界面的平坦度,而且,由于无需恢复加工性的热处理而在界面上不生成合金,其选择蚀刻性优良。
Claims (4)
1.一种用于形成半导体装置用内插器的复层板,其特征在于是通过把铜箔材料、和镍箔材料或在其单面或双面上镀镍的铜箔材料以0.1~3%的轧制率压接而制成的,且上述复层板是铜/镍/铜/镍/铜的五层结构。
2.一种如权利要求1所述的用于形成半导体装置用内插器的复层板的制造方法,其特征在于:上述用于形成半导体装置用内插器的复层板是通过在真空槽内将上述铜箔和上述镍箔或镀镍层的接合面预先活性化处理之后,把上述铜箔和上述镍箔材料或镀镍层层叠起来并以0.1~3%的轧制率冷轧接合而成的,而且上述活性化处理如下进行,即,(1)在1×101~1×10-2Pa的极低压的不活泼气体气氛中;(2)以具有接合面的上述铜箔和上述镀镍层作为分别接地的电极A,并在它和另一被绝缘支撑的电极B之间施加1~50MHz的交流电,进行辉光放电;(3)在因上述辉光放电生成的等离子体中露出的电极的面积是电极B的面积的1/3以下;(4)进行溅射蚀刻处理。
3.一种半导体装置用内插器,其特征在于:对如权利要求1所述的复层板从两面进行选择性蚀刻,分别形成与半导体芯片连接用的凸点、布线层,使用各向异性导电粘接剂实现半导体芯片与布线层的连接,借助于通过蚀刻形成的柱状导体实现内插器厚度方向上的导通。
4.一种半导体装置用内插器的制造方法,其特征在于包括下列工序:
形成用于形成半导体装置用内插器的复层板,该复层板是通过把形成导体层等的铜箔材料和形成蚀刻停止层的镍箔材料或镀镍层层叠起来并以0.1~3%的轧制率进行压接而形成的;
从两面对该复层板选择性蚀刻,分别形成柱状导体;
在该复层板的要与半导体芯片相连的一侧形成布线层;以及
在与形成布线层的一侧相反的一侧上形成绝缘层,且使上述柱状导体露出,并在上述柱状导体上形成凸点。
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JP4447762B2 (ja) * | 2000-10-18 | 2010-04-07 | 東洋鋼鈑株式会社 | 多層金属積層板及びその製造方法 |
JP4748340B2 (ja) * | 2001-03-22 | 2011-08-17 | 日立化成工業株式会社 | 金属薄膜層が形成された接続用導体内蔵の両面板製造方法 |
WO2003100850A1 (fr) * | 2002-05-28 | 2003-12-04 | Hitachi Chemical Co., Ltd. | Substrat, tableau de connexions, substrat pour boitier a semi-conducteur, boitier a semi-conducteur et leurs procedes de production |
JP4288912B2 (ja) * | 2002-08-08 | 2009-07-01 | 日立化成工業株式会社 | 配線板、半導体パッケージ用基板、半導体パッケージ及びそれらの製造方法 |
US7462942B2 (en) * | 2003-10-09 | 2008-12-09 | Advanpack Solutions Pte Ltd | Die pillar structures and a method of their formation |
JP4105202B2 (ja) * | 2006-09-26 | 2008-06-25 | 新光電気工業株式会社 | 半導体装置の製造方法 |
EP1986230A2 (en) * | 2007-04-25 | 2008-10-29 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing SOI substrate and method of manufacturing semiconductor device |
US20090196999A1 (en) * | 2007-12-12 | 2009-08-06 | Rohm And Haas Electronic Materials Llc | Adhesion promotion |
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JPH0755384B2 (ja) * | 1988-03-02 | 1995-06-14 | 東洋鋼板株式会社 | クラッド金属板の製造法及びその装置 |
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US4896813A (en) * | 1989-04-03 | 1990-01-30 | Toyo Kohan Co., Ltd. | Method and apparatus for cold rolling clad sheet |
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US5156923A (en) * | 1992-01-06 | 1992-10-20 | Texas Instruments Incorporated | Heat-transferring circuit substrate with limited thermal expansion and method for making |
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US5482784A (en) * | 1993-12-24 | 1996-01-09 | Mitsui Mining And Smelting Co., Ltd. | Printed circuit inner-layer copper foil and process for producing the same |
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JP2630293B2 (ja) * | 1995-02-28 | 1997-07-16 | 日本電気株式会社 | 多層配線基板 |
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US5844310A (en) * | 1996-08-09 | 1998-12-01 | Hitachi Metals, Ltd. | Heat spreader semiconductor device with heat spreader and method for producing same |
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