CN1191698C - 用于多线程数据包处理的千兆位数据包分配的方法和设备 - Google Patents

用于多线程数据包处理的千兆位数据包分配的方法和设备 Download PDF

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CN1191698C
CN1191698C CNB008192065A CN00819206A CN1191698C CN 1191698 C CN1191698 C CN 1191698C CN B008192065 A CNB008192065 A CN B008192065A CN 00819206 A CN00819206 A CN 00819206A CN 1191698 C CN1191698 C CN 1191698C
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CN1437816A (zh
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G·沃尔里奇
D·伯恩斯坦因
M·J·阿迪莱塔
D·F·胡珀
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Intel Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/102—Packet switching elements characterised by the switching fabric construction using shared medium, e.g. bus or ring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • H04L49/352—Gigabit ethernet switching [GBPS]

Abstract

一种网络处理器，其具有多个处理单元，每一个都支持访问一个接口中的共享资源的多个同步程序线程。数据包从高速端口分段获得，而且每个段被分配到一个程序线程。每个数据包可被分配给一个单独的线程、两个程序线程—一个用于头段处理另一条用于处理有效负载段—或用于数据包中不同的数据段的程序线程。就绪状态的专门输入和顺序号提供了在高速端口接收数据数所需要的帮助。专门的输入端被用于在每次循环的基础上监控来自高速端口的就绪标志。由分配的线程使用顺序号以维持数据包内的段排序，以及整个数据包向发送队列写操作的顺序。

Description

用于多线程数据包处理的千兆位数据包分配的方法和设备
技术领域
本发明通常涉及网络数据处理。
背景技术
诸如路由器之类的网络产品要求分组数据高速移动的单元，也就是，从进入的网络设备端口收集分组数据并将分组数据排队以转移至适当的转送设备端口。它们也要求处理分组数据的高速特殊控制器，也就是，分析数据并作出转送的决定。因为这些高速功能的实施通常包含ASIC或定制的设备的开发，所以这样的网络产品其灵活性被限制，而且因此会使其在对高速控制器的端口分配中显得非常严格。通常，分配每个控制器以不变的方式服务来自一个或更多给定端口的网络数据包。
发明内容
在本发明的一个方面，转送数据包括，将控制信息与从第一端口接收到的数据连接，以及使用相关的控制信息对数据排队以按照数据从第一端口接收到的相同顺序传送至第二端口。
附图说明
本发明的其它特征和优势将从以下与附图结合的描述中变得明显，其中：
图1是应用基于硬件的多线程处理器的通讯系统的框图；
图2是在图1的基于硬件的多线程处理器中应用的微引擎的框图；
图3是典型的线程任务分配的图解；
图4是图1中所示的I/O总线接口的框图；
图5是通过图4的I/O总线接口应用的总线接口单元的详细图；
图6A-6F是不同总线结构的控制和状态寄存器(CSR)的图解；
图7是描绘了两个千兆位以太网(“快”)端口与总线接口单元之间相互连接的详细图；
图8A-8C是分别对应RCV_RDY_CTL、RCV_RDY_HI和RCV_RDY_LO CSR寄存器格式的图解；
图9是接收线程以及在接收过程中它们与I/O总线接口相互作用的描绘图；
图10A和图10B是分别对应RCV_REQ FIFO和RCV_CTL_FIFO格式的图解；
图11A-11B是分别对应SOP_SEQx寄存器和ENQUEUE_SEQx寄存器格式的图解；
图12是快速端口接收过程的流程图；
图13A和图13B是描绘使用单线程模式的快速端口的接收过程部分的流程图；
图14A和图14B是描绘使用双线程(或头/体)模式的快速端口的接收过程部分的流程图；
图15A和图15B是描绘使用显性(分布式线程)模式的快速端口的接收过程部分的流程图；
图16是快速端口分组编队处理过程的流程图。
具体描述
参考图1，通讯系统10包括并行的、基于硬件的多线程处理器12。基于硬件的多线程处理器12与第一外围总线(所示为PCI总线)14、引用为I/O总线的第二外围总线以及存储器系统18相耦连。系统10对可被分解成并行的子任务或功能的任务来说特别有用。基于硬件的多线程处理器12包括多重微引擎22，每个微引擎带多重的可同时工作并可独立完成任务的硬件控制的程序线程。在所示的实施例中，有六个微引擎22a-22f，六个中的每一个微引擎就如以下将要完整描述的，能够处理四个程序线程。
基于硬件的多线程处理器12还包括处理器23，它可协助加载对其它基于硬件的多线程处理器12的资源的微码控制，并完成其它诸如处理协议、异常以及微引擎终使数据包获得更详细处理的数据包处理的额外支持之类的通用计算机类型功能。在实施例中，处理器23是StrongARM(ARM是英国ARM有限公司的商标)为核心基础的结构。处理器(或核心)23具有操作系统，处理器23可通过它调用功能以在微引擎22a-22f上操作。处理器23能使用任何支持的操作系统，较佳为实时操作系统。对于作为StrongARM结构应用的核心处理器，可使用诸如MicrosoftNT实时、VXWorks以及CUS——一种在互联网上供应的免费操作系统——之类的操作系统。
六个微引擎22a-22f，每个均用包括存储器系统18、PCI总线接口24和I/O总线接口28的共享资源操作。PCI总线接口为PCI总线14提供接口。I/O总线接口28负责对处理器12和I/O总线16的控制和接口。存储器系统18包括可通过SDRAM控制器26a被访问的同步动态随机存取存储器(SDRAM)18a，可使用SRAM控制器26b被访问的静态随机存取存储器(SRAM)18b，用于引导程序操作的非易失性示的FlashROM(快闪只读存储器))18c。SDRAM16a和SDRAM控制器26a通常用于处理大量的数据，例如，处理来自网络数据包的有效负载。SRAM18b和SRAM控制器26b在低等待时间的网络应用、快速访问任务——比如，访问查找表、处理器23的存储，以此类推的网络应用中使用。微引擎22a-22f能够执行SDRAM控制器26a或SRAM控制器18b的存储器访问指令。
基于硬件的多线程处理器12同诸如媒体访问控制器设备之类的网络设备接口，包括高速(或快速)设备31，比如千兆位以太网MAC、ATM设备或类似在I/O总线16上的设备。在所示的实施例中，高速设备是具有两个快速端口33a和33b的双重千兆位MAC设备。每个I/O总线16所附的网络设备可包括多个由处理器12服务的端口。其它诸如主机(未显示)之类可与PCI总线14相连接的设备也由处理器12服务。总的来说，作为网络处理器，处理器12可与任何类型的通讯设备或接收/发送大量数据的接口连接。起网络处理器作用的处理器12可从设备31接收分组数据的单元并如将要描述的，以并行的方式处理那些分组数据的单元。分组数据的单元可包括整个网络数据包(比如，以太网数据包)或这种数据包的部分。
处理器12的每个功能性单元与一个或更多内部总线相连接。内部总线包括将处理器23与存储控制器26a和26b以及与AMBA译码器36耦连的内部核心总线34(标为“AMBA”)。处理器12也包括将微引擎22a-22f与SRAM控制器26b耦连的专用总线38、AMBA译码器36以及F总线接口28。存储总线40将存储控制器26a和26b同总线接口24和28以及存储器系统18耦连。
参考图2，显示了22a-22f中一个典型的微引擎。微引擎22a包括存储微程序的控制存储器70。微程序通过中央处理器20加载。微引擎70还包括控制逻辑72。控制逻辑72包括指令解码器73和程序计数单元72a-72d。四个程序计数器保留在硬件中。微引擎22a也包括关联事件转换逻辑74。关联事件转换逻辑74从每一个共享资源(比如，SRAM26b、SDRAM26a或处理器核心20、控制和状态寄存器，以此类推)接收消息(比如，SEQ_#_事件_响应；FBI_事件_响应；SRAM_事件_响应；SDRAM_事件_响应；以及AMBA_事件_响应)。这些信息提供了请求的功能是否已完成的信息。基于请求的功能是否已由线程完成并发出完成的信号，线程需要等待完成的信号，而且如果线程是可操作的，则线程被列入可用线程的列表(未显示)。如先前提到的，微引擎22a能具有最多4个可用执行线路。
除了对执行线程本地化的事件信号，微引擎应用了全球化的信号状态。具备了信号状态之后，执行线程能够将信号状态广播至所有的微引擎22。微引擎中任何或何或所有的线程能转移至这些信号状态。这些信号状态可被用于确定资源的可用性或资源是否应该服务。
关联事件逻辑74具有对于四条线程的仲裁功能。在一实施例中，仲裁是一种轮流机制。然而，也可使用诸如优先权队列或加权公平队列之类的仲裁技术。微引擎22a也包括执行盒(EBOX)数据通道76，该通道包括算术逻辑单元(ALU)76a和通用寄存器(GPR)组76b。ALU76a除了移位功能外，还完成算术和逻辑功能。
微引擎22a还包括写转移外部寄存器文件78和读转移外部寄存器文件80。写转移寄存器文件78存储将要写入资源的数据。读转移寄存器文件80用于存储从资源返回的的数据。在数据到来之后或与数据到达同时，来自相应共享资源(比如，存储控制器26a、26b、或核心23)的事件信号将提供给关联事件仲裁器74，后者依次通知线程数据可用或已被发送。外部转移寄存器文件78和80都通过数据通道与EBOX76连接。在所描述的实现中，每个寄存器文件包括64个寄存器。
微引擎线程的功能性由特定用户在每个微引擎控制存储器70中的应用所加载(通过核心处理器)的微码来决定。参考图3，显示了典型的线程任务分配90。通常，分配一个微引擎线程作为接收调度器92，而分配另一个作为发送调度器94。构造多个线程作为接收处理线程96和发送处理(或“填充”)线程98。其它的线程任务分配包括发送仲裁器100和一个或更多核心通讯线程102。一旦运行，线程将独立地完成其功能。
接收调度器线程92将数据包分配给接收处理线程96。举例来说，在网桥/路由器的分组转送应用中，接收处理线程分析数据包的表头并基于数据包表头信息完成查表。一旦接收处理线程或多个线程96已经处理了数据包，它发送作为将进一步被核心23处理的异常的数据包(比如，转送的信息不能在查找表中找到而核心处理器又必须获取它)，或者将数据包存入SDRAM并通过在由表头/查找指示的发送(转送口)相关的发送队列内放置对该数据包的数据包连接描述符，将数据包排入发送队列。传送队列被存入SRAM。发送仲裁器线程100赋予发送队列优先权，且发送调度器线程94将数据包分配给发送处理线程，后者发送数据包至转送口，该转送口在接收过程中由表头/查找信息表示。
接收处理线程96可专门用于服务特定端口或可通过接收调度器线程92动态分配给端口。对于某些系统的构造，专用的分配较理想。例如，如果端口的号码与接收处理线程96的号码相同，那么它在以一对一的专用分配额方式将接收处理线程分配到端口的过程中不仅有效而且非常实用。在其它的系统构造中，动态分配可对系统资源更加有效的使用。
接收调度器线程92维持它执行的微引擎的GPR76b中的调度信息104。调度表信息104包括线程性能信息106、端口至线程的分配(列表)108和“线路忙”跟踪信息110。最小限度，线程性能信息通知接收调度器线程关于其它线程为何种类型的任务配置，比如，哪些线程起接收处理线程的作用。另外，它可向接收调度器传达其它适于特殊端口服务的性能。比如，可配置一个接收处理线程以支持某种协议、或特殊的一个端口或多个端口。有效接收处理线程已被接收调度器线程分配的端口的当前列表保存在线程至端口的分配列单108中。线路忙碌掩码寄存器110指示了哪些线程有效地为一个端口服务。接收调度器在选择分配给需要可用分组数据服务的端口的线程中，使用了该调度表的所有信息，以下将会进一步地详细描述。
参考图4，I/O总线接口28包括与入队/出队引擎接口122和总线接口单元124耦连的共享资源120。总线接口单元124包括与就绪总线128相连的就绪总线控制器126和用于连接一部分被称为F总线132的I/O总线的F总线控制器130。合起来说，就绪总线128与F总线132组成了I/O总线16(图1)的信号。资源120除了CSR138、一个高速暂存存储器140和一个散列单元142以外，还包括两个FIFO(先入先出)、一个发送FIFO134和一个接收FIFO136。F总线132转移设备31端口和I/O总线接口28之间的数据。就绪总线128是完成几项功能的8位总线。它被用于从设备31读取有关数据可用性的控制信息，比如，以就绪状态标志的形式。它还向设备31提供流程控制信息并可用于与另外一个同F总线132相连的网络处理器12进行通讯。总线128和132都通过CSR138被微引擎22访问。CSR138用于总线配置、访问总线接口单元124和在线程间发送信号。它们也包括将要描述的几个计数器和线程状态寄存器。CSR138被微引擎22和核心23访问。接收FIFO(RFIFO)136包括保留从F总线132接收的数据的数据缓冲器，它通过微引擎22读出。发送FIFO(TFIFO)134包括保留将要被发送至F总线132的数据的数据缓冲器，它通过微引擎22写入。高速暂存存储器140被核心23和微引擎22访问，并支持多种操作，包括读操作和写操作，以及位测试、位测试/清零和增量操作。散列单元142产生48位或64位数据的散列索引，并在查找操作过程中被微引擎22访问。
处理器23和22当访问资源120的其中一个时，向入队/出队引擎接口122发出命令。入队/出队引擎接口122将命令放入队列(未显示)，仲裁服务哪些命令，并移动资源120、核心23和微引擎22之间的数据。除了为来自核心23和微引擎22的服务请求之外，入队/出队引擎122还为来自将控制信息转移至微引擎读转移寄存器22的服务请求之外，入队/出队引擎122还为来自将控制信息转移至微引擎读转移寄存器80中寄存器的就绪总线128的服务请求。
当线程向资源120发出请求时，指令被驱动至内部指令总线150之上并被放入入队/出队引擎接口122内的队列中。与接收/读取相联系的指令(诸如读取CSR之类的指令)被写入“入队”指令队列。
CSR138包括以下类型的寄存器：F总线接收和发送寄存器；F总线和就绪总线配置寄存器；就绪总线控制寄存器；散列单元配置寄存器；中断寄存器；和包括线程状态寄存器的几个杂项寄存器。那些和接收过程有关的寄存器将更详细地描述。
中断/信号寄存器包括用于线程间信令的INTER_THD_SIG寄存器。任何微引擎22或核心23内的线路能够将线程号写入该寄存器以发出线程间事件的信号。
图5中显示了F总线控制器130和就绪总线控制器126的更详细情况。就绪总线控制器126包括从MAC设备31取回MAC设备状态信息并通过就绪总线接口逻辑161经就绪总线128施加对MAC设备的流程控制的程控顺序器160。F总线控制器130包括用于从设备31转移出数据或将数据转移进设备31的F总线接口逻辑162，该接口逻辑162由发送状态机(TSM)164和接收状态机(RSM)166控制。在此处的实施例中，F总线132可配置成双向64位的总线或两条专用的32位总线。在单向的32位结构中，每个状态机有它自己的32位总线。在双向的结构中，总线的所属权通过仲裁确立。相应地，F总线控制器130还包括选择哪个状态机拥有F总线132的总线仲裁器168。
在图6A-6F中显示了一些用于编程和控制就绪总线128和F总线132以接收处理的相关CSR。参考图6A，RDYBUS_TEMPLATE_PROGx寄存器170被用于存储就绪总线定序器的指令。这些32位寄存器170a、170b和170c中的每个寄存器均包括四个8位指令字段172。参考图6B，RCV_RDY_CTL寄存器174规定了接收状态机166的工作情况。格式如下：保留字段(位31:15)174a；快速端口模式字段(位14:13)174b，它如将要描述的，规定了快速端口线程模式；自动入队保护窗口字段(位12:10)174c，它规定了由就绪总线定序器使用的自动入队保护窗口，以防止在自动入队操作(将信息压入那些寄存器)将要开始时接收调度器访问它的读转移寄存器；自动出队启动(位9)174d，它被用于启动接收就绪标志的自动入队；另一个保留字段(位8)174e；自动入队目标字段(位7:6)174f，用于规定自动入队操作的目标寄存器；信号线程启动字段(位5)174g，当被置位时表示线程在自动入队操作之后被收到信号；接收调度器线程ID(位4:0)174h，它规定了已被配置为接收调度器的微引擎线程的ID。
参考图6C，REC_FASTPORT_CTL寄存器176与从诸如端口33a和33b之类的快速端口接收分组数据有关。如将要描述的，它启动接收线程察看这两个快速端口的表头和主体线程分配的当前分配。它包括以下的字段：保留字段(位31:20)176a；FP2_HDR_THD_TD字段(位19:15)176b，它规定了快速端口2表头接收(处理)线程的ID；FP2_BODY_THD_ID字段(位14:10)176c，规定快速端口2主体接收处理线程的ID；FP1_HDR_THD_ID字段(位9:5)176d，规定快速端口1表头接收处理线程的ID；以及FP1_BODY_THD_ID字段(位4:0)176e，规定快速端口1主体处理线程ID。RSM166使用这些字段所采用的方式将在以后详细描述。
虽然没有详细描述，其它总线寄存器包括如下的：RDYBUS_TEMPLATE_CTL寄存器178(图6D)，它保持就绪总线和F总线控制器的控制信息，比如，它启动就绪总线定序器；RDYBUS_SYNCH_COUNT_DEFAULT寄存器180(图6E)，它规定了就绪总线定序器的程序周期率；以及FP_FASTPORT_CTL寄存器182(图6F)，它如将要描述的，规定了RSM166在上一个数据转移与下一个快速接收状态的采样之间必须等待多少个F总线时钟周期。
参考图7，MAC设备31提供了表示相关传送FIFO204或接收FIFO206中的数据量是否已达到某个阈级的发送状态标志200和接收状态标志202。就绪总线定序器160定时地轮询就绪标志(在通过标志选择208选择接收就绪标志202或发送就绪标志200之后)并通过在就绪总线数据线209上转移标志数据，将它们放入适当的一个CSR138中。在本该实施例中，就绪总线包括8条将标志数据从每个端口转移至F总线接口单元124的数据线。如果就绪总线定序器160被编程分别执行接收和发送就绪标志的读取指令，写入标志数据的CSR就被定义为接收就绪标志的RCV_RDY_HI/LO寄存器210和发送就绪标志的XMIT_RDY_HI/LO寄存器212。
当就绪总线定序器用适当的指令它询问MAC接收就绪标志的适当指令编程时，它从MAC设备或指令中规定的设备读取接收就绪标志并将标志放入RCV_RDY_HI寄存器210a和RCV_RDY_LO寄存器210b中，合起来即，RCV_RDY寄存器210。这些寄存器中的每一位对应I/O总线上不同的设备端口。
仍然如图中所示，总线接口单元124还支持快速MAC设备31的两个快速端口的两个快速端口接收就绪标志管脚FAST_RX1 214a和FAST_RX2 214b。这些快速端口接收就绪标志管脚由RSM166直接读取并被放入RCV_RDY_CNT寄存器216。RCV_RDY_CNT寄存器216是几个被接收调度器线程使用以确定如何发出接收请求的216a；位27被定义为就绪总线主控字段216b并被用于表示就绪总线128被配置成主控字段还是从动字段；对应位26的字段216c提供了流程控制信息；位25和24分别对应FRDY2字段216d和FRDY1字段216e。FRDY2 216d和FRDY1 216e分别用于存储FAST_RX2管脚214b和FAST_RX1管脚214a的值，都通过RSM166的每个F总线时钟周期来取样；位23:16对应保留字段216f；接收请求计数字段(位15:8)216g规定了接收请求计数，它在RSM166完成接收请求并且数据已在RFIFO136中之后增1；接收就绪计数字段(位7:0)216h规定了接收就绪计数，它是一个8位的计数器，每次就绪总线定序器160将就绪总线寄存器——RCV_RDY_CNT寄存器216、RCV_RDY_LO寄存器210b和RCV_RDY_HI寄存器210a上的信息写入接收调度器读转移寄存器中时，它就增1。
对于读取就绪总线的寄存器有两种技术：“自动入队”和轮询。自动入队指令可在接收过程(接收自动入队)或发送过程(发送自动入队)中由就绪总线定序器160来执行。轮询要求，微引擎线路定时地对I/O总线接口28发出读引导。
接收自动入队操作完成若干功能。它将RCV_RDY_CNT寄存器216中的接收就绪计数器增1。如果通过RCV_RDY_CTL寄存器174启动，它可自动将RCV_RDY_CNT 216、RCV_RDY_LO和RCV_RDY_HI寄存器210b和210a上的信息写入接收调度器读转移寄存器80(图2)并当接收自动入队操作完成后向接收调度器线程92发出信号(通过关联事件信号)。
就绪总线定序器160定时并与发生在处理器12中的其它事件异步地轮询MACFIFO接收就绪标志。理想地，轮询MAC FIFO接收就绪标志的速率大于数据到达MAC设备端口的最大速率。因此，接收调度器线程92必须确定由就绪总线定序器160读取的MAC FIFO接收就绪标志是不是新的，或它们是否已被读取了。每次接收自动入队的指令执行时，该指令就将RCV_RDY_CNT寄存器216中的接收就绪计数器增1。RCV_RDY_CNT寄存器216可通过接收调度器线程92被用于确定规定的标志状态是否必须估算或者因为已发出接收请求同时端口正被服务，它们是否可以被忽略。例如，如果设置了用于千兆位的以太网端口的FIFO阈值，使得当64字节的数据在MAC接收FIFO 206中时发出了接收就绪标志，则直到下一个64字节到达5120ns之后标志的状态才变化。如果定序器160被编程在每5120ns阶段中采集四次标志，那么下面三个通过就绪总线定序器160采集的就绪标志可被忽略。
当接收就绪计数器被用于监测接收就绪标志的新鲜性时，有这个可能，当接收就绪标志提供新的状态时，接收就绪标志被忽略。对于就绪标志新鲜性更准确的确定，可使用接收请求计数器。每次完成接收请求并且接收控制信息被压入RCV_CNTL寄存器232之中时，RSM166将接收请求计数器增1。在就绪总线定序器第一次执行每个程序循环的接收就绪指令时，在RCV_RDY_CNT寄存器中记录了计数。接收调度器线程92能使用该计数以跟踪接收状态机已完成了多少次请求。因为接收调度器线程发出了指令，它能够维持它所提交的一个接收请求列表以及与每一个这样的请求相关的一列端口。
参考图8B和8C，寄存器RCV_RDY_HI 210a和RCV_RDY_LO 210b分别具有对应每一个端口的标志位217a和217b。
参考图9，接收调度器线程92以保证RSM166总是忙碌的速率执行它的任务，也就是，总有接收请求等待被RSM166处理。以下为几个由接收调度器92完成的任务。接收调度器92通过分别读取RCV_RDY_HI、RCV_RDY_LO和RCV_RDY_CNT寄存器210a、210b和216确定哪个端口需要服务。接收调度器92还通过使用上述RCV_RDY_CNT中的接收请求计数或接收就绪计数来决定哪个接收就绪标志是新的。它通过读取线程的已完成状态CSR240来跟踪其它微引擎线程的线程处理状态。接收调度器线程92经就绪总线对在F总线132对面的转移器进行初始化，同时接收状态机器166在F总线132上完成了准确的读转移。接收调度器92通过两个FBI CSR138：一个RCV_REQ寄存器230和RCV_CNTL寄存器232与接收状态机器166接口。RCV_REQ寄存器230指导接收状态机该怎样从F总线132接收数据。
仍旧参考图9，显示了对F总线接收转移器进行初始化的过程。已从RCV_RDY_HI/LO寄存器210a和210b接收了就绪状态信息，以及从线程已完成寄存器240接收了线程的可用性(交互动作1，由箭头标志“1”表示)，接收调度器线程92判定在RCV_REQ FIFO 230中是否有给另一个接收请求的空间。如果它判定RCV_REQFIFO 230有接收一个请求的空间，则接收调度器线程92通过压入数据将接收请求写入RCV_REQ FIFO 230中(交互动作2)。RSM166处理RCV_REQ FIFO 230中的请求(交互动作3)。RSM166通过将请求的数据移入RFIFO 136(交互动作4)，向RCV_CTL FIFO232写入相关的控制信息(交互动作5)，以及向接收请求中规定的接收处理线程96发出开始接收的信号事件(交互动件6)来响应请求。RFIFO 136包括16个单元241，每个单元用于存储64字节的单元或在此处称为MAC数据包(“MPKT”)的数据段。RSM166从大小为一个或两个RFIFO单元的分段MAC端口读取数据包。规定的接收处理线程96通过从RCV_CTL寄存器232读取控制信息(交互动件7)来响应信号事件。它使用控制信息在其它数据处于RFIFO 136中的信息中作决定。接收处理线程96将取数据包。规定的接收处理线程96通过从RCV_CTL寄存器232读取控制信息(交互动件7)来响应信号事件。它使用控制信息在其它数据处于RFIFO 136中的信息中作决定。接收处理线程96将从四倍字长界限上的RFIFO 136读进其读转移寄存器或直接将数据移入SDRAM(交互动作8)。
RCV_REQ寄存器230被用来对F总线上的接收转移进行初始化，并被映射至由微引擎写操作的双入口FIFO。I/O总线接口28向接收调度器线程发出信号，表示RCV_REQ FIFO 236具有另一个接收请求的可用空间，并且上一个发出的请求已被存入RCV_REQ寄存器230中。
参考图10A，RCV_REQ FIFO 230包括两个入口231。每个入口231的格式如下。前两位对应保留字段230a。位29是规定完成该请求的F总线访问的最大数目的FA字段230b。THSG字段(位28:27)230c是两位线程消息字段，它使调度器线程通过就绪状态机传送消息至分配的接收线程，该就绪状态机器将此消息复制给RCV_CNTL寄存器。在状态信息转移至以下的EOP MPKT的情况中，使用SL字段230d(位26)。它表示在32位F总线的配置中需要两根还是一根32位总线访问。E1字段230e(位21:18)和E2字段(位25:22)230f规定了接收转移数据的RFIFO单元。如果只接收到一个MPKT，它就被放入由E1字段表示的单元中。如果接收到两个MPKT，则两个MPKT被放入由E2字段表示的RFIFO单元中。FS字段(位17:16)230g规定了是使用快速端口模式还是慢速端口模式，即，请求直接到快速端口还是到慢速端口。快速端口模式设置向RSM表示，顺序号与请求相关，以及顺序号将处理推测请求，这些将在以后详细描述。NFE字段(位15)230h规定了被填充的RFIFO单元的数目(比如，一个或两个单元)。不管快速就绪标志管脚的状态，只有当选择了快速端口模式并向RSM表示它应该处理请求时，才使用IGFR字段(位13)230i。SIGRS字段(位11)230j，如果被设置了，则表示，只要接收请求一完成，就要向接收调度器发出信号。TID字段(位10:6)230k规定了在处理接收请求之后通知或向它发出信号的接收线程。因此，如果位11被置位，在RCV_REQ入口可从RCV_REQ FIFO除去之前，它必须被读两次，一次被接收线程读一次被接收调度器线程读。RM字段(位5:3)2301规定了已被接收调度表选中的MAC设备的ID。最后一个，RP字段(位2:0)230m规定了在RM字段2301中规定的MAC设备的哪个端口被选中。
RSM166读取RCV_REQ寄存器的入口231以决定它应该怎样从F总线132接收数据，即，信号的发送该怎样在F总线上完成，数据应该被放入RFIFO中，而微引擎在接收到数据后应该收到信号。RSM166在RCV_REQ FIFO 230中搜索有效的接收请求。它选择了RM字段中识别的MAC设备并通过施加适当的控制信号选择MAC中规定的端口。它随后开始在F总线数据线上接收来自MAC设备的数据。接收状态机总是准备在F总线上如接收请求中规定的从MAC设备读取8个或9个四倍字长的数据。如果MAC设备发出了EOP信号，RSM166就早一点终止接收(在完成8个或9个访问之前)。RSM166计算用于每个请求而接收的总字节并报告RCV_CNTL寄存器232中值。如果收到EOP，RSM166就确定在上一次接收数据的周期中有效字节的数目。
RCV_CNTL寄存器232映射到通过接收状态机写、通过微引擎线路读的四入口FIFO(在此处称为RCV_CNTL_FIFO 232)。I/O总线接口28当有效入口到达RCV_CNTL FIFO顶部时向分配的线程发出信号。当微引擎线路读取RCV_CNTL寄存器时，数据从FIFO被弹出。如果SIGRS字段230i在RCV_REQ寄存器230中被设置，除了向TID字段230k中规定的线程发出信号以外，也向RCV_CNTL寄存器232中规定的接收调度器线程92发出了信号。在这种情况下，RCV_CNTL寄存器232中的数据在接收请求数据从RCV_CNTL FIFO 232退出前被读取两次，并且向下一个线程发出信号。只要FIFO不满，接收状态机就会向RCV_CNTL寄存器232写数据。如果RCV_CNTL FIFO 232满了，接收状态机便拖延并停止接受任何更多的请求。
参考图10B，RCV_CNTL FIFO 232向接收信号的线程(也就是，在TID中规定的线路)提供指令处理数据。如以上所表示的，RCV_CNTL FIFO包括4个入口233。RCV_CNTL FIFO入口233的格式如下：THMSG字段(31:30)23a包括由RSM从RCV_REQ寄存器[28:27]复制的2位消息。MACPORT/THD字段(位29:24)232b规定了MAC端口号或接受线程的ID，这将在以后进行详细地描述。SOP SEQ字段(23:20)232c用于快速端口，而且如果SOP(分组开始)在接受数据转移的过程中被加载，则该字段表示作为SOP顺序号的分组顺序号，如果SOP没有被加载，则该字段表示MPKT顺序号。RF字段232d和RERR字段232e(分别为位19和18)都传送接受错误信息。SE字段232f(17:14)和FE字段232g(13:10)都分别是RCV_REQ的E2和E1字段的复制品。EF字段(位9)232h规定了由接收请求填充的RFIFO单元的数目。SN字段(位8)232i用于快速端口并表示SOP_SEQ字段232c中规定的顺序号与快速端口1相关还是与快速端口2相关。如果RFIFO单元包含在EOP MPKT中，则VLD BYTES字段(7:2)232j规定了该单元中有效
可使用CSR指令通过线程对线程完成寄存器240进行读和写。使用这样的寄存器，接收调度器线程能决定哪个RFIFO单元未被使用。THREAD_DONE CSR240支持用于每个微引擎线程的两位消息。分配的接受线程可向该寄存器写入两位的消息，表示它已完成任务。每次消息被写入THREAD_DONE寄存器，当前的消息就与新的消息逻辑或。THREAD_DONE寄存器中的位值通过写“1”而清除，因此可通过向THREAD_DONE寄存器写入读回的数据使调度器可清除消息。两位状态字段的定义由软件确定。
分配的接收处理线程无论状态在何时变化都将它们的状态写入THREAD_DONE寄存器。当接收调度器读取THREAD_DONE寄存器时，它可查看返回值以决定每个线程的状态并更新它的线程/端口分配列表。
快速端口的包速率(即，千兆位端口)是这样的，接收状态机从单一端口读取MPKT的速率是这样快，以至于接收线程不能够在接收状态机从相同的端口带来另一个MPKT之前处理MPKT。也就是说，快速端口可需要使用一些RFIFO单元并并行地接收线程以维持全线路速率。一个MPKT需要的处理量可包括表头处理(即，表头修改，向前搜索)或简单地将数据包体碎片移向存储器。
快速数据包以及，一些情况中的快速MPKT(例如，构成从快速端口接收的数据包的MPKT)可并行地并由不同的线程处理，因此需要对给定的端口维持数据包内的顺序和数据包间的顺序。从而，为了维持从快速端口接收的数据包的包数据顺序，网络处理器12使用一组用于高速端口的顺序号。每组顺序号提供网络数据包的顺序号、MPKT顺序号和入队的顺序号。这些顺序号以4位计数器在I/O总线接口28内维持并在它们到达十五时自动翻转至零。
顺序号在F总线接收寄存器(CSR)中保持。参考图11A，顺序号寄存器270包括具有SOP_SEQ1字段273的SOP_SEQ1寄存器272和具有SOP_SEQ2字段275的SOP_SEQ2寄存器274。这些字段存储它们相应的第一端口的SOP顺序号并通过RSM增1。参考图11B，入队顺序号寄存器276包括具有存储快速端口1入队顺序号的ENQUEUE_SEQ1字段279的ENQUEUE_SEQ1寄存器278，和包括存储快速端口2入队SOP顺序号的ENQUEUE_SEQ2字段281的ENQUEUE_SEQ2寄存器280。入队顺序号通过接收处理线程增1。
在SOP_SEQ1寄存器(快速端口1)或SOP_SEQ2寄存器(快速端口2)中的网络数据包顺序号被放入RCV_CNTL寄存器并同时被增1。接收状态机器以一定的方式对数据包顺序号增1，该方式允许接收处理线程不仅仅跟踪网络数据包的序列络数据包顺序号被放入RCV_CNTL寄存器并同时被增1。接收状态机器以一定的方式对数据包顺序号增1，该方式允许接收处理线程不仅仅跟踪网络数据包的序列还跟踪单独MPKT的序列。如果SOP信号在接收请求中被检测到，则网络数据包顺序号在网络数据包的基础上提供顺序号(下文中称为SOP顺序号)。如果在接收请求中未检测到SOP信号，那么数据包顺序号以MPKT为基础(在下文中，称为MPKT顺序号)。由于RCV_CNTL寄存器包含数据包顺序号和SOP状态，所以接收线路可确定数据包顺序号的类型。
每个快速端口的SOP和MPKT顺序号以4位计数器实现。SOP顺序号计数器在每次检测到SOP时增1。MPKT顺序号计数器无论SOP信号在何时加载都会接收SOP顺序号，当未检测到SOP信号时只要每收到请求就增1。
由接收处理线程，使用入队顺序号确定是否轮到这些顺序号将完整的网络数据包放至传送队列上。当接收到完整的网络数据包时，接收处理线程从适当的入列顺序号寄存器读取入队顺序号。如果入队顺序号与分配给数据包的SOP顺序号匹配，那么接收处理线程能将数据包放到发送队列。如果入队顺序号不匹配，那么接收处理线程等待“顺序号变化”信号事件发生。当事件发生时，接收处理线程再次读取入队顺序号并核对其是否匹配。如果匹配发生，则数据包可被放到发送队列。
在数据包放到发送队列之后，接收处理线程将入队顺序号增1。入队顺序号通过向ENQUEUE_SEQ1或ENQUEUE_SEQ2寄存器写入来增1。接收处理线程可选择将它的处理状态写入THREAD_DONE寄存器，以及同时将入队顺序号增1。这可用向附加CSR、THREAD_DONE_INCR1寄存器或THREAD_DONE_INCR2寄存器(未显示)的单个写指令来完成。
接收调度器线程控制它发出接收请求的速率。它发出不超过端口所需求的一些接收请求，但足够防止端口的接收FIFO的溢出。
当使用诸如10/100BaseT以太网端口之类的较慢端口时，接收调度器线程读取用于多个端口的MAC接收FIFO就绪标志，确定哪个端口有数据供应，并在知道数据在MAC接收FIFO中可供使用的基础上发出接收的请求。由于它每次都读取多个的接收FIFO就绪标志，因此它能够在必须再次读取标志之前发出多个接收请求。因为快速端口以远高于缓慢端口的数据速率操作，而且与某些任务相关的等待时间，(比如，从端口或从RCV_RDY_HI/LO寄存器读取接收就绪标志，向RCV_REQ写入接收请求)可远大于数据包到达的速率，因此单个MAC端口必须服务的速率不能只凭借当获知数据已在设备端口的接收FIFO中可供使用时发出接收请求来维持。
因此，接收调度器线程使用高速端口的推测请求。也就是说，接收调度器线程在推测端口的接收FIFO中有数据可供使用的基础上向端口发出多个接收请求。在RSM166处理每个接收请求的时候，它判定在端口是否真的有数据供应。在这个判定的基础上，RSM166处理或者取消该请求。
RSM166通过读取快速接收就绪管脚(图7的FAST_RX1 214a和FAST_RX2214b)来确定在两个快速端口之中是否有数据供应。这些管脚214a和214b提供了对它们各自MAC端口的接收FIFO就绪标志的直接连接。当到达接收FIFO饱和阈值级或已收到完成的数据包时，MAC端口加载这些信号。
如果快速就绪管脚没有被加载，RSM166取消待处理的请求并向RCV_CNTL寄存器的消息字段中写入取消消息。它随后向指定的接收处理线程发出信号。接收处理线程被编程以读取RCV_CNTL寄存器，准确地译出取消消息并向接收调度器线程表示它可供应给其它的任务。
两个快速就绪管脚的状态在RCV_RDY_CNT寄存器216(未在图8A中显示)的FRDY2字段216d(端口2)和FRDY1字段216e(端口1)表示。接收调度器线程从RCV_RDY_CNT寄存器216定时地读取快速就绪标志字段216d和216e，确定它何时应该收到请求。它发出足够的接收请求以覆盖可能在从上一次它读取快速就绪标志以来已到达MAC端口33的数据。
接收状态机166支持三种快速端口模式，该模式确定接收处理线程该怎样分配给RFIFO中的处理分组数据。这些快速端口模式被称为单线程模式、头/主体线程模式和显性线程模式。当选择了一个模式时，网络处理器分析以下的参数：处理每个接收请求的线程的可用性；接收线程的执行时间。模式需要了解一个网络数据在何处结束以及下一个数据包在哪里开始。为此，它们依靠对应于施加SOP的网络数据包的开始和对应于施加EOP的网络数据包的结束。回到图6B，RCV_RDY_CTL寄存器176的快速端口模式字段174b将三种模式定义为单线程‘00’、头/主体‘01’和显性‘10’。
单线程模式当使用推测请求时将单个的线程分配给每个数据包。如果在RCV_RDY_CTL寄存器176中规定了单线程模式，且设置了快速端口模式(RCV_REQ[17:16])，那么RSM166以以下的方式完成。如果RSM166在MPKT的接收数据转移中检测到SOP，那么它向在RCV_REQ寄存器230中规定的线程发出信号。也就是说，它将规定的线程的线程ID写入TID字段230k。它还保存在REC_FASTPORT_CTL寄存器176的适当头字段中的线程ID。如果没有检测到SOP，那么RSM166忽略RCV_REQ寄存器中规定的线程ID并用信号通知在REC_FASTPORT_CTL寄存器的头字段中规定的线程。RSM166将未使用的线程ID写入RCV_CNTL寄存器的MACPORT/THD字段232b。未使用的ID被返回到接收调度器线程，因此接收调度器线程能够更新它的线程可用性的列表。为了返回线程ID，当完成接收请求且接收线程将不使用的线程ID通过使用线程间通讯传递给接收调度器时，RSM166发出信号通知接收线程。还有一种选择，接收调度器可以要求在RSM完成接收请求之后，向它以及向接收处理线程发出信号。在这种情况下，RCV_CNTL必须在数据从RCV_CNTL FIFO去除前被读取两次。在多数情况下，接收处理线程读取它一次，而接收调度器线程也读取它一次。如果没有完成两次读操作，则RSM停止。在另一种选择中，当接收请求完成且接收处理线程通过使用线程间信号寄存器将不使用的线程返回给接收调度器线程时，RSM向接收处理线程发出信号，其中的线程间信号寄存器，如同线程完成寄存器一样，对每个线程有一个位且由接收调度器定时地读取以确定线程的可用性。它将那个寄存器中不使用的线程ID所对应的位置位，而该寄存器随后由接收调度器线程读取。
在头/主体模式中，指定两条线程处理网络数据包中的MPKT。第一条线程起头线程的作用并负责处理表头以决定怎样转送数据包。第二条线程是主体线路，负责将数据包的剩余数据移至SDRAM。当主体线程完成它的任务时，它使用在线程间的信令来通知头线程数据包的主体在何处。头线程随后将数据包放入发送队列中。
RSM166以以下的方式支持头线程和主体线程。如果RSM166检测到SOP，它就向RCV_REQ寄存器中规定的线程发出信号并在REC_FASTPORT_CTL寄存器176的头字段中保存线程号。当它处理下一个请求时，它向RCV_REQ寄存器230中规定的线程发出信号并在REC_FAST_PORT_CTL寄存器176的主体字段中保存线程号。从这一点以后，RSM忽略存在于RCV_REQ寄存器230中的线程ID并向REC_FASTPORT_CTL寄存器176中规定的体线程发出信号。RSM将未使用的线程ID写入RCV_CNTL寄存器的MACPORT/THD字段232b中。如同用单线程模式一样，未使用的线程ID被返回到接收调度器线程，这样接收调度器线程知道，该线程可用于处理。分配的线程发出信号，它已完成，异常是列中的最后一个线程，它收到的为头线程的线程ID。另外，每个线程为下一个分配的线程提供缓冲存储器的指针，由此保证给定的网络数据包的MPKT以它们到来的顺序在分组存储器中排列。一旦分配给EOP MPKT的线程已完成处理并通过先前MPKT的线程发出信号，它便会通知头线程，整个数据包可被排入发送队列中，也就是说，只要入队顺序号跟由头线程处理的MPKT的SOP顺序号匹配。提供MPKT顺序号以保证MPKT以正确的顺序排队。
参考图12，显示了选中的快速端口的快速端口接收处理的总览图300。接收调度器线程选择或分配可用线程给端口302并发出规定分配线程的接收请求304。如虚线所示，在显性模式中，调度器选中第二线程作为下一个接收请求中分配的线程并在将要写入的RFIFO存储单元所对应指定的存储位置中存储该第二条线程306。RSM检查快速就绪标志的快速端口308。RSM确定其是否被加载310。如果被加载，则RSM处理接收请求312，并通过转移请求的MPKT至由请求指示的RFIFO存储单元中来响应请求314，并完成步骤：将RVC_CNTL FIFO入口(根据在RCV_RDY_CTL寄存器174中规定的快速端口模式)登记到RCV_CNTL FIFO同时发出信号通知分配的线程(任何其它的线程，比如由请求规定的调度器)316。一旦这些步骤完成，分配的接收处理线程处理由RCV_CNTL寄存器中的控制信息和快速端口模式所指示的MPKT 318。如果就绪标志未被加载，它判定在RCV_REQ入口中是否设置了IGFR字段319。如果未被设置，RSM取消请求并返回线程的ID320。如果设置了，RSM继续请求的处理。
参考图13A，316(图12)的RCV_CNTL入口登记和线程信令，对于单线程模式，包括如下。RSM判定在接收数据的周期中SOP是否被加载330。如果是的话，它便将SOP顺序号放入SOP_SEQ字段中332，将SOP_SEQx计数器增1 334，置位SOP位336，向TID字段写入规定的线程ID 338，同时将它保存在适当的快速端口的REC_FASTPORT_CTL寄存器头字段中340。它向规定的线程发出信号342。如果SOP未被加载，RSM将MPKT顺序号写入顺序号字段346，并将那个号增1 348。它将TID字段设置为在REC_FASTPORT_CTL寄存器的头字段中表示的线程的ID(也就是，曾是SOP MPKT的最后一个MPKT的TID)350。它同样将未用的接收处理线程，即由接收请求规定的线程，写入MACPORT/THD字段352。它发出信号通知分配的线程和调度器读取寄存器，分配的线程因此知道怎样处理数据包，而接收调度器线程因此知道规定的线程不被使用从而可提供给新的分配。未用的接收处理线程，即由接收请求规定的线路，写入MACPORT/THD字段352。它发出信号通知分配的线程和调度器读取寄存器，分配的线程因此知道怎样处理数据包，而接收调度器线程因此知道规定的线程不被使用从而可提供给新的分配。
参考图13B，单线程模式MPKT的处理(图12的318)如下。如果分配的处理线程确定MPKT作为SOP MPKT(如由RCV_CNTL寄存器所表示的)360，分配的处理线程分析表头362并完成查找(基于表头和从散列表取回的散列信息)364。在将存储在SDRAM转送表中的信息和MPKT中的剩余信息(比如，有效负载)转送到数据包缓存器中的临时队列的同时，它移动所有处理的表头366。如果它判定MPKT是EOP 368，则分配的线程认为，数据包准备好进入由转送信息表示的转送端口的发送队列。入队处理将参考图18进行描述。如果MPKT不是SOP，则处理线程将负载数据转移到缓存器中(在SDRAM中)372，随后判定它是否为EOP 374。如果它是EOP，则处理线程准备将数据包入队376。如果MPKT不是EOP，则处理线程发出信号，它已完成(通过信号间方法，比如，写线程完成寄存器)378。
参考图14A，线程的RCV_CNTL入口登记和信令316，对于双线程(头/主体)模式包括如下。RSM判定，在接收数据的周期中SOP是否被加载380。如果是，将SOP顺序号放入SOP_SEQx字段中382，将SOP_SEQx计数器增1 384，将规定的线程ID写入TID字段386，同时将其保存在适当的快速端口的REC_FASTPORT_CTL寄存器表头字段中388。它向规定的线程发出信号390。如果SOP未被加载，RSM将MPKT顺序号写入顺序号字段392，并将该号增1394。它判定最后一个请求是否给SOP MPKT 396。如果是的话，它就向规定的线程发出信号398，在REC_FASTPORT_CTL寄存器的适当TID字段和主体字段中设置该线程的ID 400。它也指示在MACPORT/THD字段中头线程的ID(这样，当完整的数据包被接收并被处理后，头线程可发出信号)402。如果最后的请求不是SOPMPKT，则RSM向主体字段中规定的线路发出信号404，将该ID写入TID字段406并规定MACPORT/THD字段中接收请求的未使用线程的ID(返回到可用的接收处理线程池(pool)中408。它也向调度器发出信号410，由此，除了被信号通知的接收处理线程，调度器也可在其从RCV_CNTL FIFO中移去之前读取REC_CNTL寄存器入口。
参考图14B，MPKT在双线程模式中由“分配”的线程处理如下。如果线路判定MPKT是SOP MPKT 412，则它就以上述相同的方式处理头数据和负载数据414(即，分析表头，等等)。如果它判定正在处理的MPKT是EOP，即MPKT是最小尺寸的网络数据包416，则它就认为MPKT准备好入列418。如果MPKT不是数据包中的最后一个MPKT，则线程(是头线程)等待EOP的通知420。一旦它接收到这样的通知422，数据包就准备好被放入发送队列中。如果MPKT不是SOP而是数据包的继续，则线程在SDRAM中由头线程指定的缓冲位置的临时队列中存入有效负载424。如果它判定MPKT是EOP 426，则它向调度器和头线程(如MACPORT/THD字段所确定的)发出信号已完成428。由此，它判定整个数据包现已准备好入队430。如果MPKT不是EOP，它只向调度器发出信号，它已完成处理自己的MPKT并可提供给其它的任务432。
参考图15A，线程的RCV_CNTL入口的登记和信令，对于显性模式，包括以下步骤。如在其它的快速端口模式中一样，RSM判定SOP在接收数据的周期中是否被加载440。如果是的话，它便将SOP顺序号放入SOP_SEQx字段中442，将SOP_SEQx计数器增1 444，将规定的线路ID写入TID字段446。它向规定的线路发出信号448。如果SOP未被加载，RSM将MPKT顺序号写入顺序号字段450，将该号增1 452并向规定的线路发出信号454。
参考图15B，接收线程根据显性模式处理快速端口的MPKT如下。如果规定的线程判定，MPKT是SOP MPKT 460，则规定的线路处理表头462，将有效负载和处理的表头移入缓存器464。如果它判定EOP位在RCV_CNTL寄存器入口处被置位465，则它就认为MPKT准备好入队到适当的端口发送队列466中。如果EOP未被置位，即MPKT不是EOP MPKT，则线程(在这种情况下，表头线程)将指向下一个可用缓冲位置的指针传给第二线程ID468，该第二线程的ID由对应存储MPKT的RFIFO存储单元的公用位置中的调度器规定。它随后等待来自EOP线程的通知470。如果MPKT不是SOP MPKT，则它接收指向SDRAM中缓冲位置的指针472并将MPKT入队到由指针指向的缓存器中的位置474。如果线路判定MPKT是EOP MPKT 475，则线路发出信号476，它已完成，且MPKT是EOP，这样表头线程便知道，属于该EOP MPKT的网络数据包准备好进入发送队列。如果MPKT不是EOP，处理线程将指向下一个可用的缓冲位置的指针增1 478，并将指针送至处理下一个连续MPKT的线路480，即由作为对应存储MPKT的RFIFO存储单元的储存位置中的第二线程的调度器规定的ID。
参考图16，示出了入队的处理。表头线程(如前面所描述的，由另一个线程的EOP或EOP的接收信号通知确定)先判定是否轮到该特定的数据包入队。它判定入队顺序#是否与SOP MPKT相关的SOP顺序号相同490。如果它们相同，表头线程链接网络数据包(现完整地存储在SDRAM中的数据包缓存器中)和端口传送队列(位于SRAM中)494。它将入队顺序号增1 496并通知调度器的完成498。如果SOP顺序号与入队顺序号不相同，它就等待接收指示SOP顺序号已改变的信号500，并再次比较两个顺序号。
将理解的是，在图12-16中描绘的处理过程认为，无数据包异常发生，线程能够处理数据包的处理而不需要核心处理器的帮助。这样的帮助，如果被调用，绝不会改变维持数据包顺序的方式。此外，图12-16的处理过程认为FIFO，比如RFIFO空间具备可用性。虽然在上图12-16的步骤中未描述，可以理解的是，不同的状态机必须在向该FIFO写入新入口之前判定是否有可用空间。如果特定的FIFO满了，该状态机将等待直到适当的入口号从该FIFO返回。
添加、删减和本发明较佳实施例的其它修改将在那些在该领域实际操作的例子中变得明显，并且在以下权利要求的范围中。

Claims (24)

1.一种转送数据的方法，其特征在于包括：
使控制信息与从第一端口接收到的数据相关；
由接收处理程序线程来处理数据单元以确定数据单元要被传送的第二端口；以及
使用相关的控制信息将数据入队，以与数据从第一端口接收到的相同顺序发送至第二端口。
2.权利要求1的方法，其特征在于，控制信息包括顺序号。
3.权利要求2的方法，其特征在于，该数据包括数据单元和与网络数据包相关的数据单元。
4.权利要求3的方法，其特征在于，当第一顺序号从第一端口接收到时将它们与相关的数据单元关联。
5.权利要求4的方法，其特征在于，关联还包括，维持第二顺序号，其中，使用包括：
判定第一顺序号是否与在数据单元被处理之后对数据单元排序的第二顺序号相等。
6.权利要求2的方法，其特征在于还包括：
控制将数据从第一端口到用于处理的接收处理程序线程的转移。
7.权利要求6的方法，其特征在于，控制包括：
分配接收处理程序线程以处理数据。
8.权利要求7的方法，其特征在于，控制包括：
将数据单元转送至各个分配的接收处理程序线程。
9.权利要求7的方法，其特征在于，控制包括：
将数据单元转送至各个单个分配的接收处理程序线程。
10.权利要求7的方法，其特征在于，控制包括：
由第一和第二不同的接收处理程序线程，转送用于处理的数据单元，第一处理程序线程处理包含数据包表头和一部分有效负载数据的数据单元的第一数据单元，第二接收处理程序线程处理包含有效负载数据另一部分数据单元的第二个数据单元。
11.权利要求3的方法，其特征在于，还包括：
维持用于生成数据包起始顺序号的顺序号计数器；以及
当数据单元被确认为对应于新数据包的开始时，通过将顺序号计数器的当前计数值作为数据包起始顺序号与数据单元相关联，将顺序号计数增1。
12.权利要求3的方法，其特征在于，还包括：
维持用于生成入队顺序号的入队顺序号计数；以及
在判定数据包是否准备好入队以发送至第二端口之后，将入列顺序号计数增1。
13.一种将数据从第一端口转送至第二端口的处理器，其特征在于包括：
用于执行程序线程的微引擎，该线程包括用于发出请求从而从第一端口转移数据单元的接收调度器程序线程和接收处理程序线程；
总线接口，响应微引擎，用于接收来自第一端口的数据单元并将数据单元转送至接收处理程序线程，以处理数据单元并将其按照从第一端口接收以发送至第二端口的顺序入队。
14.权利要求13的处理器，其特征在于，总线接口包括用于控制来自第一端口的数据单元转移的接收状态机。
15.一种将数据从第一端口转送至第二端口的方法，其特征在于包括：
由微引擎执行程序线程，该线程包括用于发出请求从而从第一端口转移数据单元的接收调度器程序线程和接收处理程序线程；
由总线接口响应微引擎，用于接收来自第一端口的数据单元并将数据单元转送至接收处理程序线程，以处理数据单元并将其按照从第一端口接收以发送至第二端口的顺序入队。
16.权利要求15的方法，其特征在于，总线接口使用顺序号确保数据单元以它们从第一端口接收时的顺序入队。
17.权利要求16的方法，其特征在于，当数据单元从第一端口收到时，总线接口将第一组顺序号同数据单元相关联，并维持由接收处理程序线程用来确定数据单元要入队的顺序的第二组顺序号。
18.权利要求15的方法，其特征在于，总线接口向接收调度器程序线程指示，第一端口是否有数据要被一个或更多接收处理程序线程来处理。
19.权利要求15的方法，其特征在于，接收调度器程序线程分配来自一个或更多接收处理程序线程中的可用线程以处理数据单元。
20.权利要求15的方法，其特征在于，数据单元与网络数据包相关。
21.权利要求20的方法，其特征在于，接收调度器程序线程将每个数据单元分配给不同的接收处理程序线程。
22.权利要求21的方法，其特征在于，接收状态机将数据单元转送至各个分配的不同接收处理程序线程。
23.权利要求21的方法，其特征在于，接收状态机将数据单元转送至各个单个分配的不同接收处理程序线程。
24.权利要求21的方法，其特征在于，接收状态机转送由第一和第二不同接收处理程序线程处理的数据单元，第一处理程序线程处理包含数据包表头和有效负载数据一部分的数据单元的第一个数据单元，第二接收处理程序线程处理包含有效负载数据另一部分的数据单元的第二个数据单元。
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