CN1193193A - 硅/锗硅垂直结型场效应晶体管 - Google Patents
硅/锗硅垂直结型场效应晶体管 Download PDFInfo
- Publication number
- CN1193193A CN1193193A CN98104250A CN98104250A CN1193193A CN 1193193 A CN1193193 A CN 1193193A CN 98104250 A CN98104250 A CN 98104250A CN 98104250 A CN98104250 A CN 98104250A CN 1193193 A CN1193193 A CN 1193193A
- Authority
- CN
- China
- Prior art keywords
- semiconductor layer
- layer
- window
- effect transistor
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 title claims description 16
- 239000010703 silicon Substances 0.000 title claims description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 70
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000003989 dielectric material Substances 0.000 claims description 14
- 230000008859 change Effects 0.000 claims description 11
- 239000002800 charge carrier Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 230000001965 increasing effect Effects 0.000 claims description 6
- 230000005684 electric field Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000006698 induction Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 230000009286 beneficial effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 6
- 239000000203 mixture Substances 0.000 abstract description 5
- 229910045601 alloy Inorganic materials 0.000 abstract description 4
- 239000000956 alloy Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 239000012212 insulator Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 230000032258 transport Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66916—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN heterojunction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1058—Channel region of field-effect devices of field-effect transistors with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
- H01L29/8083—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
- H01L29/8086—Thin film JFET's
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/936—Graded energy gap
Abstract
描述了一种结型场效应管及其制作方法,包括窗口中的水平半导体层以形成沟道和其中开有窗口的半导体层,它形成环绕沟道的栅电极。水平半导体层可以是在源和漏附近具有渐变组分的SiGe合金。本发明克服了形成JFET低电阻的问题,提供了很容易降到亚微米尺寸的栅长以便用于RF、微波、毫米波和逻辑电路而没有短沟道效应。
Description
本发明涉及结型场效应晶体管，更具体地涉及带有渐变SiGe合金的垂直沟道的结型场效应晶体管，渐变的SiGe合金为增大迁移率而提供应变，并在沟道的源端提供了一感应电场以加速载流子进入沟道。
在标准的金属-氧化物-硅(MOS)工艺中，场效应管速度的增强通常伴随着四件尺寸的缩小。然而，当晶体管的栅长小于0.1微米或更小时，由于不能按比例缩小其它各种参数，存在尺寸极限。短沟道效应变得很重要，而且导致载流子(电子)以低的速度在沟道的源端移动的惯性(inertial)效应也变得很重要。
在1991年5月28日授予P.M.Solomon的美国专利51019,882中描述了含有用作沟道的硅锗层的一种场效应晶体管。
已经公开了使用渐变的SiGe区以增强双极器件中的载流子加速，如1990年8月21日授予D.L.Harame等的美国专利4,951,115和1994年10月4日授予E.F.Crabbe等的美国专利5,359,912，它被转让给本申请的受让人。
已公开渐变SiGe和应变Si和SiGe层以在MOS FET器件中增强迁移率，如K.E.Ismail和F.Stern的美国专利5,534,713中所述，它已部分转让给本申请的受让人。
1994年11月22日授予A.Chantre的美国专利5,367,184中描述了具有优化的双极工作模式的垂直JFET的改进结构。为增强双极工作，提供了SiGe薄层以在n沟道中提供价带不连续性。该薄层从栅区延伸进入沟道区以从栅(基)区注入少数载流子(空穴)，垂直JFET工作不需要该SiGe薄层。
根据本发明，公开了一种结型场效应晶体管及其制作方法，包括：第一类型的第一半导体层；形成在第一半导体层上轻掺杂的第一类型的第二半导体层；形成在第二半导体层上的第三半导体层，其上开有窗口，露出一部分第二半导体层；形成在第三半导体层上的介质材料层，其上开有和第三半导体层相通的窗口；Si1-xGex的第一类型的第四半导体层，x为0至0.1，具有一定厚度，形成在第三半导体层的窗口中的第二半导体层上；Si(1-y)Gey的第一类型的第五半导体层，y可以等于0.15，它形成在第三半导体层的开口中的第四半导体层上；Si(1-z)Gez的第一类型的第六半导体层，z为0.15至0，其有一定厚度，形成在介质材料层的开口中的第五半导体层上。第一和第二类型的半导体可以分别为n和p或p和n。
本发明提供了一种用于大规模集成(LSI)的结型场效应晶体管，其沟道长度为0.1微米量级或更小，这基于硅工艺，它能工作在用于卫星、无线广域网络和通讯设备的微波和毫米波频带。
本发明还提供了一种结型场效应晶体管结构，其中栅与源自对准。
本发明还提供了一种结型场效应晶体管结构，其中栅长可轻易地降到0.1微米以下，并不受短沟道或惯性效应的影响。
本发明还提供了一种结型场效应晶体管结构，其中沟道本身由应变SiGe制成，这样轻电子有效质量易于在垂直方向输运。
本发明还提供了一种结型场效应晶体管结构，其中沟道的源侧的SiGe梯度提供了一电场以加速载流子或以高速将载流子(电子)注入沟道。
本发明还提供了一种结型场效应晶体管结构，其中沟道的漏侧的SiGe梯度降低了电场并因此增大了击穿电压和器件的可靠性，改善了饱和电流并因此增加了晶体管的增益。
本发明还提供了一种结型场效应晶体管结构，其中串联的源漏电阻可以极低，因为不需离子注入和退火即可生长高掺杂的外延层。
本发明还提供了适于体硅的体材料衬底和/或绝缘体上的硅(SOI)衬底的结型场效应晶体管结构。
本发明还提供了适于高速大规模集成(LSI)逻辑的一种结型场效应晶体管结构。
本发明还提供了一种制作垂直结型场效应晶体管的工艺，当外延层用超高真空化学汽相淀积(UHV-CVD)生长时，它不需要离子注入或任何560℃以上的高温步骤。
本发明的这些和其它特点、目的和优点参照本发明的详细描述和附图将变得很明显；其中：
图1-3是说明实现本发明一个实施例的制造步骤的剖面图；
图4是图2的顶视图；
图5是图3的顶视图；
图6是图3一部分的放大的剖视图；
图7是带有电极接触的图3实施例的剖视图的三维视图；
图8是图7的顶视图。
现参照附图，尤其是图1-3，显示了制作垂直结型场效应晶体管(JFET)10的步骤。起始衬底12可以是如二氧化硅的绝缘体，或衬底12可以是如单晶硅、锗硅或绝缘体上的硅的半导体。在衬底12上可形成掺p-的半导体单晶层14，如硅或锗硅。起始衬底12，如果是绝缘体，和层14可以通过注氧隔离(SIMOX)形成，这在本领域中是公知的，或通过链合和深刻蚀涂有氧化物的晶片和半导体载体衬底以形成绝缘体上的硅(BESOI)而形成。层14可以是重掺杂的n+层以形成图3所示的JFET10的漏电极15。
外延层16形成在层14上，它可以是掺杂的n-层以降低随后外延形成在层16上的栅层18的电容。栅层18可以是，例如Si或SiGe，p+掺杂，厚度在30-100nm之间。然后，如二氧化硅的介质层20形成在层18上，用以降低随后形成在其上的源电极21的电容。
Si或SiGe外延层的生长温度可在500-560℃之间，如果用超高真空化学汽相淀积(UHV-CVD)生长JFET10，如1994年3月24日授予B.S.Meyerson的美国专利5,298,452中所述，这将是最高的温度，该专利已转让给这里的受让人，亦在此引入作为参考。然而，该外延层不只限于UHV-CVD，也可以在700-800℃范围内用低压外延(LPE)生长。
其次，利用例如刻蚀在层20上开例如1×1μm的窗口24。然后，例如通过反应离子刻蚀(RIE)，窗口24延伸通过栅层18，它可以选择性地终止于层16。如果层18是SiGe合金，层16是Si，则在RIE过程中折射率的变化可用于停止刻蚀，如果层16被曝光。窗口24的顶视图示于图4。
1995年3月7日授予M.Arienzo等的美国专利5,395,769中描述了一种控制硅刻蚀深度的方法，它可将刻蚀终止于合适的深度，其在这里引入作为参考。
然后，SiGe的外延渐变层30在层16上的窗口24中生长。Si(1-x)Gex的渐变层30可以n-掺杂，x在层16中可以为0并作为层厚的函数变化，在上表面31处为0.1。然后在层16上生长Si1-yGey外延层34，这里y是常数约0.15。层34形成JFET10的沟道36的中心部分。然后，在层34的上表面37上生长Si(1-z)Gez的渐变外延层38，这里z为层厚的函数，在表面37处为约0.15，在层38的上表面39处为0。
层30和38中的Ge浓度分布和层34中Ge含量的选择由层14和16的晶格失配决定。JFET10中所需的层30、34和38的厚度与浓度分布将导致整个应变层30、34和38，而不产生错位以释放应变。
如果第一类型是p型，第二类型是n型则沟道36是p型。层30和38仍需以相同方式渐变。在所有方向都有应变。所谓压应变，通常是指在较小的晶格上生长较大的晶格，这样它的平面内(in-plane)晶格常数被压缩以调节下面的层晶格常数。然而，这样做使得，长在上面的层的晶格在平面内经受压应变，在垂直方向(如图6中箭头50所指的电流方向)经受拉伸应变。
层30、34和38的外延淀积或生长对层30、34和38是优选的或选择性的，在介质层20上没有诸如硅氧化物的晶核发生。其它适于作掩蔽层的氧化物在1995年6月27日授予C.Cabral，Jr等的美国专利5,427,630中有描述，它已转让给本申请受让人，并在此引入作为参考。
然后，例如Si的导电材料层44淀积在层38和介质层20上，随后如图3、5、6所示进行构图。层44可以n++重掺杂，用于提供JFET10的源电极21。
底层14和顶层44分别构成JFET10的漏电极15和源电极21。p型层18构成JFET10的栅电极19，从全部四个侧边整个包围导电沟道36。因此栅电极19对电荷载流子有很好的控制，不可能产生短沟道效应。由于栅电极19围绕沟道36的全部侧边，JFET10的调制效率被优化。然而JFET10将在沟道36的两边用栅电极19工作。
SiGe层38中Ge的梯度z和Ge含量y的选择使得在沟道36的源侧感应出电场，它加速电子并以高速将它们送到沟道36中，因此避免了惯性效应。沟道36本身是应变SiGe，因此轻电子有效质量易于在图6中箭头50所示的垂直方向输运。在沟道36的漏侧处SiGe层30的Ge的梯度x降低了电场，因此增加了击穿电压和器件的可靠性，并改进了电流饱和度因此提高了晶体管的增益。在制造和操作JFET10时只在源侧或只在漏侧部分渐变Ge是可行的。
由于栅长由p型层18的厚度决定，层18的厚度可以很容易降到0.1微米以下的尺寸，例如从0.1μm或100nm至30nm，精度约1nm。
p型层18的厚度或栅长可以从几个nm如5nm到几百nm。给出优化的范围30至100nm，主要原因是层18做得很薄，p层18的电阻较高，因此可以降低如栅的RC时间常数。短至5nm的栅长也是可行的。
由于不需要离子注入和退火即可生长高掺杂外延层，串联的源漏电阻可以极低。使用例如用SIMOX工艺制作的SOI晶片，在p型层18下增加轻掺杂n-层16和在p型层18上加介质层20，使寄生电容最小化。栅层18下面的n-层16有益于制作器件的电接触。如图3、6、7所示的JFET10的本征开关时间在栅长为50nm时小于1ps。
参考图6、7、8，可在构图的层44和介质层20上形成介质层52。通过刻蚀暴露出栅电极19，源电极21和漏电极15，在介质层52上开窗口53-55。如图7和8所示，可以淀积金属层或外延生长高掺杂多晶Si或Si/SiGe层并构图作为互连线56-58。如果互连线56-58为金属，到硅的接触可通过在400℃下金属烧结(sintering)1至5分钟形成。栅电极19和漏电极15也可分别用高掺杂的n型层14和p型层18形成，作为由反应离子刻蚀限定的互连线。JFET10可用于RF、微波或毫米波放大器电路以及高速LSI逻辑电路。
虽然已经描述和说明了一种含有栅的垂直结型场效应晶体管，该栅完全围绕沟道且栅长小至几十纳米，对本领域技术人员而言，可以做各种改进和变化而不背离本发明的范围，本发明的范围只由后面的权利要求书限定。
Claims (25)
1.一种结型场效应晶体管，包括：
第一类型的第一半导体层；
在第一半导体层上形成的轻掺杂第一类型的第二半导体层；
形成在第二半导体层上、其中开有窗口以暴露部分所述第二半导体层的第二类型的第三半导体层；
形成在所述第三半导体层上、其中开有窗口以与第三半导体中的窗口相联系的介质材料层；
Si1-xGex的第一类型的第四半导体层，其中x随厚度而增加，它形成在所述第三半导体层的所述窗口中；
形成在所述第三半导体层的所述窗口中的、Si1-yGey的第一类型的第五半导体层，其中y基本是常数；和
形成在所述介质材料层的所述窗口中的、Si1-zGez的第一类型的第六半导体层，其中z随厚度减少。
2 根据权利要求1的结型场效应管，特征在于还包括在所述第一半导体层下的绝缘衬底。
3.根据权利要求1的结型场效应管，特征在于还包括形成在所述介质材料层和所述第六半导体层上的第一类型的硅的第七半导体层。
4.根据权利要求1的结型场效应管，特征在于所述第三半导体层和所述介质材料层具有多个窗口，其中介质材料层中的窗口与所述第三半导体层中的各窗口相联系，且所述第三材料层中的窗口暴露出部分所述第二半导体层。
5.根据权利要求4的结型场效应管，特征在于还包括形成在所述介质材料层上和所述第六半导体层上的第一类型的第七半导体层，在所述多个窗口中以互连由所述第四和第五半导体层在所述多个窗口中的各个窗口形成的多个沟道。
6.根据权利要求1的结型场效应管，特征在于所述第一类型是n，第二类型是p。
7.根据权利要求1的结型场效应管，特征在于所述第一类型是p，第二类型是n。
8.根据权利要求1的结型场效应管，特征在于所述第三层具有预定的厚度，形成栅电极。
9.根据权利要求8的结型场效应晶体管，特征在于，所述厚度在30至100nm之间。
10.根据权利要求8的结型场效应晶体管，特征在于所述第三层的厚度决定了所述晶体管的沟道长度。
11.根据权利要求1的结型场效应晶体管，特征在于，所述第五层是应变的，使得轻电子有效质量的输运利于在横过所述第三层的所述第五层中完成。
12.根据权利要求1的结型场效应晶体管，特征在于，所述第六层是渐变的，由此感应出加速载流子并将载流子以高速送到所述第五层中的电场。
13.根据权利要求1的结型场效应晶体管，特征在于，所述第五层是在所述第三半导体层和所述介质材料之间的界面上延伸的所述窗口中。
14.根据权利要求1的结型场效应晶体管，特征在于，x从0增加到0.1。
15.根据权利要求1的结型场效应晶体管，特征在于，y在从约0.1到约0.3的范围内。
16.根据权利要求1的结型场效应晶体管，特征在于，z从0.15降到0。
17.一种制备结型场效应晶体管的方法，包括以下步骤：
形成第一类型的第一半导体层；
在所述第一半导体层上形成轻掺杂的第一类型的第二半导体层；
在所述第二半导体层上形成第二类型的所述第三半导体层，其中开有窗口以暴露部分所述第二半导体层；
在所述第三半导体层上形成介质材料层，其中开有与所述第三半导体层中的窗口相联系的窗口；
在所述第三半导体层的所述窗口中形成Si1-xGex的第一类型的第四半导体层，其中x随厚度增加；
在所述第三半导体层的所述窗口中形成Si1-yGey的第一类型的第五半导体层，其中y基本是常数；
在所述介质材料层的所述窗口中形成Si1-zGez的第一类型的第六半导体层，其中z随厚度而减少。
18.根据权利要求17的方法，特征在于还包括在介质材料层和所述第六半导体层上形成硅的第一类型的第七半导体层的步骤。
19.根据权利要求17的方法，特征在于还包括在介质材料层和所述第三半导体层中形成多个窗口以露出部分所述第二半导体层的步骤。
20.根据权利要求19的方法，特征在于还包括在所述介质材料层上和在所述第六半导体层上在所述多个窗口中形成第一类型的第七半导体层的步骤，它用于互连在所述多个窗口的各个窗口中由所述第四和所述第五半导体层形成的多个沟道。
21.根据权利要求17的方法，特征在于还包括在所述第四半导体层的SiGe中渐变Ge组分的步骤，由此所述第五层是应变的，使得轻电子有效质量的输运有利于在横过所述第三层的所述第五层中完成。
22.根据权利要求17的方法，特征在于还包括在所述第六层的SiGe中渐变Ge组分的步骤，由此产生感应电场以加速载流子并以高速将载流子送入所述第五层。
23.根据权利要求17的方法，特征在于所述形成第四半导体层的步骤中，x从0增加到0.1。
24.根据权利要求17的方法，特征在于在形成第五半导体层的所述步骤中，y值设定在约0.1到约0.3的范围内。
25.根据权利要求17的方法，特征在于在形成第六半导体层的步骤中，z从0.15降低到0。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/803,033 US5714777A (en) | 1997-02-19 | 1997-02-19 | Si/SiGe vertical junction field effect transistor |
| US08/803033 | 1997-02-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1193193A true CN1193193A (zh) | 1998-09-16 |
| CN1263161C CN1263161C (zh) | 2006-07-05 |
Family
ID=25185391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB981042503A Expired - Fee Related CN1263161C (zh) | 1997-02-19 | 1998-01-16 | 硅/锗硅垂直结型场效应晶体管及其制造方法 |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US5714777A (zh) |
| EP (1) | EP0860884B1 (zh) |
| JP (1) | JP2951629B2 (zh) |
| KR (1) | KR100260687B1 (zh) |
| CN (1) | CN1263161C (zh) |
| DE (1) | DE69838307T2 (zh) |
| ES (1) | ES2289768T3 (zh) |
| MY (1) | MY120718A (zh) |
| TW (1) | TW343365B (zh) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100349270C (zh) * | 2002-07-24 | 2007-11-14 | 住友电气工业株式会社 | 纵向结型场效应晶体管及其制造方法 |
| CN100379029C (zh) * | 2002-03-15 | 2008-04-02 | 住友电气工业株式会社 | 横型接合型场效应晶体管及其制造方法 |
| CN101317271B (zh) * | 2004-12-01 | 2011-08-03 | 半南实验室公司 | 宽能带隙半导体横向沟槽场效应晶体管及制造方法 |
| CN101371359B (zh) * | 2005-10-28 | 2011-11-09 | 苏伏特股份有限公司 | 在硅和硅合金中使用互补结型场效应晶体管和mos晶体管的集成电路 |
| CN101467262B (zh) * | 2006-04-04 | 2012-01-04 | 半南实验室公司 | 结势垒肖特基整流器及其制造方法 |
| CN102709323A (zh) * | 2004-10-07 | 2012-10-03 | 费查尔德半导体有限公司 | 设计带隙的mos栅功率晶体管 |
| CN101595565B (zh) * | 2006-09-18 | 2013-03-27 | 昆南诺股份有限公司 | 在垂直半导体结构上制造精密垂直和水平层的方法 |
| CN103578996A (zh) * | 2012-07-27 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | 晶体管制造方法 |
| CN104124170A (zh) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | 晶体管及其形成方法 |
| CN108258032A (zh) * | 2018-01-19 | 2018-07-06 | 重庆邮电大学 | 一种采用组合发射区的异质结双极晶体管及其制造方法 |
| CN108766967A (zh) * | 2018-05-23 | 2018-11-06 | 燕山大学 | 一种平面复合应变Si/SiGe CMOS器件及制备方法 |
Families Citing this family (82)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400808B1 (ko) * | 1997-06-24 | 2003-10-08 | 매사츄세츠 인스티튜트 오브 테크놀러지 | 그레이드된 ＧｅＳｉ층 및 평탄화를 사용한 Ｓｉ상의 Ｇｅ의 쓰레딩 전위 밀도 제어 |
| FR2765395B1 (fr) * | 1997-06-30 | 1999-09-03 | Sgs Thomson Microelectronics | Procede de realisation de grille de transistors mos a forte teneur en germanium |
| US7227176B2 (en) | 1998-04-10 | 2007-06-05 | Massachusetts Institute Of Technology | Etch stop layer system |
| US5891792A (en) * | 1998-08-14 | 1999-04-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | ESD device protection structure and process with high tilt angle GE implant |
| US6369438B1 (en) * | 1998-12-24 | 2002-04-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| US6633066B1 (en) * | 2000-01-07 | 2003-10-14 | Samsung Electronics Co., Ltd. | CMOS integrated circuit devices and substrates having unstrained silicon active layers |
| US6602613B1 (en) | 2000-01-20 | 2003-08-05 | Amberwave Systems Corporation | Heterointegration of materials using deposition and bonding |
| WO2001054175A1 (en) * | 2000-01-20 | 2001-07-26 | Amberwave Systems Corporation | Low threading dislocation density relaxed mismatched epilayers without high temperature growth |
| JP2004507084A (ja) * | 2000-08-16 | 2004-03-04 | マサチューセッツ インスティテュート オブ テクノロジー | グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス |
| US20020100942A1 (en) * | 2000-12-04 | 2002-08-01 | Fitzgerald Eugene A. | CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
| US6649480B2 (en) * | 2000-12-04 | 2003-11-18 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
| US6495402B1 (en) | 2001-02-06 | 2002-12-17 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions and method of manufacture |
| US6410371B1 (en) | 2001-02-26 | 2002-06-25 | Advanced Micro Devices, Inc. | Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer |
| US6703688B1 (en) * | 2001-03-02 | 2004-03-09 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
| US6723661B2 (en) * | 2001-03-02 | 2004-04-20 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
| US6724008B2 (en) | 2001-03-02 | 2004-04-20 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
| US6830976B2 (en) * | 2001-03-02 | 2004-12-14 | Amberwave Systems Corproation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
| WO2002082514A1 (en) * | 2001-04-04 | 2002-10-17 | Massachusetts Institute Of Technology | A method for semiconductor device fabrication |
| US6905542B2 (en) * | 2001-05-24 | 2005-06-14 | Arkadii V. Samoilov | Waveguides such as SiGeC waveguides and method of fabricating the same |
| US6770134B2 (en) * | 2001-05-24 | 2004-08-03 | Applied Materials, Inc. | Method for fabricating waveguides |
| US6462388B1 (en) * | 2001-07-26 | 2002-10-08 | Hewlett-Packard Company | Isolation of memory cells in cross point arrays |
| US6690040B2 (en) | 2001-09-10 | 2004-02-10 | Agere Systems Inc. | Vertical replacement-gate junction field-effect transistor |
| WO2003025984A2 (en) | 2001-09-21 | 2003-03-27 | Amberwave Systems Corporation | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
| AU2002341803A1 (en) | 2001-09-24 | 2003-04-07 | Amberwave Systems Corporation | Rf circuits including transistors having strained material layers |
| US7060632B2 (en) | 2002-03-14 | 2006-06-13 | Amberwave Systems Corporation | Methods for fabricating strained layers on semiconductor substrates |
| KR100460201B1 (ko) * | 2002-04-08 | 2004-12-08 | 한국전자통신연구원 | ＳｉＧｅ/Ｓｉ 이종 접합 전계 효과 트랜지스터 제조용 기판의 형성 방법 |
| US7615829B2 (en) * | 2002-06-07 | 2009-11-10 | Amberwave Systems Corporation | Elevated source and drain elements for strained-channel heterojuntion field-effect transistors |
| US7335545B2 (en) * | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
| US20030227057A1 (en) * | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
| US7307273B2 (en) * | 2002-06-07 | 2007-12-11 | Amberwave Systems Corporation | Control of strain in device layers by selective relaxation |
| US6995430B2 (en) * | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
| US7074623B2 (en) * | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
| US6946371B2 (en) * | 2002-06-10 | 2005-09-20 | Amberwave Systems Corporation | Methods of fabricating semiconductor structures having epitaxially grown source and drain elements |
| US6900521B2 (en) * | 2002-06-10 | 2005-05-31 | Micron Technology, Inc. | Vertical transistors and output prediction logic circuits containing same |
| US6982474B2 (en) | 2002-06-25 | 2006-01-03 | Amberwave Systems Corporation | Reacted conductive gate electrodes |
| EP1530800B1 (en) * | 2002-08-23 | 2016-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor heterostructures having reduced dislocation pile-ups and related methods |
| US7594967B2 (en) * | 2002-08-30 | 2009-09-29 | Amberwave Systems Corporation | Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy |
| EP2337062A3 (en) * | 2003-01-27 | 2016-05-04 | Taiwan Semiconductor Manufacturing Company, Limited | Method for making semiconductor structures with structural homogeneity |
| US6921913B2 (en) * | 2003-03-04 | 2005-07-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained-channel transistor structure with lattice-mismatched zone |
| CN100437970C (zh) * | 2003-03-07 | 2008-11-26 | 琥珀波系统公司 | 一种结构及用于形成半导体结构的方法 |
| US6900502B2 (en) * | 2003-04-03 | 2005-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel on insulator device |
| US6882025B2 (en) * | 2003-04-25 | 2005-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained-channel transistor and methods of manufacture |
| US6867433B2 (en) * | 2003-04-30 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
| US6974733B2 (en) * | 2003-06-16 | 2005-12-13 | Intel Corporation | Double-gate transistor with enhanced carrier mobility |
| US20050012087A1 (en) * | 2003-07-15 | 2005-01-20 | Yi-Ming Sheu | Self-aligned MOSFET having an oxide region below the channel |
| US6940705B2 (en) * | 2003-07-25 | 2005-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor with enhanced performance and method of manufacture |
| US6936881B2 (en) * | 2003-07-25 | 2005-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor that includes high permittivity capacitor dielectric |
| US7078742B2 (en) * | 2003-07-25 | 2006-07-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained-channel semiconductor structure and method of fabricating the same |
| US7301206B2 (en) * | 2003-08-01 | 2007-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors |
| US7101742B2 (en) * | 2003-08-12 | 2006-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel complementary field-effect transistors and methods of manufacture |
| US7112495B2 (en) * | 2003-08-15 | 2006-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
| US20050035369A1 (en) * | 2003-08-15 | 2005-02-17 | Chun-Chieh Lin | Structure and method of forming integrated circuits utilizing strained channel transistors |
| US6974755B2 (en) * | 2003-08-15 | 2005-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation structure with nitrogen-containing liner and methods of manufacture |
| US7071052B2 (en) | 2003-08-18 | 2006-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Resistor with reduced leakage |
| US6902965B2 (en) * | 2003-10-31 | 2005-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained silicon structure |
| US7888201B2 (en) * | 2003-11-04 | 2011-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors |
| US20050186722A1 (en) * | 2004-02-25 | 2005-08-25 | Kuan-Lun Cheng | Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions |
| US7211845B1 (en) * | 2004-04-19 | 2007-05-01 | Qspeed Semiconductor, Inc. | Multiple doped channel in a multiple doped gate junction field effect transistor |
| US20050266632A1 (en) * | 2004-05-26 | 2005-12-01 | Yun-Hsiu Chen | Integrated circuit with strained and non-strained transistors, and method of forming thereof |
| US20060113603A1 (en) * | 2004-12-01 | 2006-06-01 | Amberwave Systems Corporation | Hybrid semiconductor-on-insulator structures and related methods |
| US7393733B2 (en) * | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
| US8900980B2 (en) * | 2006-01-20 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect-free SiGe source/drain formation by epitaxy-free process |
| US7772060B2 (en) * | 2006-06-21 | 2010-08-10 | Texas Instruments Deutschland Gmbh | Integrated SiGe NMOS and PMOS transistors |
| KR101217555B1 (ko) * | 2006-06-28 | 2013-01-02 | 삼성전자주식회사 | 접합 전계 효과 박막 트랜지스터 |
| US8558278B2 (en) * | 2007-01-16 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained transistor with optimized drive current and method of forming |
| FR2914783A1 (fr) | 2007-04-03 | 2008-10-10 | St Microelectronics Sa | Procede de fabrication d'un dispositif a gradient de concentration et dispositif correspondant. |
| US7531854B2 (en) | 2007-05-04 | 2009-05-12 | Dsm Solutions, Inc. | Semiconductor device having strain-inducing substrate and fabrication methods thereof |
| US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
| US7795605B2 (en) * | 2007-06-29 | 2010-09-14 | International Business Machines Corporation | Phase change material based temperature sensor |
| US7943961B2 (en) * | 2008-03-13 | 2011-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain bars in stressed layers of MOS devices |
| US7808051B2 (en) * | 2008-09-29 | 2010-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Standard cell without OD space effect in Y-direction |
| US9755630B2 (en) | 2009-04-30 | 2017-09-05 | The United States of America as represented by the Secretary of the Government | Solid-state circuit breakers and related circuits |
| US8742628B2 (en) * | 2009-04-30 | 2014-06-03 | The United States Of America As Represented By The Secretary Of The Army | Solid state circuit breaker |
| US8729739B2 (en) | 2010-04-28 | 2014-05-20 | The United States Of America As Represented By The Secretary Of The Navy | Bi-directional circuit breaker |
| TWI416727B (zh) * | 2009-12-04 | 2013-11-21 | Inotera Memories Inc | Ｐ型金屬氧化層半導體場效電晶體及其製造方法 |
| US8754455B2 (en) | 2011-01-03 | 2014-06-17 | International Business Machines Corporation | Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure |
| CN103187308B (zh) * | 2011-12-29 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | 结型场效应管及其形成方法 |
| US10170618B2 (en) | 2017-03-02 | 2019-01-01 | International Business Machines Corporation | Vertical transistor with reduced gate-induced-drain-leakage current |
| US10431695B2 (en) | 2017-12-20 | 2019-10-01 | Micron Technology, Inc. | Transistors comprising at lease one of GaP, GaN, and GaAs |
| US10825816B2 (en) | 2017-12-28 | 2020-11-03 | Micron Technology, Inc. | Recessed access devices and DRAM constructions |
| US10734527B2 (en) | 2018-02-06 | 2020-08-04 | Micron Technology, Inc. | Transistors comprising a pair of source/drain regions having a channel there-between |
| US11271108B2 (en) | 2020-04-08 | 2022-03-08 | International Business Machines Corporation | Low-noise gate-all-around junction field effect transistor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60261176A (ja) * | 1984-06-08 | 1985-12-24 | Hitachi Ltd | 電界効果トランジスタ |
| JPH05267678A (ja) * | 1992-03-17 | 1993-10-15 | Rohm Co Ltd | 半導体装置およびその製造方法 |
| JP3229012B2 (ja) * | 1992-05-21 | 2001-11-12 | 株式会社東芝 | 半導体装置の製造方法 |
| FR2693314B1 (fr) * | 1992-07-02 | 1994-10-07 | Alain Chantre | Transistor JFET vertical à mode de fonctionnement bipolaire optimisé et procédé de fabrication correspondant. |
-
1997
- 1997-02-19 US US08/803,033 patent/US5714777A/en not_active Expired - Fee Related
- 1997-09-24 TW TW086113894A patent/TW343365B/zh not_active IP Right Cessation
- 1997-10-23 KR KR1019970054456A patent/KR100260687B1/ko not_active IP Right Cessation
-
1998
- 1998-01-16 ES ES98300319T patent/ES2289768T3/es not_active Expired - Lifetime
- 1998-01-16 MY MYPI98000184A patent/MY120718A/en unknown
- 1998-01-16 EP EP98300319A patent/EP0860884B1/en not_active Expired - Lifetime
- 1998-01-16 CN CNB981042503A patent/CN1263161C/zh not_active Expired - Fee Related
- 1998-01-16 DE DE69838307T patent/DE69838307T2/de not_active Expired - Lifetime
- 1998-01-30 JP JP10018365A patent/JP2951629B2/ja not_active Expired - Lifetime
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100379029C (zh) * | 2002-03-15 | 2008-04-02 | 住友电气工业株式会社 | 横型接合型场效应晶体管及其制造方法 |
| CN100349270C (zh) * | 2002-07-24 | 2007-11-14 | 住友电气工业株式会社 | 纵向结型场效应晶体管及其制造方法 |
| CN102709323A (zh) * | 2004-10-07 | 2012-10-03 | 费查尔德半导体有限公司 | 设计带隙的mos栅功率晶体管 |
| CN101317271B (zh) * | 2004-12-01 | 2011-08-03 | 半南实验室公司 | 宽能带隙半导体横向沟槽场效应晶体管及制造方法 |
| CN101371359B (zh) * | 2005-10-28 | 2011-11-09 | 苏伏特股份有限公司 | 在硅和硅合金中使用互补结型场效应晶体管和mos晶体管的集成电路 |
| CN101467262B (zh) * | 2006-04-04 | 2012-01-04 | 半南实验室公司 | 结势垒肖特基整流器及其制造方法 |
| CN101595565B (zh) * | 2006-09-18 | 2013-03-27 | 昆南诺股份有限公司 | 在垂直半导体结构上制造精密垂直和水平层的方法 |
| CN103578996A (zh) * | 2012-07-27 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | 晶体管制造方法 |
| CN104124170A (zh) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | 晶体管及其形成方法 |
| CN108258032A (zh) * | 2018-01-19 | 2018-07-06 | 重庆邮电大学 | 一种采用组合发射区的异质结双极晶体管及其制造方法 |
| CN108766967A (zh) * | 2018-05-23 | 2018-11-06 | 燕山大学 | 一种平面复合应变Si/SiGe CMOS器件及制备方法 |
| CN108766967B (zh) * | 2018-05-23 | 2021-05-28 | 燕山大学 | 一种平面复合应变Si/SiGe CMOS器件及制备方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10242478A (ja) | 1998-09-11 |
| CN1263161C (zh) | 2006-07-05 |
| EP0860884A2 (en) | 1998-08-26 |
| KR100260687B1 (ko) | 2000-07-01 |
| TW343365B (en) | 1998-10-21 |
| EP0860884A3 (en) | 1999-03-31 |
| DE69838307T2 (de) | 2008-05-21 |
| JP2951629B2 (ja) | 1999-09-20 |
| US5714777A (en) | 1998-02-03 |
| ES2289768T3 (es) | 2008-02-01 |
| MY120718A (en) | 2005-11-30 |
| EP0860884B1 (en) | 2007-08-29 |
| KR19980070031A (ko) | 1998-10-26 |
| DE69838307D1 (de) | 2007-10-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1263161C (zh) | 硅/锗硅垂直结型场效应晶体管及其制造方法 | |
| US5792679A (en) | Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant | |
| KR100392166B1 (ko) | 반도체 장치의 제조 방법 및 반도체 장치 | |
| JP4521542B2 (ja) | 半導体装置および半導体基板 | |
| US5637889A (en) | Composite power transistor structures using semiconductor materials with different bandgaps | |
| US5998807A (en) | Integrated CMOS circuit arrangement and method for the manufacture thereof | |
| EP2383785A2 (en) | A nanoscale electronic device | |
| EP0657942A2 (en) | Lateral bipolar transistor | |
| US7301180B2 (en) | Structure and method for a high-speed semiconductor device having a Ge channel layer | |
| CN111029400A (zh) | 具有宽能隙三五族汲极的金属氧化物硅半导体场效晶体管及其制造方法 | |
| US7820523B2 (en) | Fabrication of active areas of different natures directly onto an insulator: application to the single or double gate MOS transistor | |
| Cai et al. | Fully-depleted-collector polysilicon-emitter SiGe-base vertical bipolar transistor on SOI | |
| CN111739800B (zh) | 一种SOI基凹栅增强型GaN功率开关器件的制备方法 | |
| US5311045A (en) | Field effect devices with ultra-short gates | |
| JP3389009B2 (ja) | 半導体装置およびその製造方法 | |
| EP0278072A2 (en) | Permeable-base transistor | |
| CN100336172C (zh) | 改进注氧隔离技术制备的绝缘体上的硅锗材料结构及工艺 | |
| JP3598271B2 (ja) | 半導体装置 | |
| CN1655321A (zh) | 基于硅锗/硅结构注氧隔离制备绝缘体上硅锗材料的方法 | |
| JP3600174B2 (ja) | 半導体装置の製造方法及び半導体装置 | |
| Wittmann et al. | Silicon nanoelectronic devices with delta-doped layers | |
| CN1663052A (zh) | 具有重组区域的绝缘体上硅场效应晶体管及形成该场效应晶体管的方法 | |
| EP0243609A1 (en) | Complementary semiconductor device structure and its production | |
| Ballrooms et al. | High-Frequency Electronics: Devices and Applications | |
| Dudek et al. | Silicon MOSFETs on insulator with lithography-independent 100 nm channel length |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060705 Termination date: 20110116 |