CN1215920A - 带有导热支持元件的电子封装件 - Google Patents

带有导热支持元件的电子封装件 Download PDF

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Publication number
CN1215920A
CN1215920A CN98116911A CN98116911A CN1215920A CN 1215920 A CN1215920 A CN 1215920A CN 98116911 A CN98116911 A CN 98116911A CN 98116911 A CN98116911 A CN 98116911A CN 1215920 A CN1215920 A CN 1215920A
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Prior art keywords
substrate
semiconductor device
circuit
heat conduction
packaging part
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CN98116911A
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CN1095201C (zh
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F·E·安德罗斯
J·R·布普
R·B·汉默
M·迪皮特罗
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International Business Machines Corp
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International Business Machines Corp
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    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Abstract

一种电子封装件,它包括一个坚实的支持元件(例如铜片),其上固定有封装的半导体芯片以及电路化衬底元件。用导热粘合剂来固定芯片,而电路化衬底(最好是一种柔性电路)用电绝缘粘合剂来固定。最好用引线、热压或热声焊接来使芯片电连接到衬底电路的设定部分。可使用包封剂来覆盖并保护芯片和衬底间的连接。此种封装件本身可以电连接到诸如印刷电路板那样的分立的第二衬底上。

Description

带有导热支持元件的电子封装件
本发明步及到电子封装,确切地说是采用电路化衬底和半导体器件(芯片)作为其部件的一种封装。更确切地说,本发明涉及到用于信息处理系统(计算机)领域的电子封装。
在计算机工业界已知采用半导体芯片作为其部件的电子封装,其例子在美国专利证书4,004,195(Harayda等人)、4,415,025(Horvath)、4,593,342(Lindsay)、4,914,551(Anschel等人)、4,962,416(Jenes等人)以及5,278,724(Angulas等人)中已描述过。特别是专利4,593,342和5,914,551中,半导体芯片电耦合到柔性的薄的电路化衬底上,此衬底本身又电耦合到一个诸如印刷电路板(PCB)之类的第二衬底上。半导体芯片本身被热连接于一个分立的热沉元件以使运行过程中芯片产生的热得以发散。此六个专利综合于此作为参考。
当然,现代电子封装工业的主要目的是大大提高组成这些封装件的各种元件(如半导体芯片和电路化衬底)的电路密度。密度的增加就迫使运行过程中半导体芯片所产生的更多的热量要有效地交换,这种热交换对于保持芯片温度在一定的范围以得到高的芯片可靠性并从而提高整个封装件的使用寿命来说是至关重要的。这一高密度还迫使要有效地提供芯片同相关电路(如作为其部件的电路化衬底的电路)的电耦合方法。
如此处所述,本发明的电子封装代表了一种特别适用于带有高电路密度的半导体器件和相关的电路化衬底作为其部件的密集结构。而且,此处所述的封装可提供能够相当容易而便宜地安装的独特结构性能(高的功率耗散能力和优越的电学性能)。而且,此结构适合于采用各种不同的半导体芯片结构和相关的电路化衬底结构,从而提供一种更为理想得多的封装通用性。再者,此处所述的本发明可容易地适应于各种芯片安装工艺(例如引线、热压或热声焊、焊接等)。
可以认为,具有上述和此处所述的其它特性的电子封装,代表了电子封装领域的一个明显的进展。还可认为,制作这种封装件的新的独特的方法将是对本领域的一种贡献。
因此,本发明的主要目的是提供一种具有此处所述的一些优点的电子封装件,以提高电子封装技术。
本发明的另一目的是提供一种制造这种电子封装件的方法。,根据本发明的一种情况,确定了一种电子封装件,它包含一个质地坚实的导热的支持元件、一个电绝缘地焊接于支持元件上的薄的电路化的衬底、以及一个也焊接于支持元件上的半导体器件。薄的电路化的衬底包括一个至少有一层电路的介电元件,而半导体器件在相对于薄的电路化衬底的电路的位置处导热地焊接于支持元件上。半导体器件电连接到电路化衬底的电路上。
根据本发明的另一情况,确定了一种制造电子封装件的方法,此方法包含下列步骤:提供一个质地坚实的导热的支持元件,将一个薄的电路化衬底直接焊接到此支持元件上,将一个半导体器件导热地焊接到导热的支持元件上,以及将半导体器件电连接到组成薄的电路化衬底的部件的电路上。薄的电路化衬底电绝缘地焊接到导热的支持元件上。
图1示出了用于本发明的薄的电路化衬底的一个实施例;
图2表示图1衬底的高倍放大局部剖面,其上附着有一个焊接元件;
图3-6表示根据本发明的一个实施倒来生产电子封装件的各个步骤,图6中包括用前述焊接元件来使电路化衬底连接到第二电路化衬底的步骤;
图7-9表示根据本发明的另一实施例来生产电子封装件的另一组步骤;以及
图10表示根据本发明的再一个实施例的一个带有导热支持元件的电子封装件。
结合上述附图,参照下列公开的例子和所附的权利要求,以便更好地了解本发明及其其它的目的、优点和功能。
图1示出了根据本发明的一个实施例适用于电子封装件13(图4)的一例薄的电路化衬底11。薄衬底11最好包含一个成相当薄(例如约0.001-0.005英寸厚)的介电材料层状的介电元件15,最好是聚酰亚胺。市场有售的此种材料的已知例子包括Kapton(杜邦公司的一种商标)和Upilex(Ube产业的一种商标)。衬底11最好包括至少一层可根据本产业熟知的光刻方法来形成的电路17。通常此种电路包括铜或相似的连接金属作为其部件。在图1所述实施例中,衬底11还包括一个位于介电元件15的第一层17反面上的第二导电层19。此第二电路层的材料同层17相似,且用熟知的工艺来制作。采用金属化孔(PTH)21或其它适当的方法可实现17和19二层间的互连。用已知的工艺可制作这种镀通孔,无需赘述。
在图1所示的电路化衬底的实施例中,当然其中的一层(如17)电学上可用作信号层,而反面的一层(如19)主要用作接地层。
各层的厚度可在约0.0005-约0.002英寸范围内,这样形成的衬底11其总厚度为约0.002-0.009英寸。因而认为此结构是很薄的。
图2所示(只示出了一部分)的衬底11还包括一个如所示位于各PTH电接触中的焊接元件23。在本发明中有可能为用于衬底11的各个PTH提供焊接元件23。图2只示出了一个焊接元件,但这不是本发明的限制。在本发明的一个例子中,衬底11总共包括736个PTH21和相同数目的焊接元件23。
各焊接元件最好用回流焊方法焊接到各个PTH,其中预制的焊球图形与各PTH对准,且以此法使PTH物理接触,之后加热以引起焊球至少部分地熔化并使焊料经由各内部窗口22(图2)发生毛细运动之类。最佳焊料为Sn∶Pb=10∶90的焊料。作为变通,采用多种焊料元件(如Sn∶Pb=37∶63)并使其上的各PTH 21位于上述焊料元件极近处来形成这种焊料连接,也属于本发明的范围。然后加热,使焊料元件“起球”并填入各PTH。适合于上述焊接操作的温度最好在约170℃-约225℃范围。注意美国专利证书5,133,495(Angulas等人),其中说明了采用的焊料即使在二个电路化衬底(例如一个PCB和一个柔性电路)之间也“起球”并形成连接。此专利也综述于此作为参考。
在上述焊接元件用于衬底11之前,一个保护材料镀层25可用来覆盖电路层17的选定部分。此材料的一个例子是名为Scotchcast(明尼苏达矿业公司出售的产品)的市售改型聚合树脂。Scothchcast通常包括(重量比)约47%的环氧聚合物、约52%的硬化剂和增塑剂混合物以及约0.4%的着色剂。硬化剂和增塑剂混合物含有约25-39%的六氢邻苯二甲酸酐、约50-75%重量比的聚丙二醇和/或聚氧亚丙基二醇增塑剂、约0.85-1.0%重量比的叔胺和少量的六氢化邻苯二甲酸。这种材料在本技术领域中是熟知的,无需赘述。此保护层的目的是在诸如将如图4和5所示的成品封装件连接到诸如PCB 27(图6)之类的外部第二衬底的后工序中,用来保护电路17。这种镀层可防止可能的离子沾污形成在电路上,这种沾污在电路的最终使用中可能有不利影响(为引起电路短路)。前述的加热步骤最好采用热空气或将元件放在适当的炉子中。若使用炉子,当加以前述温度时,在约1.5-5分钟的时间内,衬底11的焊料就附着到PCB上。关于焊料的采用,如果需要,用于本发明的最佳焊料可从Alpha金属公司购到。
在图3中,按位带有焊接元件23的电路化衬底11被直接焊到导热支持元件31上。如所示,元件31的结构为细长的大体平面状,而且其中最好包括一个凹槽33。元件31最好是一个导热良好材料例如铜构成的金属片。在最佳实施例中,元件31是由起始厚度约为0.020英寸的铜片制作的。这种厚度的元件31是质地坚实的,可用作最终封装件的加强元件,从而当衬底11焊接于其上时,可确保薄的电路化衬底大体成平面状,此衬底在无支持的情况下将是柔性的并易于弯曲。这代表了本发明的一个重要特征,以致如图5(和图8)所示,在结构中可有效地保持衬底11的平面状,特别是由于此结构在后工序中还要经受诸如焊接到外衬底(图6和9)之类的额外工序。
用电绝缘粘合剂将衬底11固定到元件31。根据本发明的最佳实施例,一种成功地用于本发明的粘合剂包含一薄层聚酰亚胺,其一面或二面上涂覆有一薄层硅树脂粘合剂。
图4示出了一个半导体芯片41,也是直接地安装在支持元件31的最佳位置的凹槽33处。芯片41可选自本技术的各种已知芯片,因而可有不同的尺寸,都可以容易地用作本发明的部件。芯片41最好采用诸如前述明尼苏达矿产公司的改型Scotchcast产品的优良导热粘合剂采粘合到元件31上。若打算将芯片41电连接到支持元件31,例如作为一个接地电位,则选用的粘合剂也可以是导电粘合剂。如图4所示,芯片41还包括多个位于其外表面45上的电接触位置43。在半导体芯片上采用这种位置43是众所周知的,无需赘述。如图4所示,这些位置43大体上是平面状,而且在图4所示的方位中,最好同衬底11上电路的相应位置(相邻)层17大体共平面。或者,芯片也可位于比衬底11更深处,以使位置43的平面比此处所示的更凹进去。这是本发明的一个显特征,它使各位置43和形成层17的相应部件(如导线或焊点)之间的下一步电连接变得更容易。
在图4中,提供此种连接的最佳方法是采用焊线操作,其例子在本技术中是众所周知的,无需赘述。采用热声、热压、激光和激光声、或其它种类的焊接来提供各导线(49)和相应的被连导电元件之间的连接,也属于本发明的范围。这种导线49通常可以是铝或金材料。
前述电连接之后,最好加入一定数量的包封剂51(图5),以大致覆盖芯片41的外表面45和有关的导线49以及部分相邻电路层17。此种包封剂的一个例子是Hysol FP4511,这是一种流动性的液态环氧凝胶,其特点是粘滞性低和应力低。(Hysol是纽约州Olean的Dexter公司的商标)。当衬底和支持元件相对于图4和5所示方位被倒转时,最好实行这种有如前述引线焊接操作中的包封。这样,包封剂51就硬化(凝固)了大体如图5所示的结构。
图5所述的电子封装结构至此即可与相关的电路结构(如图6所示的PCB 27)进行电连接,从而进一步扩展本发明的应用范围。在图5的实施例中,所示的方位在元件运行过程中,当然就使芯片41的热量更容易经由导热粘合剂(53)流向导热支持元件31。图5所示的包封剂51可延伸到完全覆盖芯片41的整个外表面,如有必要,可包括芯片的各个侧面55。这一大范围包封为芯片41提供了进一步的保护。
图6示出了电连接于PCB 27之上的衬底11和支持元件31。在最佳实施例中,PCB 27包括许多根据与衬底11上焊球23的相应图形相当的一定图形而彼此分隔地位于其上表面62的导体61(如铜焊点)。其上带有焊接元件23的衬底降低到PCB 27位置与之物理啮合,因而使元件23同各导体61物理接触。然后加热(例如210℃)使至少部分地熔化焊接元件23从而与各导体61连接起来。采用美国专利证书5,203,075(Angulas等人)所述的工艺(其中,在各导体上采用一适当的焊料,且这些焊料通过各焊球元件23物理啮合并形成结)也属于本发明的范围。5,203,075的方法因而也综合于此作为参考。
所示导体61本身可电连接于PCB27的介电材料中的内部导电平面(未示出),在PCB产业中已知这些平面是用作信号、接地或供电平面的、无需赘述。图5所示的电子封装结构至此当然已在许多单独的位置上电连接到了PCB27。用这种办法,PCB27本身可用本技术领域熟知的方法安装并电连接到电子计算机中(例如在处理器机盒中)。
图7-9示出了根据本发明另一实施例制作电子封装件的另一方法。在图7中,芯片41用相似于图4中固定芯片41的方法,先固定在支持元件31的凹槽33位置上。如所示,采用相似的导热粘合剂53使芯片41确保定位,然后如图8所示,将衬底(11′)对准并固定在元件31。这一固定是采用相似于图4实施例的粘合剂来完成的。衬底11′稍许不同于图1的衬底11,其电路层17最好包括多个凸出的导线71作为其部件,这些导线延伸越过形成在衬底上的内部窗口73。当然,在图4的最佳实施例中,衬底11也包括相似的窗口73。这种凸出的引线71相对于介电体15呈悬臂状,并设计为在衬底11′最终固定到支持元件31时,用来与芯片41上各个接触位置43进行对准。这种对准可用照相机或本技术领域熟知的其它精确方法来进行。采用热压焊或根据本技术领域熟知的前述其它方法,可实现引线71和位置43的最终连接,无需赘述。
在上述悬臂导电元件71和各接触位置43连接之前,以及在上述图4实施例中引线焊接之前,在电路17的各导体上以及在各接触位置43上,最好加一薄层贵金属(如金),以增强其间的连接。
图9示出了电连接于PCB 27的图8封装件,此连接最好根据图5实施例所用的工艺来完成。
图10示出了根据本发明的再一实施例的电子封装件13′。像图4中封装件13一样,封装件13′包括一个电路化衬底11,它在本发明的一个实施例中可能与图4实施例中使用的完全相同。或者,此衬底也可相似于图8中的衬底11′。在图10中,封装件13′包括一个结构不同于上述各实施例的热导支持元件31。具体地说,支持元件31′包括一个最好由一单片厚度大体相似于上述实施例中支持元件31的金属组成的平面状基底81,还包括至少一个分隔层83,如图所示,83最好周上述固定芯片41到支持元件31所采用的导热粘合剂来固定到基底81上。在最佳实施例中,至少使用了二个分隔层83,各用于其上衬底11的相应部分。衬底11最好用相似于上述用来固定衬底11到元件31的导电粘合剂(54)来固定到分隔层83上。在一个实施例中,各分隔层还包含铜或铝导热材料,且厚度仅为约0.025英寸。这样,支持元件31′的分隔层和基底元件的总厚度仅为约0.029英寸。在图10的实施例中,分隔层用来有效地将衬底11上电路的外层17与外表面分隔开来,并在芯片定位于衬底11和相邻分隔层元件83所界定的窗口73时,用来确定芯片41(示于虚框中)的接触位置43的位置。可以理解,这样就可以将芯片41定位在窗口73中并固定到相对于窗口73的那部分基底81上。芯片41采用相似于图4和8中固定芯片41的导热粘合剂来固定。采用上述(图4)引线焊接操作可实现向各电路层17的连接,衬底11也可包括如图8实施例所采用的悬臂导线元件。
这就描述完了一种电子封装件及其制造方法,其中封装件的半导体芯片和薄的电路化衬底元件都固定在一个共用的导热支持元件上,此导热支持元件如所述而同时用作热沉和加固元件以便为其上的薄的电路化衬底提供质地坚实的支持。此封装件如所述,使半导体芯片相对于此电路上至少一层的定位变得容易,同时还确保了最终封装中芯片和电路化衬底二者的固定。而且,这种封装件易于适应向诸如PCB之类的分立导电衬底进行后续安装和耦合。
虽然已描述了本发明的各最佳实施例,但是很显然,对本领域一般技术人员来说,在不超越所附权利要求确定的本发明的范围的前提下,可做出各种修正和改变。

Claims (25)

1.一种电子封装件包括:
一个质地坚实的导热支持元件;
一个薄的柔性的电路化衬底,包括有置于其第一表面上的第一电路层,所述薄的柔性的电路化衬底包括位于所述介电元件内并和所述第一电路层电连接的多个导体通过口,所述薄的电路化衬底以电绝缘的方式直接固定到所述支持元件上,包括沿着其上有所述多个导体通过孔所述介电元件的部分;
以导热方式,在所述电路化衬底的所述第一电路层的相对位置被固定到所述支持元件的半导体器件,所述半导体器件包括其上有多个电接触位置的表面,用于电连接到所述电路化衬底的所述电路的所述第一层上;和
多个焊接部件,每个位于所述导体通过孔的所选择的一些上,并与之电连接,每个所述焊接部件包括在选择的一些所述导体通过孔的相应一个中扩展的第一步部分,和一个圆形的第二部分,从所述导体通过孔凸出,并适于和一个外部电路化衬底电连接。
2.权利要求1的电封装件,其特征在于,所述焊接部件由10∶90的锡:铅组成。
3.权利要求1的电封装件,其特征在于,进一步包括位于基本和所述导体通过孔及所述多个焊接部件相邻的所述薄的柔性电路化衬底上的保护层。
4.权利要求1的电封装件,其特征在于,所述导热支持元件包括一个金属片部件。
5.权利要求1的电封装件,其特征在于,所述金属片元件由铜组成。
6.权利要求1的电封装件,其特征在于,所述导热支持元件上包括至少一个凹槽,所述半导体部件固定在所述支持元件的所述凹槽位置。
7.权利要求1的电封装件,其特征在于,所述半导体部件的所述电接触位置的选定的一些,通过多条导线被电连接到所述电路化衬底的所述第一电路层。
8.权利要求1的电封装件,其特征在于,所述薄的柔性电路化衬底的所述第一电路层包括多个凸出的引线部件,所述凸出的引线部件中选定的一些被电连接到所述半导体部件的所述电接触位置的相应一个上。
9.权利要求1的电封装件,其特征在于,所述导热支持部件既作为所述电封装件操作期间所述半导体器件产生的热量的热沉部件,又作为加固元件,使所述薄的电路化衬底基本保持在平面取向。
10.权利要求1的电封装件,其特征在于,进一步包括在所述薄的柔性电路化衬底上的第二电路层,所述薄的柔性电路化衬底的所述电路的第二层和所述导热支持部件相对,并且通过所述导体通过孔中的一个或多个和所述第一电路层电连接。
11.权利要求1的电封装件,其特征在于,所述薄的柔性电路化衬底通过电绝缘黏合剂被固定到所述导热支持部件上。
12.权利要求1的电封装件,其特征在于,所述半导体器件通过导热黏合剂被固定到所述支持部件上,从而所述半导体器件发出的热量将容易地传到所述导热支持部件。
13.权利要求1的电封装件,其特征在于,进一步包括一定数量的包封材料,它大体上覆盖至少一部分上述半导体器件,和至少一部分上述薄的柔性电路化衬低的所述电路。
14.权利要求1的电封装件,其特征在于,进一步包括第二电路化衬底,所述多个焊接元件的所述圆形第二部分和所述第二电路化衬底电连接。
15.权利要求1的电封装件,其特征在于,所述导热支持部件包括一个基底和至少一个分隔元件,所述分隔元件将所述薄的柔性电路化衬低和所述基部分隔开预定距离。
16.权利要求1的电封装件,其特征在于,每个所述焊接部件的所述第一部分从所述焊接部件的所述凸出的圆形第二部分,凸出到所述通过孔的相对侧的所述相应导体通过孔之外。
17.一种制造电子封装件的方法,所述方法包括:
提供一个质地坚实的导热支持元件;
以电绝缘方式将至少一个薄的电路化衬底直接固定到所述导热支持部件上,所述薄的电路化衬底包括有至少一个电路层的介电部件;
以导热方式将半导体器件固定到所述导热支持部件的一个相对于所述电路层的位置;
电连接所述半导体器件到所述薄的电路化衬底的所述电路上;和
基本上用封装材料覆盖所述半导体器件的至少一部分和所述电路的至少一部分。
18.权利要求17的方法,其特征在于,用黏合剂将所述薄的电路化衬底固定到所述导热部件。
19.权利要求17的方法,其特征在于,用黏合剂将所述半导体器件固定到所述导热支持部件上。
20.权利要求17的方法,其特征在于,用线固定操作实现所述半导体设备到所述薄的电路化衬底的所述电路的所述电连接。
21.权利要求17的方法,其特征在于,所述半导体器件到所述薄的电路化衬底的所述电路的所述电连接是通过热压缩固定操作实现的。
22.权利要求17的方法,其特征在于,在将所述薄的电路化衬底固定到所述导热支持部件之后,进行所述半导体器件到所述导热支持部件的所述固定。
23.权利要求17的方法,其特征在于,在所述导热支持部件上提供凹槽,之后将所述半导体器件固定到所述支持部件上,所述半导体器件在所述凹槽位置被固定到所述支持部件上。
24.权利要求17的方法,其特征在于,进一步包括将多个焊接部件固定在所述薄的电路化衬底的所述电路层的选定位置上的步骤。
25.权利要求24的方法,其特征在于,进一步包括提供一个第二电路化衬底,和电连接所述薄的电路化衬底到所述第二电路化衬底,用所述焊接部件实现所述电连接。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100403532C (zh) * 2005-08-19 2008-07-16 南茂科技股份有限公司 散热型球格阵列封装结构
CN100429769C (zh) * 2005-04-26 2008-10-29 株式会社东芝 用于带有排气孔的半导体封装体的方法和系统
US7495256B2 (en) 2002-10-18 2009-02-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor apparatus and fabrication method of the same
CN102651352A (zh) * 2011-02-25 2012-08-29 富士通株式会社 半导体装置、用于制造半导体装置的方法以及电子器件
CN106816419A (zh) * 2015-12-02 2017-06-09 联咏科技股份有限公司 薄膜上芯片封装
US10770368B2 (en) 2015-12-02 2020-09-08 Novatek Microelectronics Corp. Chip on film package and heat-dissipation structure for a chip package
CN114530549A (zh) * 2022-04-20 2022-05-24 江苏芯德半导体科技有限公司 一种半导体结构及其制备方法

Families Citing this family (106)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3258764B2 (ja) * 1993-06-01 2002-02-18 三菱電機株式会社 樹脂封止型半導体装置の製造方法ならびに外部引出用電極およびその製造方法
JPH07169872A (ja) * 1993-12-13 1995-07-04 Fujitsu Ltd 半導体装置及びその製造方法
US5455390A (en) * 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
JP2531382B2 (ja) * 1994-05-26 1996-09-04 日本電気株式会社 ボ―ルグリッドアレイ半導体装置およびその製造方法
US5717252A (en) * 1994-07-25 1998-02-10 Mitsui High-Tec, Inc. Solder-ball connected semiconductor device with a recessed chip mounting area
CA2156795C (en) * 1994-08-31 1999-08-17 Yuzo Shimada An electronic device assembly and a manufacturing method of the same
JP2595909B2 (ja) * 1994-09-14 1997-04-02 日本電気株式会社 半導体装置
US5945741A (en) * 1995-11-21 1999-08-31 Sony Corporation Semiconductor chip housing having a reinforcing plate
US5798909A (en) * 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips
TW373308B (en) * 1995-02-24 1999-11-01 Agere Systems Inc Thin packaging of multi-chip modules with enhanced thermal/power management
JP2677242B2 (ja) * 1995-04-27 1997-11-17 日本電気株式会社 半導体装置及びその製造方法
KR0159987B1 (ko) * 1995-07-05 1998-12-01 아남산업주식회사 솔더볼을 입출력 단자로 사용하는 볼그리드 어레이(bga) 반도체 패캐지의 열 방출구조
US5706171A (en) * 1995-11-20 1998-01-06 International Business Machines Corporation Flat plate cooling using a thermal paste retainer
US5877551A (en) * 1996-11-18 1999-03-02 Olin Corporation Semiconductor package having a ground or power ring and a metal substrate
US5796589A (en) * 1995-12-20 1998-08-18 Intel Corporation Ball grid array integrated circuit package that has vias located within the solder pads of a package
JPH09186414A (ja) * 1995-12-27 1997-07-15 Ibiden Co Ltd 電子部品搭載用基板
DE19600306C1 (de) * 1996-01-05 1997-04-10 Siemens Ag Halbleiter-Bauelement, insb. mit einer optoelektronischen Schaltung bzw. Anordnung
US5723369A (en) * 1996-03-14 1998-03-03 Lsi Logic Corporation Method of flip chip assembly
US6100596A (en) * 1996-03-19 2000-08-08 Methode Electronics, Inc. Connectorized substrate and method of connectorizing a substrate
US5726858A (en) * 1996-05-23 1998-03-10 Compaq Computer Corporation Shielded electrical component heat sink apparatus
JP3195236B2 (ja) * 1996-05-30 2001-08-06 株式会社日立製作所 接着フィルムを有する配線テープ,半導体装置及び製造方法
US6791194B1 (en) 1996-05-30 2004-09-14 Hitachi, Ltd. Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same
CA2180807C (en) * 1996-07-09 2002-11-05 Lynda Boutin Integrated circuit chip package and encapsulation process
US5904581A (en) * 1996-07-17 1999-05-18 Minnesota Mining And Manufacturing Company Electrical interconnection system and device
US5804984A (en) * 1996-08-02 1998-09-08 International Business Machines Corporation Electronic component test apparatus with rotational probe
US6051982A (en) * 1996-08-02 2000-04-18 International Business Machines Corporation Electronic component test apparatus with rotational probe and conductive spaced apart means
AU4991397A (en) * 1996-11-08 1998-05-29 W.L. Gore & Associates, Inc. Electronic package having reduced radius of curvature
EP1536521B1 (en) * 1996-11-14 2007-08-15 Fci High density connector having a ball type of contact surface
JPH10150069A (ja) * 1996-11-21 1998-06-02 Sony Corp 半導体パッケージ及びその製造方法
US5990545A (en) * 1996-12-02 1999-11-23 3M Innovative Properties Company Chip scale ball grid array for integrated circuit package
US5866949A (en) * 1996-12-02 1999-02-02 Minnesota Mining And Manufacturing Company Chip scale ball grid array for integrated circuit packaging
KR100209760B1 (ko) * 1996-12-19 1999-07-15 구본준 반도체 패키지 및 이의 제조방법
JPH1174651A (ja) 1997-03-13 1999-03-16 Ibiden Co Ltd プリント配線板及びその製造方法
JP3475426B2 (ja) * 1997-03-24 2003-12-08 セイコーエプソン株式会社 半導体装置の製造方法
US6208022B1 (en) * 1997-03-27 2001-03-27 Nec Corporation Electronic-circuit assembly
US5869889A (en) * 1997-04-21 1999-02-09 Lsi Logic Corporation Thin power tape ball grid array package
US6020637A (en) * 1997-05-07 2000-02-01 Signetics Kp Co., Ltd. Ball grid array semiconductor package
JP3639088B2 (ja) 1997-06-06 2005-04-13 株式会社ルネサステクノロジ 半導体装置及び配線テープ
US5940687A (en) * 1997-06-06 1999-08-17 International Business Machines Corporation Wire mesh insert for thermal adhesives
US5877552A (en) * 1997-06-23 1999-03-02 Industrial Technology Research Institute Semiconductor package for improving the capability of spreading heat and electrical function
US6166434A (en) * 1997-09-23 2000-12-26 Lsi Logic Corporation Die clip assembly for semiconductor package
US5909057A (en) * 1997-09-23 1999-06-01 Lsi Logic Corporation Integrated heat spreader/stiffener with apertures for semiconductor package
US6037658A (en) * 1997-10-07 2000-03-14 International Business Machines Corporation Electronic package with heat transfer means
US5966804A (en) * 1997-11-03 1999-10-19 National Center For Manufacturing Sciences Printed wiring board assemblies
FR2771890B1 (fr) * 1997-11-28 2000-02-18 Thomson Csf Procede de montage en surface d'un boitier hyperfrequence sur un circuit imprime et boitier et circuit imprime pour la mise en oeuvre du procede
FR2771889B1 (fr) * 1997-11-28 2000-02-18 Thomson Csf Procede de montage en surface d'un boitier hyperfrequence sur un circuit imprime et boitier et circuit imprime pour la mise en oeuvre du procede
US6125042A (en) * 1998-04-10 2000-09-26 Lucent Technologies, Inc. Ball grid array semiconductor package having improved EMI characteristics
US6404065B1 (en) 1998-07-31 2002-06-11 I-Xys Corporation Electrically isolated power semiconductor package
US6479887B1 (en) 1998-08-31 2002-11-12 Amkor Technology, Inc. Circuit pattern tape for wafer-scale production of chip size semiconductor packages
US6428641B1 (en) 1998-08-31 2002-08-06 Amkor Technology, Inc. Method for laminating circuit pattern tape on semiconductor wafer
KR20010099684A (ko) 1998-10-14 2001-11-09 스프레이그 로버트 월터 상호 연결된 접지면이 있는 테이프 볼 그리드 어레이
JP2000138262A (ja) 1998-10-31 2000-05-16 Anam Semiconductor Inc チップスケ―ル半導体パッケ―ジ及びその製造方法
JP2000138317A (ja) 1998-10-31 2000-05-16 Anam Semiconductor Inc 半導体装置及びその製造方法
TW421981B (en) * 1998-12-18 2001-02-11 Hon Hai Prec Ind Co Ltd Welding method for electric connection between the mother board and the electric components
US6300168B1 (en) * 1999-01-07 2001-10-09 Sony Corp Method of manufacturing a semiconductor device
FR2794266B1 (fr) * 1999-05-25 2002-01-25 Gemplus Card Int Procede de fabrication de dispositif electronique portable a circuit integre comportant un dielectrique bas cout
US6359334B1 (en) 1999-06-08 2002-03-19 Micron Technology, Inc. Thermally conductive adhesive tape for semiconductor devices and method using the same
US6876554B1 (en) * 1999-09-02 2005-04-05 Ibiden Co., Ltd. Printing wiring board and method of producing the same and capacitor to be contained in printed wiring board
JP3973340B2 (ja) * 1999-10-05 2007-09-12 Necエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
US6249045B1 (en) * 1999-10-12 2001-06-19 International Business Machines Corporation Tented plated through-holes and method for fabrication thereof
US6281437B1 (en) 1999-11-10 2001-08-28 International Business Machines Corporation Method of forming an electrical connection between a conductive member having a dual thickness substrate and a conductor and electronic package including said connection
KR100390453B1 (ko) * 1999-12-30 2003-07-04 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조방법
US6414396B1 (en) 2000-01-24 2002-07-02 Amkor Technology, Inc. Package for stacked integrated circuits
US6377466B1 (en) * 2000-03-10 2002-04-23 Lucent Technologies Inc. Header, a method of manufacture thereof and an electronic device employing the same
JP3442721B2 (ja) * 2000-05-24 2003-09-02 沖電気工業株式会社 半導体装置
US6320128B1 (en) * 2000-05-25 2001-11-20 Visteon Global Technology, Inc. Environmentally-sealed electronic assembly and method of making same
US6664617B2 (en) * 2000-12-19 2003-12-16 Convergence Technologies, Ltd. Semiconductor package
US6731002B2 (en) 2001-05-04 2004-05-04 Ixys Corporation High frequency power device with a plastic molded package and direct bonded substrate
US6727585B2 (en) 2001-05-04 2004-04-27 Ixys Corporation Power device with a plastic molded package and direct bonded substrate
JP2003086970A (ja) * 2001-09-10 2003-03-20 Hitachi Unisia Automotive Ltd 電動機の駆動回路およびその組立方法
US6545716B2 (en) * 2001-09-13 2003-04-08 Tracey Gardiner Camera body for protecting components
KR20030054588A (ko) * 2001-12-26 2003-07-02 동부전자 주식회사 Tbga 반도체 패키지
JP2003229517A (ja) * 2002-01-31 2003-08-15 Fujitsu Hitachi Plasma Display Ltd 半導体チップ実装基板及びフラットディスプレイ
JP3803596B2 (ja) * 2002-03-14 2006-08-02 日本電気株式会社 パッケージ型半導体装置
US7161238B2 (en) * 2002-12-31 2007-01-09 Intel Corporation Structural reinforcement for electronic substrate
US7109732B2 (en) * 2003-07-31 2006-09-19 Endicott Interconnect Technologies, Inc. Electronic component test apparatus
JP2005280044A (ja) * 2004-03-29 2005-10-13 Brother Ind Ltd インクジェットヘッドの製造方法
KR100634379B1 (ko) * 2004-07-14 2006-10-16 삼성전자주식회사 반도체 패키지
US7135781B2 (en) * 2004-08-10 2006-11-14 Texas Instruments Incorporated Low profile, chip-scale package and method of fabrication
US8125076B2 (en) * 2004-11-12 2012-02-28 Stats Chippac Ltd. Semiconductor package system with substrate heat sink
US7968371B2 (en) * 2005-02-01 2011-06-28 Stats Chippac Ltd. Semiconductor package system with cavity substrate
US8067831B2 (en) * 2005-09-16 2011-11-29 Stats Chippac Ltd. Integrated circuit package system with planar interconnects
US9466545B1 (en) * 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
US8159828B2 (en) * 2007-02-23 2012-04-17 Alpha & Omega Semiconductor, Inc. Low profile flip chip power module and method of making
TWI360207B (en) * 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
US9059074B2 (en) * 2008-03-26 2015-06-16 Stats Chippac Ltd. Integrated circuit package system with planar interconnect
US8043894B2 (en) * 2008-08-26 2011-10-25 Stats Chippac Ltd. Integrated circuit package system with redistribution layer
KR200448519Y1 (ko) * 2009-04-28 2010-04-21 남동진 돌출형 ⅰc 패키지용 방열판
TWI456715B (zh) * 2009-06-19 2014-10-11 Advanced Semiconductor Eng 晶片封裝結構及其製造方法
TWI466259B (zh) * 2009-07-21 2014-12-21 Advanced Semiconductor Eng 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法
TWI405306B (zh) * 2009-07-23 2013-08-11 Advanced Semiconductor Eng 半導體封裝件、其製造方法及重佈晶片封膠體
US20110084372A1 (en) 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8372689B2 (en) * 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8320134B2 (en) * 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
JP5544950B2 (ja) * 2010-03-16 2014-07-09 カシオ計算機株式会社 半導体装置の製造方法及び半導体装置の実装方法
TWI411075B (zh) * 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
CN102790034A (zh) * 2011-05-17 2012-11-21 飞思卡尔半导体公司 具有散热器的半导体器件
JP6197619B2 (ja) * 2013-12-09 2017-09-20 富士通株式会社 電子装置及び電子装置の製造方法
SG10201810052WA (en) 2018-11-12 2020-06-29 Delta Electronics Int’L Singapore Pte Ltd Packaging process and packaging structure
TWI738596B (zh) * 2020-12-23 2021-09-01 頎邦科技股份有限公司 撓性半導體封裝構造

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE276387C (zh) * 1912-10-15
DE3235650A1 (de) * 1982-09-27 1984-03-29 Philips Patentverwaltung Gmbh, 2000 Hamburg Informationskarte und verfahren zu ihrer herstellung
GB2129223A (en) * 1982-10-09 1984-05-10 Welwyn Electronics Ltd Printed circuit boards
EP0116396A3 (en) * 1983-01-06 1985-11-06 Crystalate Electronics Limited Electrical assembly
GB2135521A (en) * 1983-02-16 1984-08-30 Ferranti Plc Printed circuit boards
JPS59198790A (ja) * 1983-04-26 1984-11-10 イビデン株式会社 プリント配線基板
US4890152A (en) * 1986-02-14 1989-12-26 Matsushita Electric Works, Ltd. Plastic molded chip carrier package and method of fabricating the same
US4766670A (en) * 1987-02-02 1988-08-30 International Business Machines Corporation Full panel electronic packaging structure and method of making same
JPH0777243B2 (ja) * 1987-03-19 1995-08-16 イビデン株式会社 表面実装用パツケ−ジ
US4993148A (en) * 1987-05-19 1991-02-19 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a circuit board
JPH0724291B2 (ja) * 1987-07-06 1995-03-15 住友金属工業株式会社 集積回路容器およびその製造方法
US4962416A (en) * 1988-04-18 1990-10-09 International Business Machines Corporation Electronic package with a device positioned above a substrate by suction force between the device and heat sink
DE3813565A1 (de) * 1988-04-22 1989-11-02 Bosch Gmbh Robert Elektrischer anschluss von hybridbaugruppen
US4868349A (en) * 1988-05-09 1989-09-19 National Semiconductor Corporation Plastic molded pin-grid-array power package
US5032543A (en) * 1988-06-17 1991-07-16 Massachusetts Institute Of Technology Coplanar packaging techniques for multichip circuits
US4992850A (en) * 1989-02-15 1991-02-12 Micron Technology, Inc. Directly bonded simm module
US5023202A (en) * 1989-07-14 1991-06-11 Lsi Logic Corporation Rigid strip carrier for integrated circuits
US5012386A (en) * 1989-10-27 1991-04-30 Motorola, Inc. High performance overmolded electronic package
US5045921A (en) * 1989-12-26 1991-09-03 Motorola, Inc. Pad array carrier IC device using flexible tape
JPH03212961A (ja) * 1990-01-18 1991-09-18 Matsushita Electric Works Ltd 半導体チップキャリア
US5095404A (en) * 1990-02-26 1992-03-10 Data General Corporation Arrangement for mounting and cooling high density tab IC chips
US5114880A (en) * 1990-06-15 1992-05-19 Motorola, Inc. Method for fabricating multiple electronic devices within a single carrier structure
JP2753767B2 (ja) * 1990-08-29 1998-05-20 イビデン株式会社 電子部品搭載用基板
JPH04180660A (ja) * 1990-11-15 1992-06-26 Matsushita Electric Works Ltd パワーデバイス実装板
JPH04256342A (ja) * 1991-02-08 1992-09-11 Toshiba Corp 半導体パッケージ
US5133118A (en) * 1991-08-06 1992-07-28 Sheldahl, Inc. Surface mounted components on flex circuits
US5263245A (en) * 1992-01-27 1993-11-23 International Business Machines Corporation Method of making an electronic package with enhanced heat sinking
US5220487A (en) * 1992-01-27 1993-06-15 International Business Machines Corporation Electronic package with enhanced heat sinking
US5262927A (en) * 1992-02-07 1993-11-16 Lsi Logic Corporation Partially-molded, PCB chip carrier package
US5278724A (en) * 1992-07-06 1994-01-11 International Business Machines Corporation Electronic package and method of making same
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
US5291062A (en) * 1993-03-01 1994-03-01 Motorola, Inc. Area array semiconductor device having a lid with functional contacts

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7495256B2 (en) 2002-10-18 2009-02-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor apparatus and fabrication method of the same
CN101562150B (zh) * 2002-10-18 2011-06-08 株式会社半导体能源研究所 半导体设备及其制作方法
CN100429769C (zh) * 2005-04-26 2008-10-29 株式会社东芝 用于带有排气孔的半导体封装体的方法和系统
CN100403532C (zh) * 2005-08-19 2008-07-16 南茂科技股份有限公司 散热型球格阵列封装结构
CN102651352A (zh) * 2011-02-25 2012-08-29 富士通株式会社 半导体装置、用于制造半导体装置的方法以及电子器件
US8866312B2 (en) 2011-02-25 2014-10-21 Fujitsu Limited Semiconductor apparatus, method for manufacturing the same and electric device
CN102651352B (zh) * 2011-02-25 2014-11-19 富士通株式会社 半导体装置、用于制造半导体装置的方法以及电子器件
US9177938B2 (en) 2011-02-25 2015-11-03 Fujitsu Limited Method for manufacturing semiconductor apparatus
CN106816419A (zh) * 2015-12-02 2017-06-09 联咏科技股份有限公司 薄膜上芯片封装
CN106816419B (zh) * 2015-12-02 2019-08-30 联咏科技股份有限公司 薄膜上芯片封装
US10770368B2 (en) 2015-12-02 2020-09-08 Novatek Microelectronics Corp. Chip on film package and heat-dissipation structure for a chip package
CN114530549A (zh) * 2022-04-20 2022-05-24 江苏芯德半导体科技有限公司 一种半导体结构及其制备方法

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TW258829B (zh) 1995-10-01
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GB9500965D0 (en) 1995-03-08
CN1095201C (zh) 2002-11-27
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US5519936A (en) 1996-05-28

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