CN1224299A - Digital signal source decoder of parallel decoding - Google Patents
Digital signal source decoder of parallel decoding Download PDFInfo
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- CN1224299A CN1224299A CN 98125273 CN98125273A CN1224299A CN 1224299 A CN1224299 A CN 1224299A CN 98125273 CN98125273 CN 98125273 CN 98125273 A CN98125273 A CN 98125273A CN 1224299 A CN1224299 A CN 1224299A
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Abstract
A digital signal source decoder with parallel decording function for digital video equipment features use of parallel decode to lower the frequency of digital signal source decoder and increase system stability, so it can be implemented by hardware. Several core decoding boards are used for parallel decoding of video input code stream. The additional memory on each board can prevent vector overrun, so parallelly processed images can be spliced without seam. Its advantages are reasonable structure and flexible control.
Description
The present invention relates to a kind of digital video decoder, particularly a kind of digital information source decoding device that is used for the parallel decoding of various digital-video equipments.
Digital information source decoding device is the visual plant in digital video field, and its general international standard is a Moving Picture Experts Group-2, and it is by ISO/IEC 13818 file descriptions.Because the video decoding process of defined is very complicated in the Moving Picture Experts Group-2, if adopt serial decode, the decoding operating frequency will be very high, and along with the raising of decoded image definition, the decoding operating frequency also can further improve.Therefore,, improve the stability of a system, must adopt parallel decoding in order to reduce the decoding operating frequency.Parallel decoding is meant decoded image is divided into several sections according to certain way, the video code flow of each parts of images is decoded by a decoding unit, finish decoding jointly by several decoding units at one time, and finally recover the full video image data the entire image video code flow.
The common dividing mode of parallel decoding mainly contains 3 kinds " cross " and divides, is divided into vertical bar and is divided into horizontal bar by vertical direction by horizontal direction, as shown in Figure 1.According to Moving Picture Experts Group-2, be the Slice head in the minimal head information of initial code, promptly can in code stream, find the Slice head at an easy rate by opening code.But the following structure of Slice does not all have opening code as Macroblock and Block, if want to find its starting position accurately, and must be through variable length decoding.Because variable length decoding is a complex decoding method comparatively in the video decoding process, also is the bottleneck of decode procedure medium velocity, should not adopt when code stream is divided.Therefore, comparatively simple code stream division methods is to divide by Slice.Owing to divide all necessary Slice of destruction structure by being divided into vertical bar and " cross " on the horizontal direction, perhaps can only be applicable to the specific coding device, therefore, these two kinds of methods all can not adopt.And be divided into several of level in vertical direction, shown in Fig. 1 (C), can carry out code stream according to the Slice structure fully divides, and each horizontal bar at most only has exchanges data with two adjacent with it horizontal bars, be convenient to motion vector and cross the solution of boundary's problem, so the present invention adopts the division methods that is divided into horizontal bar on the vertical direction.
The digital information source decoding device that the purpose of this invention is to provide a kind of parallel decoding, this decoder is used to reduce the digital information source decoding device operating frequency, improves the stability of a system; Simultaneously, solve motion vector well by annex memory and cross boundary's problem, realize the seamless link of decoding back image.
According to above-mentioned purpose, the digital information source decoding device of parallel decoding of the present invention comprises: demultiplexing unit, and the TS stream that will meet MPEG-2 system layer standard is decoded as video PES stream, audio frequency PES stream and auxiliary data PES stream; System control unit, the video PES stream of input is decoded as video-frequency basic flow, then, to be decoded into the Slice layer, value according to the upright position behind the Slice opening code (8bit), every frame video code flow is divided into several sections, delivers to respectively on several core codec plates with various decoding parametrics again; The core codec unit, this unit is made up of polylith core codec plate, and each core codec buttress carries out synchronous decoding to the video code flow of delivering on the plate respectively according to various decoding parametrics, finally obtains YUV video data; The display buffer unit, it is to put in order two field picture that yuv data is reconsolidated, and sends by demonstration; Post-processing unit, the YUV video data that the display buffer unit is exported carries out colourity interpolation, matrixing and D/A conversion, at last the analog rgb signal is outputed to display device, demonstrates the digital video image of recovery this moment on the display.
Bring motion vector to cross boundary's problem for solving by parallel decoding, increased annex memory on each core codec plate of core codec of the present invention unit, be used for the reference frame on each plate is deposited into the row expansion, cross boundary's problem, thereby realize the seamless link of decoding back image to solve motion vector.
The present invention has following advantage:
1, the present invention has adopted parallel decoding, can reduce the decoding operating frequency, improves the stability of system;
2, the present invention deposits into the row expansion by annex memory to the reference frame on each core codec plate, has solved motion vector well and has crossed boundary's problem;
3, the structure of each core codec plate of the present invention is identical, and work transmits thereby reduced the data on the system backplane synchronously, is convenient to the system hardware debugging.
Above-mentioned purpose of the present invention and other advantage will become apparent in the detailed description of reference the drawings and specific embodiments.Wherein:
Fig. 1 represents the dividing mode that parallel decoding is common;
Fig. 2 represents the digital information source decoding device block diagram of parallel decoding of the present invention;
Fig. 3 represents the block diagram of the annex memory on each core codec plate of the present invention;
Fig. 4 represents the block diagram of digital HDTV source decoder of the parallel decoding of one embodiment of the invention;
Fig. 5 represents in the digital HDTV source decoder block diagram of annex memory on the core decoding deck.
Fig. 2 represents the block diagram of the digital information source decoding device of parallel decoding of the present invention.In Fig. 2, this digital information source decoding device comprises: demultiplexing unit 1, system control unit 2, core codec unit 3, display buffer unit 4 and post-processing unit 5 etc.Wherein core codec unit 3 is by polylith core codec plate (1 ... n) form, every block of core codec plate is made up of video decode circuit and annex memory.1 pair of demultiplexing unit meets the TS stream of MPEG-2 system layer standard decodes, and it is decomposed into video PES stream, audio frequency PES stream and auxiliary data PES stream, and they are delivered to interface separately respectively.System control unit 2 will be finished the decoding to video PES stream, it is decoded as video-frequency basic flow, and send into input buffer.To be decoded into the Slice layer from the video code flow of input buffer output, and be worth according to the upright position behind the Slice opening code (8bit), the video code flow of every frame is divided into several sections, delivers to several core codec plates (1 respectively with various decoding parametrics then ... n) on.Several core codec buttresses in the core codec unit 3 carry out synchronous decoding to the video code flow of delivering on the plate respectively according to various decoding parametrics, and finally obtain YUV video data.These YUV video datas are except that delivering to display buffer unit 4, if present frame is I frame or P frame, then yuv data also will write the reference frame memory on the plate separately, as subsequently the P frame or the predictive frame of B frame.The YUV video data of delivering to display buffer will reconsolidate and be whole two field picture, and deliver to post-processing unit 5 according to DISPLAY ORDER, 5 pairs of YUV videos of post-processing unit carry out colourity interpolation, matrixing and D/A conversion, at last the analog rgb signal is outputed to monitor 6, demonstrate the digital video image of recovery this moment on the monitor 6.
Adopt parallel decoding can reduce the decoding operating frequency, improve the stability of a system, but also can bring motion vector to cross boundary's problem, promptly at the intersection of each plate, because movement in vertical direction vector, the reference data on this plate need to obtain from the reference frame memory of adjacent core codec plate.Do not cross boundary's problem if do not solve motion vector, wrong piece can occur, can't realize the seamless link of image, thereby influence picture quality at the intersection of each plate decoded picture.In order to address the above problem, in the present invention, at every block of core codec plate (1 ... n) all increased annex memory on, reference frame on each plate deposited into gone expansion, make every block of core codec plate (1 ... n) the reference frame memory of I/P frame video data on writing this plate that solves, the reference frame that also will write the adjacent core decoding deck is deposited in (annex memory).All there is adjacent core to separate the I/P frame data that decoding deck solves in the reference frame memory on every block of core codec plate like this, make that required reference data can find when the P/B frame was taken exercises compensation subsequently in the reference frame of this plate is deposited, thereby solved the problem that motion vector is crossed the boundary.The block diagram of annex memory as shown in Figure 3 on each core codec plate.
Among the present invention, because core codec unit 3 employed core codec plates (1 ... n) can be identical on hardware configuration, so each plate can fully synchronously carry out work, the sequential of dateout also can be in full accord on every block of plate.Like this, the exchanges data between each plate only need transmit decoded YUV video data, fully compatible write the address and control signal such as enable then need not mutual transmission.So, on system backplane, need not increase too many bus, only need on every decoding deck, reference frame to be deposited suitably expansion by annex memory, can solve the problem that motion vector is crossed the boundary, realize the seamless link of decoding back image.
Fig. 4 represents the block diagram of digital HDTV source decoder of the parallel decoding of one embodiment of the invention, and in the present embodiment, the input video form of digital HDTV is 1440 * 1152 (MP﹠amp; H1440L).The core codec unit of this digital HDTV source decoder is made up of nine blocks of core codec plates.The TS that meets MPEG-2 system layer standard that is input as of whole digital HDTV source decoder flows.Demultiplexing unit 41 is decomposed into TS stream video PES stream, audio frequency PES stream and data PES stream earlier, and video PES stream is delivered to system control unit 42.42 couples of video PES of system control unit stream is decoded, and will obtain video code flow and send into input buffer.Be decoded to the Slice layer from the video code flow of input buffer output, then according to the value of the upright position (8bit) of Slice opening code back, 72 Slice are divided into 9 equal portions, 1-8 Slice sends into core codec plate 1,9-16 Slice sends into the core codec plate 2 of core codec unit 43, by that analogy, 65-72Slice is delivered to the 9th block of core codec plate.Every block of core codec plate will synchronously be finished the decoding of 8 Slice according to various decoding parametrics, the yuv data that will solve is separately respectively delivered to display buffer unit 44 then, display buffer unit 44 synthesizes whole frame data with the YUV video data of 9 blocks of plates, and according to DISPLAY ORDER they is delivered to post-processing unit 45.45 pairs of YUV video datas of post-processing unit carry out colourity interpolation, matrixing and D/A conversion, at last the analog rgb signal are outputed to monitor 46, and can see the digital HDTV image that recover on the monitor this moment.
Generally speaking, the vertical motion vector hunting zone of digital HDTV is-64-+63.5 that like this, the structure chart of its annex memory as shown in Figure 5.Every block of core codec plate deposits in reference frame deposits except 8 Slice data of I/P frame that oneself is solved, also will store each 4 Slice data that upper and lower two blocks of adjacent with it core codec plates solve in annex memory respectively.Can guarantee like this can find needed reference frame data when the P/B frame is taken exercises compensation subsequently, cross boundary's problem thereby solve motion vector.
Claims (3)
1, a kind of digital information source decoding device that is used for the parallel decoding of various digital-video equipments is characterized in that, this decoder comprises:
Demultiplexing unit, the TS stream that will meet MPEG-2 system layer standard is decoded as video PES stream, audio frequency PES stream and auxiliary data PES stream;
System control unit, the video PES stream of input is decoded as video-frequency basic flow, then, to be decoded into the Slice layer, value according to the upright position behind the Slice opening code (8bit), the video code flow of every frame is divided into several sections, delivers to respectively on several core codec plates with various decoding parametrics again;
The core codec unit, this unit is made up of polylith core codec plate, and each core codec buttress carries out synchronous decoding to the video code flow of delivering on the plate respectively according to various decoding parametrics, finally obtains YUV video data;
The display buffer unit reconsolidates yuv data into whole frame image, hands over and sends according to DISPLAY ORDER;
Post-processing unit, the YUV video data that the display buffer unit is exported carries out colourity interpolation, matrixing and D/A conversion, at last the analog rgb signal is outputed to monitor, so that display demonstrates the digital video image of recovery.
2, according to the digital information source decoding device of the parallel decoding of claim 1, it is characterized in that the YUV video data that the core codec unit obtains is if current decoded frame is I frame or P frame, then yuv data also will write the reference frame memory on the plate separately, as subsequently the P frame or the predicted value of B frame.
3, according to the digital information source decoding device of the parallel decoding of claim 1, it is characterized in that, all increased annex memory on each core codec plate of core codec unit, the reference frame that is used on each plate deposits into the row expansion, cross boundary's problem to solve motion vector, thereby realize the seamless link of decoding back image.
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| CN 98125273 CN1110205C (en) | 1998-12-15 | 1998-12-15 | Digital signal source decoder of parallel decoding |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100499784C (en) * | 2004-10-26 | 2009-06-10 | 索尼株式会社 | Information processing apparatus and method |
| US7643558B2 (en) | 2003-03-24 | 2010-01-05 | Qualcomm Incorporated | Method, apparatus, and system for encoding and decoding side information for multimedia transmission |
| CN1906880B (en) * | 2004-01-28 | 2010-04-28 | 日本电气株式会社 | Content distribution method, encoding method, reception/reproduction method and device |
| CN101707720A (en) * | 2004-06-02 | 2010-05-12 | 松下电器产业株式会社 | Seamless switch among multiplexing random access units in multi-media stream at multi-angle perspective |
| CN101080925B (en) * | 2004-12-14 | 2010-08-18 | 三星电子株式会社 | Apparatus and method for demultiplexing in a digital broadcasting receiver |
| CN101902640A (en) * | 2009-05-27 | 2010-12-01 | 索尼公司 | Messaging device and method |
| CN102293008A (en) * | 2009-01-26 | 2011-12-21 | 汤姆森特许公司 | Method, apparatus and system for improving tuning in receivers |
| CN101198050B (en) * | 2007-12-29 | 2011-12-21 | 大地辰星科技发展(北京)有限公司 | Video data processing method and device |
| US8331445B2 (en) | 2004-06-01 | 2012-12-11 | Qualcomm Incorporated | Method, apparatus, and system for enhancing robustness of predictive video codecs using a side-channel based on distributed source coding techniques |
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1998
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| CN1795679B (en) * | 2003-03-24 | 2010-11-24 | 高通股份有限公司 | Method, apparatus and system for encoding and decoding side information for multimedia transmission |
| US7643558B2 (en) | 2003-03-24 | 2010-01-05 | Qualcomm Incorporated | Method, apparatus, and system for encoding and decoding side information for multimedia transmission |
| CN1906880B (en) * | 2004-01-28 | 2010-04-28 | 日本电气株式会社 | Content distribution method, encoding method, reception/reproduction method and device |
| US8379716B2 (en) | 2004-06-01 | 2013-02-19 | Qualcomm Incorporated | Method, apparatus, and system for enhancing robustness of predictive video codecs using a side-channel based on distributed source coding techniques |
| US8331445B2 (en) | 2004-06-01 | 2012-12-11 | Qualcomm Incorporated | Method, apparatus, and system for enhancing robustness of predictive video codecs using a side-channel based on distributed source coding techniques |
| CN101707720A (en) * | 2004-06-02 | 2010-05-12 | 松下电器产业株式会社 | Seamless switch among multiplexing random access units in multi-media stream at multi-angle perspective |
| CN101707720B (en) * | 2004-06-02 | 2013-01-23 | 松下电器产业株式会社 | Seamless switch among multiplexing random access units in multi-media stream at multi-angle perspective |
| CN101707702B (en) * | 2004-06-02 | 2013-01-23 | 松下电器产业株式会社 | Seamless switching between random access units multiplexed in a multi angle view multimedia stream |
| US8411759B2 (en) | 2004-06-02 | 2013-04-02 | Panasonic Corporation | Multiplexing apparatus and demultiplexing apparatus |
| CN100499784C (en) * | 2004-10-26 | 2009-06-10 | 索尼株式会社 | Information processing apparatus and method |
| CN101080925B (en) * | 2004-12-14 | 2010-08-18 | 三星电子株式会社 | Apparatus and method for demultiplexing in a digital broadcasting receiver |
| CN101198050B (en) * | 2007-12-29 | 2011-12-21 | 大地辰星科技发展(北京)有限公司 | Video data processing method and device |
| CN102293008A (en) * | 2009-01-26 | 2011-12-21 | 汤姆森特许公司 | Method, apparatus and system for improving tuning in receivers |
| CN102293008B (en) * | 2009-01-26 | 2016-11-09 | 汤姆森特许公司 | For improving the method, apparatus and system of the tuning in receiver |
| CN101902640A (en) * | 2009-05-27 | 2010-12-01 | 索尼公司 | Messaging device and method |
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