CN1226744A - 半导体制造过程中非保形器件层的平面化 - Google Patents

半导体制造过程中非保形器件层的平面化 Download PDF

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CN1226744A
CN1226744A CN98119767A CN98119767A CN1226744A CN 1226744 A CN1226744 A CN 1226744A CN 98119767 A CN98119767 A CN 98119767A CN 98119767 A CN98119767 A CN 98119767A CN 1226744 A CN1226744 A CN 1226744A
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CN1121716C (zh
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凯瑟琳·H·瓦里安
德克·托本
马修·森德尔巴赫
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International Business Machines Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step

Abstract

从形成于复杂图形之上的非保形器件层形成一基本上平面的表面,它包括带有窄间隙的窄图形和带有宽间隙的宽图形。在非保形层上沉积一保形层。该表面然后被抛光,以暴露宽图形上的非保形层。然后,用对非保形层具有选择性的蚀刻基本除去宽图形之上的非保形层。然后,除去保形层,暴露非保形层。和以前相比,现在的非保形层的厚度更加均匀。这就使抛光可以形成一平表面,其宽间隙内的表面凹隔减少了。

Description

半导体制造过程中非保 形器件层的平面化
本发明总体上涉及半导体制造,更具体地说,涉及用非保形膜沉积来获得一平表面。
在半导体制造过程中,在基底上形成绝缘层,半导体层和导电层。这些层被构图,以形成图形(feature)和间隔。图形和间隔的最小尺寸或特性尺寸(feature size)取决于光刻系统的分辨能力。图形和间隔被构图,以形成器件,如晶体管,电容器和电阻器。这些器件然后互连,以获得理想的电功能,形成集成电路(IC)。
在先进的IC设计中,不同的器件有形成不同规格的器件图形的不同要求。结果,器件层具有不同规格的图形和间隔,形成复杂的形貌。一介电材料(如氧化物)用于填充图形之间的间隔。这种材料典型地通过多种已知的化学汽相沉积来沉积。沉积的氧化物材料在下置器件层之上形成一保形层。所以,沉积的氧化物材料具有一形貌,它反应下置层的形貌,重新形成不是平的表面。然后,用化学机械抛光对不平的表面平面化,以产生一平表面。这正是所需要的,它允许形成另外的器件层,从而在其上形成另外的器件结构,所以,增加了器件的密度。
在先进的IC设计中,随图形尺寸的减小,图形之间的间隔变得越来越小,所以,得到高的高宽比率(aspect ratio)的图形。小的具有高的高宽比率的图形使得用传统的CVD技术填充间隔很困难。为了方便较小间隔的间隙填充,需要用氧化物的高密度等离子化学气相沉积(HDP-CVD,high densityplasma chemical vapour deposition)。
HDP-CVD氧化物形成一非保形层。非保形层有一非平表面,它不反应下置层的形貌。非保形层的厚度在宽器件图形之上较厚,而在窄器件图形之上较薄。这种形貌为形成平表面的传统的平面化技术带来困难。具体地说,因为在较宽器件图形上比在较窄器件图形上有更多量的沉积材料,这样会发生较窄器件图形的过腐蚀。这种过腐蚀反过来会影响较窄器件的性能,因此,降低了产量。
上述讨论证明需要在非保形层沉积以后获得一个平面,而不会产生一些器件图形的过腐蚀。
本发明涉及集成电路的制造。更具体地说,本发明提供了一种用于在沉积于复杂图形之上的非保形层上形成一平面的表面的方法,该平表面上包括带有窄间隙的窄图形和带有宽间隙的宽图形。该方法包括在基底的表面上沉积一非保形器件层,以填充窄和宽间隔。非保形器件层在宽图形上的厚度大于在窄图形上的厚度。一保形层沉积在非保形层之上,其中,下置非保形层的形貌反应在保形层的表面上。然后,用非保形层作停止层使基底表面平面化。平面化过程在保形层和非保形层之间产生一平表面,其中,宽图形上的非保形层被暴露。用对保形层具有选择性的蚀刻来基本除去宽图形上的非保形层(除了被保形层保护的宽图形的边缘处的小部分以外)。一抛光工艺(如CMP)产生一平表面,其上带有宽和窄图形的表面。该抛光产生了一基本是平的表面,其宽间隔中的凹陷表面减少了,因为宽图形上的非保形层基本被除去。
参考附图,通过下面的详细说明,就能更好地理解本发明,其中:
图1a-1g示出了本发明的一个实施例,用于在一保形膜上提供一平表面。
本发明在非保形层形成以后提供平的表面,而不产生一些器件图形的过渡腐蚀。为了方便对本发明的理解,结合形成隔离集成电路器件的浅沟槽隔离(STI,shallow trench isolation)来对本发明进行介绍。然而,很明显,本发明的范围更广,可以用来减少抛光处理的某些部分的过渡腐蚀。
图1a-1g示出了根据本发明的一个实施例,提供一平表面的工艺过程。参考图1a,示出了集成电路一部分的截面。这种集成电路包括随机存取存储器(RAM,random acess memory);动态随机存取存储器(DRAM,dynamicrandom acess memory);同步动态随机存取存储器(SDRAM,synchronousDRAM);和只读存储器(ROM,read only memory),其它集成电路包括专用集成电路(ASIC)或任意逻辑电路。典型地,多个集成电路并行地形成于一晶片之上。工艺结束以后,切割晶片,集成电路分成单个芯片。然后,组装芯片,形成最终产品,它们可以用于计算机系统、单元电话机、个人数字助手和其它电子产品中。然而,为了便于理解,通过集成电路的形成来介绍本发明。另外,集成电路可以处于工艺过程中的任一阶段。
提供一基底101,用于形成集成电路。基底101例如包括一硅晶片。其它的半导体基底,如砷化镓、锗、绝缘层上的硅(SOI,silicon on insulator)、或其它半导体材料也可以采用。基底可以或轻或重地掺杂具有预定电导率的掺杂剂,以获得理想的电性能。
如图所示,在基底表面上形成器件图形,例如被间隔115和130分开的台面110和112。尽管,如图所示,器件图形形成于硅基底内,基底本身可以包括彼此堆叠的器件层,为了方便讨论,这种堆叠的器件图形在这里称为基底。
在图示的实施例中,间隙代表形成STI的浅沟槽。STI隔开形成器件的有效器件区域,图中用台面表示,在此台面上形成器件。在一个集成电路中,器件元件一般尺寸有变化。结果,有效器件区域的大小也变化。如图所示,有效区域110为较窄的类型,而有效区域112为较宽的类型。另外,由于有效区域大小的变化,浅沟槽可以是相对较窄的类型115或较宽的类型130。有效面积和浅沟槽的实际大小并不关键。因为人们需要制造具有高部件密度的集成电路,所以窄类型典型地与最小图形尺寸(F)或基本图形尺寸(groundrule)对应,而宽类型与比最小图形尺寸大的规格对应。这样,基底的表面几何结构包括高度接近定值的有效区域110和112。有效区域的宽度,与隔离它们的沟槽一样,是变化的。
在台面的顶部提供一停止层140。停止层例如是用来为图形构图的硬掩模层。停止层还为后续处理起着抛光或蚀刻停止的作用。停止层包括这样一种材料,使得用来填充STI的材料可以相对于停止层的材料被有选择地除去。在一个实施例中,停止层包括氮化物。另外,在硅基底和氮化物层之间有一薄的氧化物层,以促进器件层之间的粘接。
沟槽和台面的形成是用传统的光刻和蚀刻技术实现的。这包括在覆盖基底的氮化物层的表面上沉积一光致抗蚀剂层。产生例如深紫外线(DUV,deepultra-violet)辐射的暴露源照射一包括所需图案的掩模。照射产生被投影或印制到基底表面的掩模的图象,用DUV辐射选择性地对光致抗蚀剂曝光。根据所用光致抗蚀剂是正性的还是负性的,在显影过程中去除光致抗蚀剂的曝光部分或者未曝光部分,以便有选择地暴露下面的基底的与浅沟槽区域对应的区域。然后,暴露区域通过反应离子蚀刻(RIE,reactive ion etching)腐蚀,形成台面110和112以及间隔115和130。
参考图1b,在基底的表面上形成一非保形层160。由于层160的非保形性,它在较宽有效区域112的表面上的厚度比在窄有效区域110的表面上的厚度大。所以,下置层的形貌不反应在沉积层160上。
在一个实施例中,非保形层包括通过利用高强度等离子源(HDP-CVD)的等离子增强化学气相沉积(PEVCD,plasma-enhanced chemical vapordeposifion)来沉积的氧化物。这种HDP-CVD技术采用感应耦合等离子源。HDP-CVD技术在Francombe著的“薄膜物理学”(Francombe,Physics of ThinFilm,Academic Press,1994)中作过描述,这里引以为参考。HDP-CVD沉积的氧化物充分填充沟槽,而不会产生空洞。提供好的间隙填充而无空洞的其它非保形层包括通过电子回旋加速器和螺旋波激励等离子技术形成的非保形层。这种技术在上面提到的Francombe的“薄膜物理学”中也作了介绍,这里引以为参考。
如图所示,HDP-CVD氧化物层的厚度足以完全填充浅沟槽,浅沟槽的填充还涂覆基底表面。从图中可以看出,HDP-CVD技术在阵列中提供了一独特的填充形状。在有效区域上面,HDP-CVD氧化物从浅沟槽中斜着伸出,在氧化物层涂在基底表面上时,形成基本为倾斜的边缘。如图所示,倾斜边缘在窄有效区域110之上形成小三角形结构163。宽有效区域112上的氧化物层160包括基本倾斜的互补边缘165和166,两者之间有一平的中间部分168。该区域的氧化物层比三角形结构163厚。有效区域上形成的独特的三角形结构是由于HDP-CVD工艺过程中发生的即时溅射(in-situ sputtering)所导致的。
但是,必须注意的是三角形的形成并不是关键的,图中只是作为实例示出。氧化物层在有效区域上是否形成三角形,也就是,两个互补倾斜边的交汇,取决于有效区域的宽度和氧化物层的厚度。有些窄有效区域可能不够窄,所以使互补边不能交汇。这样,氧化层的形状将是类似于位于宽有效区域上的部分的三角形,只不过其平面的中心部分较窄。
有利地,HDP-CVD提供了好的间隙填充,其具有充足的密度,以为后续处理步骤提供充足的湿蚀刻选择性。所以,HDP-CVD氧化物不需要约为台阶1.5倍的过填充,此过填充是非HDP-CVD氧化物所需要的。由于能够沉积较少量的材料,除去的也就少。所以,提高了生产率。
参考图1c,在层160上形成牺牲器件层170。牺牲器件层包括可以相对于非保形层160有选择地除去的材料。在一个实施例中,牺牲层包括多晶硅(poly),多晶硅通过化学气相沉积(CVD)沉积在表面上。如图所示,CVD在非保形层160上形成了一保形多晶硅层。多晶硅层的厚度足以使凹陷区域171中的多晶硅的上表面位于非保形层的最高区域175的上表面之上。
参考图1d,多晶硅层被对氧化物具有选择性的CMP平面化。CMP抛光首先除去多晶硅的凸起部分,从其上面除去材料。随着越来越多的材料从凸起部分上除去,多晶硅的表面变得更平。CMP工艺继续,直至凸起部分中的氧化物160的表面被暴露,所以,形成一平的上表面179。如图所示,平的上表面包括多晶硅和氧化物区域。
参考图1e,执行对多晶硅和氮化物具有选择性的各向异性蚀刻,以除去暴露的氧化物材料。蚀刻例如采用反应离子蚀刻。台面的表面上的氮化物层140起着蚀刻停止层的作用。由于反应离子蚀刻是各向异性的,被多晶硅保护的氧化物部分181仍然保留着。
在图1f中,反应离子蚀刻以后以例如干蚀刻除去多晶硅。这样就留下随宽有效区域112之上的氮化物层140一起暴露的非保形层。另外,氧化物栅栏(oxide fence)180保留在宽有效区域的旁边。从图中可以看出,在窄有效区域上面的区域需要去除的氧化物材料的相对量与在宽有效区域之上需要去除的氧化物材料的量大约相同。尽管栅栏181比三角形163高,但是,因为它们非常薄,所以很容易用CMP除去。这就使CMP可以使非保形层160的表面平面化,用氮化物140作抛光停止层,而不会过渡腐蚀窄有效区域110,如图1f所示。
平表面形成以后,氮化物被从台面的表面上除去。氮化物的除去是通过对硅具有选择性的例如湿蚀刻来实现的。这样可以形成一平表面,台面的顶部带有氧化物,从而,完成STI的形成。
在提供了包括允许器件隔离的STI区域的高度平面化表面以后,可以根据已知的IC技术进一步对IC进行处理。
至此,已根据各实施例具体示出并详细介绍了本发明,本领域的技术人员应当理解,在不背离本发明范畴的前提下可以对本发明进行修改和变化。如,本发明的实施例是根据用于绝缘和介电层的具体材料进行描述的。另外,开孔的直径可以根据具体应用而变化。本发明的范畴不是根据上面的描述而确定,而是根据所附权利要求和它们的等同物来确定的。

Claims (1)

1.一种在制造集成电路过程中用于使非保形膜平面化的方法,包括:
提供一基底,其中,基底的表面包括由窄间隙隔开的窄图形和由宽间隙隔开的宽图形;
在基底表面上沉积一非保形器件层,以填充窄和宽间隙,非保形器件层在宽图形上的厚度大于在窄图形上的厚度;
在非保形层上沉积一保形层,其中,下置非保形层的形貌反应在保形层的表面上;
使保形层平面化,用非保形层作为停止层,该平面化过程在保形层和非保形层之间形成一平表面,其中,宽图形之上的非保形层被暴露;
蚀刻非保形层,其对保形层具有选择性,除了宽图形的边缘处小部分被保形层保护外,宽图形上的非保形层都被除去;
用蚀刻除去保形层,蚀刻使非保形层保持在窄图形的表面上和宽图形的边缘的小部分上;和
用抛光来形成带有宽和窄图形表面的平的表面,其中,抛光产生一基本上平面的表面,其在宽间隙上的表面凹隔减少了,因为宽图形上的非保形层基本上被除去。
CN98119767A 1997-09-30 1998-09-28 在制造集成电路过程中用于使非保形层平面化的方法 Expired - Fee Related CN1121716C (zh)

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