CN1244037A - 半导体器件的制作方法 - Google Patents

半导体器件的制作方法 Download PDF

Info

Publication number
CN1244037A
CN1244037A CN99110621A CN99110621A CN1244037A CN 1244037 A CN1244037 A CN 1244037A CN 99110621 A CN99110621 A CN 99110621A CN 99110621 A CN99110621 A CN 99110621A CN 1244037 A CN1244037 A CN 1244037A
Authority
CN
China
Prior art keywords
film
substrate
layer
window
make
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN99110621A
Other languages
English (en)
Other versions
CN1156903C (zh
Inventor
格利高里·布莱克尔曼
拉纳斯·文卡拉曼
马修·托马斯·赫里克
辛迪·R·辛普森
罗伯特·W·费阿达里斯
蒂安·L·登宁
阿杰·吉恩
克里斯蒂纳·卡帕瑟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of CN1244037A publication Critical patent/CN1244037A/zh
Application granted granted Critical
Publication of CN1156903C publication Critical patent/CN1156903C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05546—Dual damascene structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01041—Niobium [Nb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Abstract

在衬底(10)上制作互连(60)。在一个实施例中,在衬底(10)上淀积粘合/势垒层(81)、铜合金引晶层(42)和铜膜(43),并对衬底(10)进行退火。在一个变通实施例中,在衬底上淀积铜膜,并对铜膜进行退火。在又一个实施例中,在衬底(10)上淀积粘合/势垒层(81)、引晶层(82)、导电膜(83)和铜合金帽膜(84),以形成互连(92)。淀积和退火步骤可以在普通的工艺平台上执行。

Description

半导体器件的制作方法
本发明一般涉及到半导体器件，更具体地说是涉及到半导体器件中的互连结构及其制作方法。
集成电路的尺寸被半导体器件制造厂家不断地做得越来越小。互连工艺特别是镶嵌互连技术的进展，是一个为了继续减小电路尺寸而被研究的领域。但互连尺寸的减小导致电路电流密度的相应增大，并引起电迁移问题。这会引起电路的电阻和可靠性随时间的不可逆的改变。
目前，铜被研究作为铝的替换来克服由于电流密度的增大而引起的问题。铜提供了优于铝的各种固有的优点，包括其较低的电阻率和改进了的抗电迁移性。但在先进的互连技术中采用铜作为替换，并不会完全消除电迁移问题。当互连尺寸继续缩小时，电迁移将继续成为可靠性的一个问题。
此外，使用铜来制作互连还引起有关可靠性的新问题。铜在含氧化物的膜以及诸如聚酰亚胺之类的钝化聚合物上的粘附性很差。这不仅在制作通孔和互连的过程中是一个问题，而且在装配和封装完成的半导体器件时也是问题。当采用基本上纯的铜膜来制作键合焊点时，已报道了有关粘附性的可靠性问题。其中包括由铜键合焊点与铜键合焊点上方的钝化膜部分之间的不良粘附引起的失效。
用举例的方法来说明本发明，本发明不局限于各个附图，在这些图中，相同的参考号表示相似的元件，其中：
图1示出了已局部处理来确定第一互连层的半导体器件一部分的剖面图；
图2示出了图1的衬底在制作粘合/势垒层和层间介质膜之后的剖面图；
图3示出了图2的衬底在制作层间介质膜中的双重镶嵌窗口之后的剖面图；
图4示出了图3的衬底在双重镶嵌窗口中淀积粘合/势垒层、引晶层和导电膜之后的剖面图；
图5示出了图4的衬底的剖面图，并进一步示出了为使来自引晶层的合金组分重新分布到导电膜中的退火步骤；
图6示出了图5的衬底在制作双重镶嵌互连结构之后的剖面图；
图7示出了图6的衬底在淀积第二层间介质膜之后和制作上部双重镶嵌窗口和单一镶嵌窗口之后的剖面图；
图8示出了图7的衬底在淀积粘合/势垒层、引晶层、导电膜和覆盖上部双重镶嵌窗口和单一镶嵌窗口的导电合金帽膜之后的剖面图；
图9示出了图8的衬底在制作双重镶嵌互连结构和键合焊点结构之后的剖面图；
图10示出了图9的衬底在制作钝化层和钝化层中暴露键合焊点部分的窗口之后的剖面图；
图11示出了图10的衬底在制作基本上完成了的器件之后的剖面图。
熟练技术人员知道，图中的元件是为了简单明了而示出的，没有必要按比例绘出。例如，为了有助于理解本发明的实施例，图中的某些元件的尺寸相对于其它元件进行了夸大。
在衬底上制作导电互连。在一个实施例中，在衬底上淀积粘合/势垒层、铜合金引晶层和铜膜，并进行退火。在一个变通实施例中，在衬底上淀积含铜的膜，并进行退火。在另一个实施例中，在衬底上淀积粘合/势垒层、引晶层、导电膜和铜合金帽膜。此实施例中的退火被可选地执行。可以在普通工艺平台上执行淀积和退火步骤。
图1示出了已局部处理来确定第一互连层的半导体器件。此半导体器件包含半导体器件衬底10、场隔离区102、晶体管118、导电塞112和介质层110。晶体管118包括掺杂区104、栅介质膜106和栅电极108。如本说明书所用的那样，半导体器件衬底10包含单晶半导体晶片、绝缘衬底上半导体、或任何其它用来制作半导体器件的衬底。
在一个实施例中，栅电极108是多晶硅层。作为变通，栅电极108可以是诸如钨或钼的金属层、诸如氮化钛、氮化钨的金属氮化物层和它们的组合。此外，栅电极108可以是多晶硅膜上的包含诸如硅化钨、硅化钛和硅化钴之类的金属硅化物的多硅化物(polycide)膜。
在制作栅电极108之后，在衬底10上制作第一层间介质(ILD)层110，并进行图形化以制作接触窗口。在一个实施例中，第一ILD层110是用四乙氧基硅烷(TEOS)作为源气体制作的等离子体淀积的氧化物膜。作为变通，第一ILD层110可以是氮化硅膜、磷硅酸盐玻璃(PSG)膜、硼磷硅酸盐玻璃(BPSG)膜、氮氧化硅膜、聚酰亚胺膜、低k介质或它们的组合。
在图形化之后，在介质层110中制作接触窗口。接触窗口包含用诸如钛/氮化钛(Ti/TiN)和钽/氮化钽(Ta/TaN)之类的粘合/势垒层114以及诸如钨的导电填充材料116形成的导电塞112。在淀积之后，用常规腐蚀或化学机械抛光技术清除部分导电填充材料116和下方的粘合/势垒层114，以形成导电塞112。作为变通，可以用掺杂的硅作为接触填充材料来制作具有或不具有粘合/势垒层114的导电塞112。
在制作导电塞112之后，在导电塞112和介质层110上制作第二粘合/势垒层122和第二导电膜124。在一个实施例中，用Ta/TaN制作第二粘合/势垒层122，并用铜、铝之类制作导电膜124。第二粘合/势垒层122和第二导电膜124的组合构成第一互连层12。直到工艺的这一时刻，都是使用常规方法来制作图1所示的器件。
然后如图2所示，在第一互连层12上制作钝化层21。在一个实施例中，钝化层21是等离子体淀积的氮化硅膜。作为变通，钝化层21可以是等离子体淀积的氮氧化硅膜、氮化硼膜之类。钝化层21被用来减小互连层12中的金属原子扩散进入随后淀积在互连层12上的介质膜中的可能性。例如，若互连层12包含铜，则钝化层21用作铜的扩散势垒。
图2还示出了制作在粘合/势垒层122上的层间介质层(ILD)20。在一个实施例中，层间介质层20包含介质膜22、中间腐蚀停止膜23、介质膜24和硬掩模膜25。
介质膜22可以是用TEOS作为源气体制作的等离子体淀积的氧化物膜。作为变通，介质膜22可以是PSG膜、BPSG膜、SOG膜、低介电常数(低k)绝缘体之类。为了本说明书的目的，低k绝缘体是介电常数低于大约3.5的材料。中间腐蚀停止膜23可以是等离子体淀积的氮氧化硅膜。作为变通，中间腐蚀停止膜23可以是等离子体淀积的氮化硅膜、氮化硼膜之类。介质膜24可以是用TEOS作为源气体制作的等离子体淀积的氧化物膜。作为变通，介质膜24可以是PSG膜、BPSG膜、SOG膜、低介电常数(低k)绝缘体之类。层间介质膜20不一定要用不同的介质材料制作。例如，可以用诸如等离子体淀积的氧化物、PSG、BPSG、SOG、聚酰亚胺、低介质绝缘体之类的单一介质材料来制作层间介质膜20。介质膜24上是硬掩模膜25。在一个实施例中，硬掩模膜25是等离子体淀积的氮氧化硅膜。作为变通，硬掩模膜25可以是等离子体淀积的氮化硅膜、氮化硼膜之类。
在图3中，部分层间介质层20和钝化层21被图形化以制作双重镶嵌窗口30。如图3所示，双重镶嵌窗口30包含互连部分31和通孔部分32，其中通孔部分32使部分导电互连12暴露。采用与先通孔后第一沟槽(VFTL)工艺相符的图形化工艺，在介质膜24被腐蚀以确定腐蚀停止膜23中的通孔窗口时，硬掩模膜25保护介质膜24，而在制作介质膜24中的双重镶嵌窗口的互连部分时，腐蚀停止膜23保护介质膜22。
在图4中，粘合/势垒层41被制作在双重镶嵌窗口30内。在一个实施例中，粘合/势垒层是氮化钽膜。作为变通，粘合/势垒层41可以是氮化钛膜、氮化钨膜、氮化钽硅膜、钽膜、钛钨膜之类。通常用常规溅射方法来淀积粘合/势垒层41.也可以用平行溅射(collimatedsputtering)、离化溅射或化学汽相淀积工艺来制作粘合/势垒层41。
然后，在粘合/势垒层41上制作引晶层42和导电膜43。在一个实施例中，引晶层42包含铜和镁。作为变通，可以使用包括铟、锡、铬、锌、碳、锆、钯、钛、铁、铌、镁之类的其它合金材料或合金材料的组合。在变通实施例中，引晶层42可以主要由诸如铜、镍、锡之类的单一元素组成。
制作引晶层42的各种方法互不相同。在一个实施例中，用物理汽相淀积(PVD)工艺，以包含大约2％原子比的镁和大约98％原子比的铜的溅射靶，来制作引晶层42。也可以用包括离化PVD、长投射(longthrow)PVD、或平行PVD的其它PVD工艺来淀积引晶层42，或者也可以用化学汽相淀积(CVD)工艺或诸如无电镀或电镀之类的镀敷工艺来淀积。引晶层42淀积成粘合/势垒层41上的连续膜，且制作在双重镶嵌窗口30中。在一个实施例中，引晶层42的淀积厚度约为150-250nm。但本技术领域的普通熟练人员了解，为了能够恰当地镀敷导电膜，引晶层必须制成足够厚，而为了防止引晶层42在双重镶嵌窗口30的角边上过量生长和在双重镶嵌互连窗口(30)的底部随后形成空洞，引晶层又必须足够薄。
导电膜43制作在引晶层42上。导电膜43具有足以完全填充双重镶嵌窗口30的厚度。在一个实施例中，导电膜是用常规电镀技术淀积的铜。铜被电镀到厚度约为600nm，这是双重镶嵌窗口沟槽部分厚度的大约1.5倍。作为变通，可以用包括无电镀、CVD、PVD、或CVD加PVD的组合的其它淀积工艺来制作导电膜43。
图5示出了在箭头45所示的退火步骤中的图4的结构。退火步骤使合金组分44从引晶层扩散进入导电膜43。合金组分44从引晶层42到导电膜43的扩散，导致合金组分44在整个引晶层42和导电膜43中的重新分布。根据所用的合金材料和退火条件，合金组分44的重新分布可以在整个引晶层42和导电膜43中是均匀的、在引晶层42中较高、或聚集于表面处和引晶层42与导电膜43的界面处。
由于退火以及合金组分44随后进入导电膜43，就潜在地出现了益处。这包括导电膜电阻特性及其粘附性的改善。退火改变了引晶层42和导电膜43的表面组成、形貌和内部微结构。保持在300℃以上的温度促使合金组分44迁移到表面和导电膜43的界面。当暴露于氧原子时，就形成合金-氧化物膜。此合金-氧化物膜促进了导电膜43和相邻的膜包括以后淀积的钝化层之间的粘附性。根据退火被用来扩散合金组分44的实施例，退火是大约300-450℃的炉子中执行20-30分钟。
为了改善互连的电迁移可靠性，也可以在不含合金的导电膜上执行退火。在用主要含有单一材料的势垒层和导电膜制作导电互连的实施例中，可以在大约200℃下对衬底退火大约5分钟。作为改进产出的一种方法，也可以在250-400℃范围内对衬底退火至少1分钟。为了尽可能减少暴露表面被氧化，可以在氮气氛、减压气氛或真空气氛中执行退火。在此实施例中，主要包含单一材料的导电膜的例子包括具有电镀铜膜的无电镀的铜引晶层、CVD淀积的铜膜之类。
正如用电阻和电迁移数据测得的参数测试表明，由于退火步骤而能够得到改善。薄膜电阻的降低、薄膜整个电阻分布的改善、以及有关电迁移性能的改善，被归咎于退火过程中铜膜的晶粒生长和致密化。在退火之前，铜的晶粒结构和晶粒取向在整个膜中是变化的。涉及到高度可变的晶粒结构和取向的不同的失效，都有助于引起电迁移失效。借助于对铜进行退火，膜中的晶粒结构分布更为均匀，且涉及到这些晶粒结构的电迁移的变化具有相应的更紧密的分布。
借助于在淀积导电膜之前对引晶层进行退火，可以相应地获得由于引晶层和导电膜退火而得到的益处。这可以用在大约200-400℃范围的温度下淀积引晶层的方法来原位执行。也可以在淀积导电层之前，用首先淀积引晶层，然后在大约200-400℃范围的温度下对其进行大约1-5分钟的退火的方法来执行。
根据本发明的实施例，可以用快速热退火(RTA)、热板、加热的吸盘或炉子来执行退火步骤。可以将退火站组合到工艺流程中作为整个设备的一部分，在这种情况下，引晶层淀积步骤、导电膜淀积步骤、施涂-清洗-干燥(SRD)、和退火步骤、或这些步骤的任何组合，都可以在单一的工艺平台上执行。同样，这些步骤可以当作单一晶片或批量晶片加工操作来执行。
在图6中，用常规化学机械抛光工艺清除部分导电膜43、引晶层42和粘合/势垒层41，以便在互连窗口30中制作互连60。作为变通，可以用诸如离子研磨、反应离子刻蚀和等离子体刻蚀之类的常规腐蚀技术，或用腐蚀与抛光技术二者的组合，来制作互连60。
在合金组分44被从引晶层42扩散进入导电膜43的实施例中，也可以在制作互连之后执行退火。在一个变通实施例中，在清除了部分导电膜43、引晶层42和粘合/势垒层41以形成互连之后，在大约300-450℃的温度下，在炉子中对衬底进行大约20-30分钟的退火。为了减小介质膜24和导电互连被氧化的可能性，在退火过程中可以使用诸如氩、氦、氮之类的较惰性的气氛。在退火过程中，合金组分从引晶层42扩散进入导电膜43。也可以用前面所述的快速热退火(RTA)、热板退火或炉子退火工艺来执行退火。这一退火步骤与前面所述退火的不同之处在于它是在制作导电互连的步骤之后执行的。但最终产品是与前面所述的互连60提供基本上相同的益处的导电互连。
图7进一步示出了半导体器件，现在包括钝化层70、层间介质层(ILD)77、和硬掩模层76。ILD层77进一步包括下介质膜71、中间腐蚀停止膜72和上介质膜73。钝化层70、ILD层77和硬掩模层76是用相似于用来制作钝化层21、ILD层20和硬掩模膜25的方法制作的。在硬掩模层76、ILD层77和钝化层70中已经制作了双重镶嵌窗口74，使部分互连60暴露出来。双重镶嵌窗口74是用相似于前面所述制作双重镶嵌窗口30的技术制作的。
根据本发明的一个实施例，在制作双重镶嵌结构74的过程中，也制作了单镶嵌窗口75。在一个实施例中，单镶嵌窗口75被用来形成半导体器件的键合焊点。在确定单镶嵌窗口75的腐蚀过程中，用来确定双重镶嵌窗口74的互连沟槽部分的腐蚀停止膜72也防止了部分下介质膜71被清除。
图8进一步示出了半导体器件衬底，现在包括粘合/势垒层81、引晶层82、完全填充双重镶嵌结构和部分填充单镶嵌结构的导电膜83、和导电合金帽膜84。在一个实施例中，粘合/势垒层81是氮化钽膜，并制作在硬掩模层76上和前面图7确定的双重镶嵌窗口74以及单镶嵌窗口75中。粘合/势垒层81也可以是氮化钨膜、氮化钽硅膜、钽膜、钽钨膜之类。可以用常规溅射或化学汽相淀积技术来淀积粘合/势垒层81。
在粘合/势垒层81上的是引晶层82。在此特定的实施例中，引晶层82是铜引晶层，并且是用PVD工艺淀积到厚度约为150-250nm。也可以用其它常规淀积方法将此引晶层82淀积成导电合金。合金材料的例子包括铟、锡、铬、锌、锆、钯、碳、钛、铁、铌之类。
在引晶层82上的是导电膜83。通常用电镀工艺来制作导电膜83。在此特定实施例中，导电膜83是电镀成厚度约为300-500nm的铜膜。也可以用PVD或CVD工艺来制作导电膜83，并可以用诸如铝或金之类的其它导电材料来制作。
根据本发明的实施例，导电膜的厚度足以填充双重镶嵌窗口74，但不完全填充单镶嵌窗口75。
参照图8，导电膜83的总厚度的一部分位于介质膜73最上层以下。未按比例绘出的单镶嵌窗口的横向尺寸明显地大于双重镶嵌窗口。例如，单镶嵌窗口的横向尺寸可以在25-50微米范围，而双重镶嵌窗口的尺寸小于大约0.35微米。单镶嵌窗口75由于如此之宽而只被局部地填充。
在导电膜83上的是导电合金帽膜84。根据本发明的一个实施例，导电合金帽膜84是制作在导电膜83上的铜镁合金。用PVD工艺以含有大约2.0％原子比的镁和98％原子比的铜的溅射靶，来淀积导电合金帽膜84。也可以用其它常规淀积技术以包括铟、锡、铬、锌、锆、钯、碳、钛、铁、铌之类的其它合金材料，来淀积导电合金帽膜84。如图8所示。导电合金帽膜84完全填充介质膜73顶部以下的单镶嵌结构部分。铜合金帽膜84淀积成完全填充原先未被导电膜83填充的单镶嵌窗口部分。
也可以用前面所述的PVD工艺来制作铜合金帽膜84，其中的工艺温度范围约为300-450℃。更高的温度会在单镶嵌结构以及双重镶嵌结构中促使合金元素扩散进入导电膜83，从而提供前面所述的电迁移和粘附性益处。为了得到相似的总体益处，在后续工艺步骤中，也可以对复合铜合金帽膜84和导电膜83进行退火。
在图9中，已经用常规化学机械抛光技术清除了部分导电合金帽膜84、导电膜83、引晶层82和粘合/势垒层81，以便制作双重镶嵌窗口74中的互连91和单镶嵌窗口75中的键合焊点92。也可以用诸如离子研磨、反应离子刻蚀和等离子体刻蚀之类的常规腐蚀技术，或用腐蚀与抛光技术的组合，来制作互连91和键合焊点92。
导电互连91包含导电粘合/势垒层81、引晶层82和导电膜83的剩余部分。键合焊点92包含导电粘合/势垒层81、引晶层82、导电膜83和导电合金帽膜84的剩余部分。
图10进一步示出了半导体器件，现在包括部分导电互连91上的额外钝化层1001、硬掩模层76和键合焊点92。在一个实施例中，钝化层1001包含10-20nm的等离子体增强氮化物(PEN)膜上的250-350nm的氮氧化硅膜。如图10所示，钝化层1001已经被腐蚀，以形成暴露部分键合焊点92的下窗口1002。用常规等离子体或湿法腐蚀工艺技术来腐蚀钝化膜。
图11进一步示出了半导体器件，现在包括钝化层1001上的聚酰亚胺膜1102。在一个实施例中，用常规的施涂工艺来制作聚酰亚胺膜，并淀积成厚度约为2.5-3.5微米。然后用常规工艺在聚酰亚胺膜中制作上窗口1103。根据本发明的实施例，如图11所示，上窗口1103大于下窗口1002。这些尺寸取决于半导体器件的设计与封装要求以及用来制作窗口的工艺和设备。部分钝化膜1001延伸到且覆盖键合焊点92中的部分导电合金帽膜84。然后在键合焊点92和部分钝化膜上制作导电互连凸块1104。导电凸块1104以后将提供从半导体器件到半导体封装件的连接。
导电合金帽膜84的存在，改善了钝化膜/键合焊点界面处钝化膜对键合焊点的粘附性。覆盖部分钝化膜1101的部分导电互连凸块1104，在钝化膜/键合焊点界面处更不容易剥层。因此，由于存在合金帽膜84而改善了管芯键合可靠性。这就改善了半导体器件的总的可靠性。
于是，根据本发明的实施例，显然至少已经提供了优越于现有技术的三个益处。这些益处包括改善了导电互连的电阻分布、改善了金属互连的电迁移性能、以及改善了互连对上方相邻薄膜的粘附性。
在前面的说明书中，已经参照具体的实施例描述了本发明。但本技术领域的一般熟练人员理解，能够作出各种修正和改变而不超越下列权利要求所列出的本发明的范围。因此，本说明书和附图被认为是说明性的而不是限制性的，且所有这些修正都被包括在本发明的范围之内。上面已经描述了关于具体实施例的益处、其它优点和问题的解决。但是，这些益处、优点、问题的解决、以及能够引起任何益处、优点、或解决发生或变得更为明显的因素，都不构成任何一个或全部权利要求的关键的、规定的或主要的特点或因素。

Claims (10)

1.一种半导体器件的制作方法，其特征是：
在衬底上制作势垒层；
在势垒层上制作引晶层，其中的引晶层包括铜合金；
在引晶层上制作导电膜；以及
对衬底进行退火。
2.一种半导体器件的制作方法，其特征是：
在衬底上制作势垒层，其中的衬底具有介质膜中的第一窗口，且介质膜具有第一顶表面；
在势垒层上制作导电膜；
在导电膜上制作帽膜，其中的帽膜包括铜合金；以及
清除部分势垒层、导电膜和帽膜，以便确定第一镶嵌结构，其中的第一镶嵌结构具有第二顶表面，且其中的第二顶表面与第一顶表面基本共面，并包括部分帽膜。
3.权利要求2的方法，其进一步特征是第二窗口，其中的第二窗口小于第一窗口，且其中形成导电膜基本上填充第二窗口。
4.权利要求1或2的方法，其中的铜合金包括选自镁、铟、铬、钯、钛、铁、碳、铌、锆和锡构成的组中的元素。
5.权利要求1或2的方法，其中的导电膜包括铜。
6.权利要求1或2的方法，其进一步特征是将合金元素扩散进入导电膜。
7.一种半导体器件的制作方法，其特征是：
在衬底上制作主要含铜的膜，以便基本上填充窗口；以及
对衬底进行退火，其中在主要含铜的膜上制作绝缘层之前执行退火。
8.权利要求7的方法，其中制作主要含铜的膜和对主要含铜的膜进行的退火，在同一个工艺步骤中发生。
9.一种半导体器件的制作方法，其特征是：
在衬底上制作第一主要含铜的膜，其中的衬底在介质膜中具有窗口；
对第一主要含铜的膜进行退火；
在衬底上制作第二主要含铜的膜；以及
清除部分第一和第二主要含铜的膜，以确定镶嵌结构。
10.一种半导体器件的制作方法，其特征是：
提供具有镀敷室和退火室的平台；
用镀敷室将材料镀敷在衬底上；以及
用退火室对材料进行退火。
CNB991106210A 1998-07-21 1999-07-20 半导体器件的制作方法 Expired - Lifetime CN1156903C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/121,068 US6218302B1 (en) 1998-07-21 1998-07-21 Method for forming a semiconductor device
US09/121,068 1998-07-21

Publications (2)

Publication Number Publication Date
CN1244037A true CN1244037A (zh) 2000-02-09
CN1156903C CN1156903C (zh) 2004-07-07

Family

ID=22394305

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB991106210A Expired - Lifetime CN1156903C (zh) 1998-07-21 1999-07-20 半导体器件的制作方法

Country Status (5)

Country Link
US (1) US6218302B1 (zh)
JP (1) JP3588275B2 (zh)
KR (1) KR100647995B1 (zh)
CN (1) CN1156903C (zh)
TW (1) TW504753B (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1296997C (zh) * 2000-12-28 2007-01-24 因芬尼昂技术北美公司 具自行钝化铜合金之铜垫\接合\铜线
CN1319146C (zh) * 2001-10-26 2007-05-30 应用材料公司 作为用于铜金属化的阻挡层的原子层沉积氮化钽和α相钽
CN102197478A (zh) * 2008-08-21 2011-09-21 泰瑟拉互连材料公司 具有用键合层接合到其上的金属柱的微电子衬底
CN102903666A (zh) * 2011-07-25 2013-01-30 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
US8668776B2 (en) 2001-10-26 2014-03-11 Applied Materials, Inc. Gas delivery apparatus and method for atomic layer deposition
CN103797566A (zh) * 2011-09-28 2014-05-14 美光科技公司 形成贯穿衬底的导通体的方法
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10535626B2 (en) 2015-07-10 2020-01-14 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles

Families Citing this family (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100404649B1 (ko) * 1998-02-23 2003-11-10 가부시끼가이샤 히다치 세이사꾸쇼 반도체장치 및 그 제조방법
JP2000111952A (ja) * 1998-10-07 2000-04-21 Sony Corp 電気光学装置、電気光学装置用の駆動基板、及びこれらの製造方法
JP2000150647A (ja) * 1998-11-11 2000-05-30 Sony Corp 配線構造およびその製造方法
US7405149B1 (en) * 1998-12-21 2008-07-29 Megica Corporation Post passivation method for semiconductor chip or wafer
US6965165B2 (en) * 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
KR100280288B1 (ko) * 1999-02-04 2001-01-15 윤종용 반도체 집적회로의 커패시터 제조방법
US6218317B1 (en) * 1999-04-19 2001-04-17 National Semiconductor Corp. Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration
JP2000349085A (ja) 1999-06-01 2000-12-15 Nec Corp 半導体装置及び半導体装置の製造方法
US6319834B1 (en) * 1999-08-18 2001-11-20 Advanced Micro Devices, Inc. Method and apparatus for improved planarity metallization by electroplating and CMP
US7388289B1 (en) 1999-09-02 2008-06-17 Micron Technology, Inc. Local multilayered metallization
US6165891A (en) * 1999-11-22 2000-12-26 Chartered Semiconductor Manufacturing Ltd. Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer
FR2805084B1 (fr) * 2000-02-14 2003-09-26 St Microelectronics Sa Procede de fabrication de pistes metalliques pour des circuits integres
US6373137B1 (en) * 2000-03-21 2002-04-16 Micron Technology, Inc. Copper interconnect for an integrated circuit and methods for its fabrication
US6559070B1 (en) * 2000-04-11 2003-05-06 Applied Materials, Inc. Mesoporous silica films with mobile ion gettering and accelerated processing
US6309959B1 (en) * 2000-08-03 2001-10-30 Advanced Micro Devices, Inc. Formation of self-aligned passivation for interconnect to minimize electromigration
US6392922B1 (en) 2000-08-14 2002-05-21 Micron Technology, Inc. Passivated magneto-resistive bit structure and passivation method therefor
US6534394B1 (en) * 2000-09-13 2003-03-18 International Business Machines Corporation Process to create robust contacts and interconnects
US6373135B1 (en) * 2000-09-14 2002-04-16 Infineon Technologies Ag Semiconductor structure and method of fabrication
US6635564B1 (en) * 2000-09-14 2003-10-21 Infineon Technologies Ag Semiconductor structure and method of fabrication including forming aluminum columns
US6498397B1 (en) * 2000-11-06 2002-12-24 Advanced Micro Devices, Inc. Seed layer with annealed region for integrated circuit interconnects
US6503641B2 (en) * 2000-12-18 2003-01-07 International Business Machines Corporation Interconnects with Ti-containing liners
JP3954312B2 (ja) * 2001-01-15 2007-08-08 ローム株式会社 半導体装置の製造方法
US6951804B2 (en) * 2001-02-02 2005-10-04 Applied Materials, Inc. Formation of a tantalum-nitride layer
US6677679B1 (en) * 2001-02-06 2004-01-13 Advanced Micro Devices, Inc. Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers
US6534863B2 (en) * 2001-02-09 2003-03-18 International Business Machines Corporation Common ball-limiting metallurgy for I/O sites
KR100550505B1 (ko) * 2001-03-01 2006-02-13 가부시끼가이샤 도시바 반도체 장치 및 반도체 장치의 제조 방법
US6348407B1 (en) * 2001-03-15 2002-02-19 Chartered Semiconductor Manufacturing Inc. Method to improve adhesion of organic dielectrics in dual damascene interconnects
US6566242B1 (en) * 2001-03-23 2003-05-20 International Business Machines Corporation Dual damascene copper interconnect to a damascene tungsten wiring level
US6448177B1 (en) 2001-03-27 2002-09-10 Intle Corporation Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure
JP2002324797A (ja) * 2001-04-24 2002-11-08 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6528412B1 (en) * 2001-04-30 2003-03-04 Advanced Micro Devices, Inc. Depositing an adhesion skin layer and a conformal seed layer to fill an interconnect opening
US6391777B1 (en) * 2001-05-02 2002-05-21 Taiwan Semiconductor Manufacturing Company Two-stage Cu anneal to improve Cu damascene process
US6426293B1 (en) * 2001-06-01 2002-07-30 Advanced Micro Devices, Inc. Minimizing resistance and electromigration of interconnect by adjusting anneal temperature and amount of seed layer dopant
JP2003068740A (ja) * 2001-08-30 2003-03-07 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6485989B1 (en) 2001-08-30 2002-11-26 Micron Technology, Inc. MRAM sense layer isolation
US7780785B2 (en) * 2001-10-26 2010-08-24 Applied Materials, Inc. Gas delivery apparatus for atomic layer deposition
DE10154500B4 (de) * 2001-11-07 2004-09-23 Infineon Technologies Ag Verfahren zur Herstellung dünner, strukturierter, metallhaltiger Schichten mit geringem elektrischen Widerstand
US7932603B2 (en) 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
US7096581B2 (en) * 2002-03-06 2006-08-29 Stmicroelectronics, Inc. Method for providing a redistribution metal layer in an integrated circuit
US6656836B1 (en) * 2002-03-18 2003-12-02 Advanced Micro Devices, Inc. Method of performing a two stage anneal in the formation of an alloy interconnect
TWI300971B (en) * 2002-04-12 2008-09-11 Hitachi Ltd Semiconductor device
US6783995B2 (en) * 2002-04-30 2004-08-31 Micron Technology, Inc. Protective layers for MRAM devices
CN1462069A (zh) * 2002-05-31 2003-12-17 松下电器产业株式会社 布线结构的形成方法
JP4605995B2 (ja) * 2002-06-13 2011-01-05 パナソニック株式会社 配線構造の形成方法
CN1248304C (zh) * 2002-06-13 2006-03-29 松下电器产业株式会社 布线结构的形成方法
JP4555540B2 (ja) 2002-07-08 2010-10-06 ルネサスエレクトロニクス株式会社 半導体装置
KR100434511B1 (ko) * 2002-08-12 2004-06-05 삼성전자주식회사 다마신 배선을 이용한 반도체 소자의 제조방법
US6740956B1 (en) 2002-08-15 2004-05-25 National Semiconductor Corporation Metal trace with reduced RF impedance resulting from the skin effect
US6864581B1 (en) 2002-08-15 2005-03-08 National Semiconductor Corporation Etched metal trace with reduced RF impendance resulting from the skin effect
US6703710B1 (en) * 2002-08-15 2004-03-09 National Semiconductor Corporation Dual damascene metal trace with reduced RF impedance resulting from the skin effect
US6853079B1 (en) 2002-08-15 2005-02-08 National Semiconductor Corporation Conductive trace with reduced RF impedance resulting from the skin effect
US6830971B2 (en) * 2002-11-02 2004-12-14 Chartered Semiconductor Manufacturing Ltd High K artificial lattices for capacitor applications to use in CU or AL BEOL
US6674168B1 (en) * 2003-01-21 2004-01-06 International Business Machines Corporation Single and multilevel rework
JP2004304167A (ja) 2003-03-20 2004-10-28 Advanced Lcd Technologies Development Center Co Ltd 配線、表示装置及び、これらの形成方法
EP1610376B1 (en) * 2003-03-28 2014-10-15 Fujitsu Semiconductor Limited Semiconductor device
US7675174B2 (en) * 2003-05-13 2010-03-09 Stmicroelectronics, Inc. Method and structure of a thick metal layer using multiple deposition chambers
US7112454B2 (en) * 2003-10-14 2006-09-26 Micron Technology, Inc. System and method for reducing shorting in memory cells
US7009280B2 (en) * 2004-04-28 2006-03-07 International Business Machines Corporation Low-k interlevel dielectric layer (ILD)
JP2005019979A (ja) * 2004-05-31 2005-01-20 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
TWI331370B (en) * 2004-06-18 2010-10-01 Megica Corp Connection between two circuitry components
US20060001170A1 (en) * 2004-07-01 2006-01-05 Fan Zhang Conductive compound cap layer
US7157378B2 (en) * 2004-07-06 2007-01-02 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US7122458B2 (en) * 2004-07-22 2006-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating pad redistribution layer
TWI240977B (en) * 2004-07-23 2005-10-01 Advanced Semiconductor Eng Structure and formation method for conductive bump
KR20060089635A (ko) * 2005-02-04 2006-08-09 가부시키가이샤 에키쇼센탄 기쥬쓰 가이하쓰센타 구리 배선층의 형성방법
US7422979B2 (en) * 2005-03-11 2008-09-09 Freescale Semiconductor, Inc. Method of forming a semiconductor device having a diffusion barrier stack and structure thereof
KR101288790B1 (ko) * 2005-09-27 2013-07-29 에이저 시스템즈 엘엘시 플립 칩 반도체 디바이스들을 위한 솔더 범프 구조 및 이의제조 방법
EP2221864B1 (en) * 2005-12-02 2018-04-11 Ulvac, Inc. Method for forming Cu film
US7635643B2 (en) * 2006-04-26 2009-12-22 International Business Machines Corporation Method for forming C4 connections on integrated circuit chips and the resulting devices
US8592977B2 (en) * 2006-06-28 2013-11-26 Megit Acquisition Corp. Integrated circuit (IC) chip and method for fabricating the same
US7585758B2 (en) * 2006-11-06 2009-09-08 International Business Machines Corporation Interconnect layers without electromigration
JP4506767B2 (ja) * 2007-02-28 2010-07-21 カシオ計算機株式会社 半導体装置の製造方法
CN101874296B (zh) 2007-09-28 2015-08-26 泰塞拉公司 利用成对凸柱进行倒装芯片互连
JP2008252103A (ja) * 2008-04-21 2008-10-16 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
CN101630667A (zh) * 2008-07-15 2010-01-20 中芯国际集成电路制造(上海)有限公司 形成具有铜互连的导电凸块的方法和系统
US20100155949A1 (en) * 2008-12-24 2010-06-24 Texas Instruments Incorporated Low cost process flow for fabrication of metal capping layer over copper interconnects
US20100212017A1 (en) * 2009-02-18 2010-08-19 International Business Machines Corporation System and method for efficient trust preservation in data stores
JP2011009439A (ja) * 2009-06-25 2011-01-13 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
US8610283B2 (en) * 2009-10-05 2013-12-17 International Business Machines Corporation Semiconductor device having a copper plug
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US8722530B2 (en) 2011-07-28 2014-05-13 Freescale Semiconductor, Inc. Method of making a die with recessed aluminum die pads
WO2013063260A1 (en) * 2011-10-28 2013-05-02 Applied Materials, Inc. High temperature tungsten metallization process
US8659173B1 (en) 2013-01-04 2014-02-25 International Business Machines Corporation Isolated wire structures with reduced stress, methods of manufacturing and design structures
US9136166B2 (en) * 2013-03-08 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and methods of making same
CN103700648B (zh) * 2013-12-18 2016-09-07 无锡中微晶园电子有限公司 用于高温电路的金属互连结构及制备方法
JP6424610B2 (ja) * 2014-04-23 2018-11-21 ソニー株式会社 半導体装置、および製造方法
EP3034655A1 (en) * 2014-12-19 2016-06-22 ATOTECH Deutschland GmbH Trench pattern wet chemical copper metal filling using a hard mask structure
KR102420586B1 (ko) 2017-07-24 2022-07-13 삼성전자주식회사 반도체 장치, 반도체 패키지 및 반도체 패키지의 제조 방법
US10818627B2 (en) * 2017-08-29 2020-10-27 Advanced Semiconductor Engineering, Inc. Electronic component including a conductive pillar and method of manufacturing the same
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
KR102294868B1 (ko) 2019-10-02 2021-08-26 심재훈 릴 낚시대를 이용한 스풀낚시
KR20220056309A (ko) * 2020-10-27 2022-05-06 삼성전자주식회사 반도체 패키지

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5169680A (en) 1987-05-07 1992-12-08 Intel Corporation Electroless deposition for IC fabrication
JPH02143429A (ja) 1988-11-24 1990-06-01 Toshiba Corp 半導体装置及びその製造方法
GB2233820A (en) 1989-06-26 1991-01-16 Philips Nv Providing an electrode on a semiconductor device
US5130274A (en) 1991-04-05 1992-07-14 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
US5243222A (en) 1991-04-05 1993-09-07 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
US5747360A (en) 1993-09-17 1998-05-05 Applied Materials, Inc. Method of metalizing a semiconductor wafer
US5622608A (en) 1994-05-05 1997-04-22 Research Foundation Of State University Of New York Process of making oxidation resistant high conductivity copper layers
JP3391933B2 (ja) 1995-04-27 2003-03-31 沖電気工業株式会社 半導体素子とその製造方法
JPH0964034A (ja) 1995-08-18 1997-03-07 Toshiba Corp 半導体装置およびその製造方法
US5824599A (en) * 1996-01-16 1998-10-20 Cornell Research Foundation, Inc. Protected encapsulation of catalytic layer for electroless copper interconnect
US5674787A (en) 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
US5891513A (en) * 1996-01-16 1999-04-06 Cornell Research Foundation Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications
US5677244A (en) * 1996-05-20 1997-10-14 Motorola, Inc. Method of alloying an interconnect structure with copper
US5933758A (en) * 1997-05-12 1999-08-03 Motorola, Inc. Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer
US5821168A (en) * 1997-07-16 1998-10-13 Motorola, Inc. Process for forming a semiconductor device
US5939788A (en) * 1998-03-11 1999-08-17 Micron Technology, Inc. Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with cooper

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1296997C (zh) * 2000-12-28 2007-01-24 因芬尼昂技术北美公司 具自行钝化铜合金之铜垫\接合\铜线
CN1319146C (zh) * 2001-10-26 2007-05-30 应用材料公司 作为用于铜金属化的阻挡层的原子层沉积氮化钽和α相钽
US8668776B2 (en) 2001-10-26 2014-03-11 Applied Materials, Inc. Gas delivery apparatus and method for atomic layer deposition
CN102197478A (zh) * 2008-08-21 2011-09-21 泰瑟拉互连材料公司 具有用键合层接合到其上的金属柱的微电子衬底
CN102903666A (zh) * 2011-07-25 2013-01-30 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
TWI469258B (zh) * 2011-09-28 2015-01-11 Micron Technology Inc 形成貫穿基板之通道的方法
CN103797566A (zh) * 2011-09-28 2014-05-14 美光科技公司 形成贯穿衬底的导通体的方法
CN103797566B (zh) * 2011-09-28 2018-06-15 美光科技公司 形成贯穿衬底的导通体的方法
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9818713B2 (en) 2015-07-10 2017-11-14 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10535626B2 (en) 2015-07-10 2020-01-14 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10892246B2 (en) 2015-07-10 2021-01-12 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US11710718B2 (en) 2015-07-10 2023-07-25 Adeia Semiconductor Technologies Llc Structures and methods for low temperature bonding using nanoparticles

Also Published As

Publication number Publication date
TW504753B (en) 2002-10-01
US6218302B1 (en) 2001-04-17
KR100647995B1 (ko) 2006-11-23
JP2000049229A (ja) 2000-02-18
JP3588275B2 (ja) 2004-11-10
CN1156903C (zh) 2004-07-07
KR20000011786A (ko) 2000-02-25

Similar Documents

Publication Publication Date Title
CN1156903C (zh) 半导体器件的制作方法
US5525837A (en) Reliable metallization with barrier for semiconductors
JP3955386B2 (ja) 半導体装置及びその製造方法
US6399496B1 (en) Copper interconnection structure incorporating a metal seed layer
CN100424867C (zh) 集成电路的内连线结构
US6294836B1 (en) Semiconductor chip interconnect barrier material and fabrication method
US5130274A (en) Copper alloy metallurgies for VLSI interconnection structures
CN2720637Y (zh) 内联机结构
US6506668B1 (en) Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability
CN101051631A (zh) 集成电路的内联机结构、镶嵌式结构以及半导体结构
CN1708846A (zh) 用于在具有帽盖层的半导体互连结构上沉积金属层的方法
KR100712358B1 (ko) 반도체 소자의 다마신 배선 형성 방법 및 그에 의해 형성된다마신 배선 구조체
TWI232523B (en) Damascene process and structure thereof
US6075293A (en) Semiconductor device having a multi-layer metal interconnect structure
CN1298052C (zh) 具有Cu互连的半导体器件及其制造方法
US7800229B2 (en) Semiconductor device and method for manufacturing same
CN1360346A (zh) 电子结构及其形成方法
US7875978B2 (en) Metal line having a multi-layered diffusion layer in a semiconductor device and method for forming the same
KR100924556B1 (ko) 반도체 소자의 금속배선 및 그 형성방법
US5948705A (en) Method of forming interconnection line
KR100701673B1 (ko) 반도체 소자의 구리 배선 형성방법
US6661097B1 (en) Ti liner for copper interconnect with low-k dielectric
US7067917B2 (en) Gradient barrier layer for copper back-end-of-line technology
KR20000044849A (ko) 반도체 소자의 구리 합금 배선 형성 방법
JP3594888B2 (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: FREEDOM SEMICONDUCTORS CO.

Free format text: FORMER OWNER: MOTOROLA, INC.

Effective date: 20040813

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20040813

Address after: Texas in the United States

Patentee after: FreeScale Semiconductor

Address before: Illinois Instrunment

Patentee before: Motorola, Inc.

C56 Change in the name or address of the patentee

Owner name: FISICAL SEMICONDUCTOR INC.

Free format text: FORMER NAME: FREEDOM SEMICONDUCTOR CORP.

CP01 Change in the name or title of a patent holder

Address after: Texas in the United States

Patentee after: FREESCALE SEMICONDUCTOR, Inc.

Address before: Texas in the United States

Patentee before: FreeScale Semiconductor

CP01 Change in the name or title of a patent holder

Address after: Texas in the United States

Patentee after: NXP USA, Inc.

Address before: Texas in the United States

Patentee before: FREESCALE SEMICONDUCTOR, Inc.

CP01 Change in the name or title of a patent holder
CX01 Expiry of patent term

Granted publication date: 20040707

CX01 Expiry of patent term